JPS63104166A - Inter-processor data transfer system for parallel processors - Google Patents

Abstract

PURPOSE:To add the new information to a message at a transfer route by forming this route with a multi-stage switch module having at least one stage and rewriting a part of an input message into the new information by means of each switch module to transmit this information to an output message. CONSTITUTION:A transfer route 2 set among processors 1-1-1-4 is formed with multi-stage switch modules 2-1-2-6. When a message is sent to a processor #11 from a processor #00, a message 3 is first produced in the processor 1-1. The address field 3-1 of the message 3 contains 2 bits, for example, and a binary number 11 is set in this field 3-1. The data to be transferred and the transfer information are set in a data field. The message 3 is sent to the switch module 2-1 through a line l10 as long no busy signal is received from the module 2-1 via a line l30. Each switch module has a switching action with the address of a single bit. A redundant stage 2-1 or 2-2 uses an optional address as the switch information together with a 2nd stage 2-3 or 2-4 using the higher order bit of an address field in a message and a 3rd stage 2-5 or 2-6 using a lower order bit respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a particularly efficient inter-processor data transfer system in a parallel processor composed of a plurality of processors.

[Conventional technology]

In a parallel processor consisting of multiple processors, a message transfer method is known as an inter-processor data transfer method in which a message is constructed by combining sending light information such as the destination processor number and the data to be transferred, and this message is transferred. It is being Note that the data to be transferred here means data in a broad sense, and includes everything other than the light transmission information in the message (for example, tag information).

(including data identification information, etc.).

Message formats include, for example, Hardware Design of Sigma-1, Data Flow Computers for Science, Contributions, Proceedings, I.C.P.
P (1984) pp. 524-531 (A h
ardware designof Sigma-1
, A Data-flow computer for
scientific computations,
Proc, ICPP, 524-531, 1984)
It is on page 525 of .

In the message transfer method, the message actively moves toward the destination processor on the transfer path between processors based on the light transmission information that the message itself has. Therefore, the message transfer method is an effective method in which the arithmetic processing on the processor and the message transfer between the processors can be performed independently, so that the transfer processing can be separated from the arithmetic processing.

Further, the transfer paths between the processors are generally designed to have redundancy from the viewpoint of reliability or efficiency. In other words,
The transfer route to the destination processor is not uniquely determined, but multiple routes are prepared.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, all messages are composed of a sending processor, and the transfer route only sends the message to the destination processor based on the optical transmission information in the message.

Therefore, adding information that occurs during the transfer route to the message is not considered, and information that cannot be incorporated into the message by the sending processor (for example, the transfer route has redundancy, that is, there are multiple routes that the message can take,
Message route information when the route to take is determined dynamically, or the number of times a message is forced to wait if the route conflicts with another message in the network)
could not be notified to the destination processor.

The purpose of the invention is to make it possible to add new information to messages within the forwarding path.

[Means to solve problems]

In order to achieve the above object, the transfer path is constructed of one or more multi-stage switch modules, and each switch module is provided with means for rewriting a part of an input message with new information and sending it as an output message.

For example, the new information includes information such as (]) the input position when a message is input to the switch module, or (2) the waiting time when a wait occurs due to a message conflict in the switch module.

The above example (1) is used when there is redundancy in the transfer route. The source processor creates a message from the destination processor number 10 and transfers data to 7.

When this message is sent to the transfer path, the message sent from the transfer path to the destination processor is output with dynamic path information added.

In example (2) above, when a conflict occurs in a switch module, the waiting time is written into the message, so if a conflict occurs again in a subsequent switch module, the priority of the message can be determined based on this waiting time. Can be done.

[Effect]

When a message passes through a transfer path having a redundant route, the means for replacing the sending light information such as the destination processor number in the transfer route with the transit route information operates after the route through which the message passes is determined. Therefore, the message reaches the destination processor without getting lost on the transfer route, and at that time, the message receives route information that it has passed in place of the information about the destination processor that is no longer needed.

Furthermore, even when a meeting occurs due to a message conflict in the switch module, the number of meetings increases, which makes it a priority demon, and the next time a conflict occurs, it becomes easier to pass through preferentially.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a parallel processor system in which processors are connected by redundant transfer paths (having a plurality of paths) using the present invention.

In the figure, 1-1 to 1-4 are processors that independently execute instructions, and 2 is an inter-processor message transfer path, which is composed of a plurality of switch modules 2-1 to 2-6. Q10 to Q25 are message transfer paths, and Q30 to Ω45 are busy signal lines for stopping the transmission of a previous message when a message conflict occurs in the switch module and a message is waited for. 3 to 6 hold a transfer destination processor number field, a data field containing data and transfer information (for example, an identifier of the transfer data, a command to the transfer destination processor, a storage location of the transfer data in the transfer destination processor), and a transfer route. field and (meeting)
This figure shows an inter-processor transfer message (hereinafter abbreviated as message) consisting of fields that hold count data.

The processor numbers are expressed in binary numbers for convenience. Further, although the data transmitting side processor and the data receiving side processor are illustrated separately, they are actually the same.

Although the parallel processors of this embodiment assume four processors, the number of processors may be any number. Also,
The switch module constituting the inter-processor transfer path 2 was assumed to be powered by two people and has two outputs, but it has n inputs and n outputs (
A switch module with n≧2) may be used. Furthermore, although one redundant stage is provided, it is not necessary to provide a redundant stage, or conversely, more stages may be provided.

As a specific example, processor #00 to processor #11
Consider sending a message to.

First, message 3 is configured in processor #OO1-1. Address field 3-1 of message 3 consists of 2 bits (because the number of processors is 4).
, the binary number 11 is set. The data field contains
Set the data to be transferred and transfer information. Three bits are reserved for the route field including the redundant stage.

The count data field is set to 0.

Unless a busy signal is received from the switch module 2-1 through 1130, the configured 3 is sent to the switch module 2-1 through Q10.

Here, the general operating specifications of the switch modules 2-1 to 2-6 are shown. Each switch module performs switching using a 1-bit address.

Redundant stages 2-1 and 2-2 have any address, second stage 2
-3 to 2-4 use the upper bits of the intra-message address field, and third stages 2-5 to 2-6 use the lower bits of the intra-message address field as switch information. Whether the switch module uses the upper bits, the lower bits, or neither of the address fields is determined when the parallel processor system is configured and is set in each switch module.

As in this embodiment, when the message 3 is sent to the switch module 2-1, since the switch module 2-1 is a redundant stage, there is no switching information and the message is output to the non-conflicting output light. Here, it is output to Ω15. At this time, since message 3 is input from α10, 0 is written to the first bit of the route field.

Also.

This switch module is a redundant stage, so no contention occurs.
The count data field remains O.

Message 4 on α15 becomes an input to switch module 2-4. This time, the upper bits of address field 4-1 are used as switching information. As a result, message 5 is output on A21. At this time, since message 4 is input from 915, O is written to the second bit of the route field. Also, if a message is being sent from the other input at the same time in this switch module, and the output lights match and the message from A15 is in the waiting state, the count data field will be 1.
becomes. Then, it is sent to 1l121 at the primary timing.

Message 5 on +221 is switch module 2-6
becomes the input. This time, the lower bits of address field 6-1 are used as switching information. the result,
Message 6 is output on A25. At this time, since message 5 is input from Ω21, 1 is written in the third bit of the route field. Also, even if messages are being sent from the other input at the same time in this switch module and the output lights match, the input message from 1221 is once in a waiting state at the previous stage and the count data is 1. It is preferentially sent to Ω25. Of course, if the value of the count data in the message from the other side is 2 or more, the input message from 121 goes into a waiting state, counts up the count data from 1 to 2, and sends it to A25 at the next timing. .

The message on A25 is taken into processor #111-4. At this time, the route field 6-5 becomes 001, and the switch module passing through can be determined. In addition, the count data field shows the number of times that a message conflict caused a wait.

Next, details of the switch module will be described using FIG. 2.

In the figure, 7 and 8 indicate message input registers, and 50
51 to 51 are decoders; 52 is an address bit instruction that specifies bits to be extracted from the address field; 53;
54 to 54 are incrementers, 55 are comparators, 58 to 59 are NOT gates, 62 to 63 are OR gates, 56 is a priority information generation circuit, 64, 65
90 to 90 indicate selectors, 68 to 69 message output registers, and 66 to 67 busy signal input registers, respectively.

Messages fetched from 119-1221 are stored in input registers 7-8.

Address fields 7-1 to 8-1 in the message
is sent to decoders 50 and 51. At this time, the address bit instruction 52 knows that the switching of the switch module 2-6 uses the lower bits of the address field, and instructs the decoder to decode the desired bit.

Further, the messages on registers 7 and 8 are sent to selectors 64 and 65 respectively, and the information decoded by U decoders 50 and 51 is A72. A74 to A73. It is sent to message selection circuits 60 and 61 via f175.

The message selection circuits 60 and 61 are further provided with a busy signal sent via input registers 66 and 67, and a message selection circuit A83.
The priority information becomes input information through.

The message selection circuit 60 selects which one of the two input messages to the output register 68.
, A24, it is determined whether to send it to the next 2×2 switch or the destination processor.

First, the output a indicates which message from the input registers 40 or 41 has been selected, and controls the selector 64. It is also set to 68-3 in the output register, and is written to part of the route field 68-3 in the message on the output register.

Next, the output bo or bl is set when a busy signal is received from Q44 or when a conflict occurs in message transfer, causing the message on the input register or 8 to wait. This busy signal activates incrementers 53-54 and counter data fields 7-4.
Increment the value of 8-4 by 1.

Here, generation of priority information will be explained.

First, count data fields 7-4 and 8-4 in input registers 7 and 8 are sent to comparator 55. If either one is larger, that information is sent as priority information to the message selection circuits 60-61 via selectors 90-91. If the values in the count data fields match, the information generated by the priority generation circuit 56 is sent to the message selection circuits 60 to 61 via the selectors 90 to 91. The priority generation circuit 56 includes a register 57 and a NOT circuit 5.
8, and is configured so that the cycle priority changes.

〔Effect of the invention〕

According to the present invention, new information can be added to a message within the transfer path. By using this invention, for example, the following effects can be obtained. It is possible to notify the destination processor of the transfer route information through which the message has passed. Forwarding route information includes: (1) If the forwarding route has redundancy, that is, there are multiple routes, information about which route the message took, and (2) @If the message collided with another message on the reverse route and was forced to wait. waiting time information, (3
) If a message undergoes error detection/correction, etc. on a transfer route, its position within the transfer route is considered, and this information is used as data to improve the performance or reliability of the transfer route.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a parallel processor, and FIG. 2 is a transfer route selection circuit. 1-1 to 1-4...processor, 2-1 to 2
-4...2 human power 2 output switch module, 60 or 61...Message selection circuit, 63...Ply right 1 diagram

Claims (1)

[Scope of Claims] 1. A plurality of processors, a message consisting of destination information such as a destination processor number and data to be transferred, a message transfer path connecting the processors, and a message transfer path between the processors using the message. A parallel processor equipped with a message transfer means for transferring data, characterized in that the message transfer path is provided with means for removing unnecessary information from the message or adding new information. Inter-processor data transfer method 2, 1st
In the parallel processor described in Section 1, the transfer path is composed of one or more stages of multi-stage switch modules, and each switch module is provided with means for removing unnecessary information from the input message of the switch module, adding new information, and sending it out as an output message. An inter-processor data transfer method for parallel processors. 3. The parallel processor according to item 1, wherein the message transfer path is provided with means for replacing destination information such as a destination processor number in a message with source information such as a source processor number. Inter-processor data transfer method. 4. In the parallel processor of item 1, there is provided means for preparing a plurality of routes for sending a message to a destination processor in the transfer route, and means for adding to the message transfer route a route through which the message has passed in the message. An inter-processor data transfer method for parallel processors characterized by: 5. A parallel processor consisting of a plurality of processors, a shared memory consisting of a plurality of memory modules, and a transfer path connecting the plurality of processors and the plurality of memory modules, wherein data on the shared memory is transferred from the processor to the shared memory. When reading data, the processor sends only the address of the data to the transfer path, and the transfer path adds the request source processor number to the address and sends a data read request to the memory module indicated by the part of the address. An inter-processor data transfer method for parallel processors, characterized in that a data transfer method is provided.