JPS63103528A - Switching control system for time slot assign table - Google Patents

Abstract

PURPOSE:To attain switching simultaneously at transmission and reception sides synchronously by providing a switch control bit in a frame and adding switching information to the switch control bit and sending the result to the receiving side at the switching of a time slot assign table at the sending side. CONSTITUTION:The switch control bit (SW bit) to indicate from which frame the switching of a time slot assign table (TS table) is caused is provided to each frame. When the SW bit is at a high level, the TS table A is in use and when the bit is at a low level, the TS table B is in use. This is indicated by the SW bit. The SW bit is inverted from a high to a low level at a frame where the TS table in use is switched from the TS table A into the TS table B at the sending side. The reception side always monitors the SW bit and when the inversion of the SW bit is detected, the TS table in use is switched from the table A to B from the frame.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention provides a time slot assignment table indicating the correspondence between time slots on a low-speed line and a high-speed multiplex line in a time division multiplex transmission system. The present invention relates to a time slot assignment table switching control method that simultaneously switches the time slot assignment table in synchronization with the receiving side.

[Conventional technology]

In general, the time division multiplex transmission method multiplexes a plurality of low-speed lines into a high-speed multiplex line for transmission. FIG. 3 shows an example of a network configuration using a time division multiplex transmission method. The communication control device 1 and the time division multiplexing device 2 are connected to a low-speed line CH,,CHZ.
...CH, and the time division multiplexer 2 is connected to the opposing time division multiplexer 4 via a high speed multiplex line 3, and the time division multiplexer 4 is connected via a low speed line CH,, CH2.
. . , terminal devices A, , A, . . . 80 are connected via CH, .

In such a network, data signals from the communication control device 1 are transmitted through low-speed lines CH,,CH,...CHf1.
is input to the time division multiplexer 2 from
ACH1, CH2...CH7 to terminal device A,,A,
, . . . A, .

At this time, it is necessary to set a time slot assignment table (hereinafter referred to as TS table) to which low-speed line the time slot in the multiplex frame of the high-speed multiplex line 3 is assigned. Division multiplexer 2
, 4 must match.

[Problem that the invention seeks to solve]

Generally, when changing the accommodation of low-speed lines, etc., T
If it is necessary to change the S table, if the TS tables are not switched in synchronization between the multiplexers, another low-speed line may be connected between the multiplexers.
There is a drawback that transmission errors occur.

This situation will be explained in detail below. - For example, as shown in Table 1, T
It is assumed that the S table (A) is set in the time division multiplexer 2 on the transmitting side and the time division multiplexer 4 on the receiving side.

Table 1 2 TS table (A) The time division multiplexer 2.4 on the transmitting and receiving side is the TS table (A)
When using the time division multiplexing device 2 on the transmitting side, the time division multiplexing device 2 on the transmitting side transmits a TS that indicates the correspondence between the low-speed lines CH,, CH2, --CHn and the time slots (numbers 1 to n) on the high-speed multiplex line 3.
According to table (A), the transmitting side low-speed line CH,,CH
2...CH is divided into time slots on the high-speed multiplex line 3, and information on the transmitting side is time-division multiplexed to form a frame, which is a unit of information transmission, and is transmitted to the high-speed multiplex line 3.

On the other hand, the time division multiplexer 4 on the receiving side divides the time slots on the high speed multiplex line 3 into low speed lines CH1, CH2, . . . CI according to the TS table (A). and transmits the information to the respective terminal devices A+, Az, . . . 80. In this case, the transmitted and received frames have the configuration shown in FIG. 4Ll). That is, for time slot numbers 1 to n,
Channels CH, , CH, , CH2, . . . , CH, are time-division multiplexed in this order.

After setting the TS table (A), there is a change in the accommodation of the low-speed line, and the TS table used by the dual division multiplexers 2 and 4 changes from the TS table (A) in Table 1 to the TS table (B) shown in Table 2. ) shall be changed.

Table 2 2 TS Table (B) There is no problem if the switching from TS table (A) to l'S table (B) is performed simultaneously and synchronously on the transmitting side and the receiving side. If there is a delay in switching the TS table, the transmitting side transmits according to the TS table (B) (frame structure shown in FIG. 3(b)), and the receiving station receives according to the TS table (A). This causes erroneous connection of the transmission line and transmission errors.

An object of the present invention is to eliminate such drawbacks, to perform TS table switching simultaneously on the transmitting side and the receiving side in synchronization, and to provide Tile, Slot, and 7+-assignment table switching control for normal transmission. The goal is to provide a method.

[Means for Solving Problem c] The present invention enables the transmitting side and the receiving side using a time division multiplex transmission system to synchronize time slot assignment tables showing the correspondence between time slots on low-speed lines and high-speed multiplex lines. This is a time slot assignment table switching method in which a switching control bit is provided in a frame on a high-speed multiplex line on the transmitting side, and switching information is added to the switching control bit when switching the time slot assignment table on the transmitting side. The receiving side detects the switching information (length) from the received switching control bits and switches the time slot assignment table on the receiving side.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a time chart diagram for explaining one embodiment of the present invention. In this embodiment, a case will be described in which the TS table is switched from TS table (A) to TS table (B). Note that it is assumed that the TS table to be used is switched in synchronization with the frame cycle.

According to the time slot assignment table switching control method of this embodiment, a switching control bit (hereinafter referred to as SW bit) is provided for each frame to indicate from which frame the TS table switching occurs.

The SW bit indicates that the TS table (A) is used when it is "high" and that the TS table (B) is used when it is "low".

On the sending side, the TS table used is TS table (A)
The SW bit is inverted from "high" to "low" in the frame switched from to the TS table (B). The receiving side constantly monitors this SW bit, and when it detects an inversion of the SW bit, it changes the TS table to be used from that frame (
Switch from A) to (B).

Figure 1(a) shows the frame, TS table, and SW on the transmitting side.
This is a time chart showing the relationship between bits. On the transmitting side, #1 frame and #2 frame are stored in the TS table (
After A) is transmitted, the TS table (A) is switched to the TS table (B) and frames #3, #4, and #5 are transmitted. At this time, the SW bit is switched from "high" to "low" in frame #3.

On the receiving side, as shown in Figure 1(b), this S
The W bit is monitored, and since the SW bit of frames #1 and #2 are "high", they are received in TS table A, but in frame #3, the SW bit changes from "high" to "low". Therefore, the TS table is switched from (A) to (B) and received, and the subsequent #4 frame and #5 frame are also received using the TS table (B).

In this way, on the transmitting side, by switching the TS table, “
A SW bit whose state changes between "high" and "low" is provided in each frame, and by constantly monitoring this SW bit on the receiving side, it is possible to detect an inversion of the SW bit and switch the TS table in synchronization.

If we consider a general transmission path, there is a problem in that if an error occurs in reception SW bit detection due to a bit error in the transmission path, the TS table will be erroneously switched, resulting in a misconnection or error in the channel.

Another embodiment of the present invention that can avoid the occurrence of such a problem will be described based on the time chart of FIG. 2. According to the time slot assignment table switching control method of this embodiment, a plurality of bits are used as SW bits, and the TS table to be used is switched by a counting method. As shown in FIG. 2, it is assumed that the TS table is switched in frame #6. On the transmitting side, when switching the TS table for #6 frame, the SW bit count value is 4 for #1 frame and #2 frame, the SW bit count value is 3 for #3 frame, and the SW bit count value for #4 frame. The value is 2, and by setting the count value of the SW bit to 1 in frame #5, the SW bit is counted down sequentially, and the count value of the SW bit in frames after frame #6 is set to 0.

On the receiving side, this SW bit is monitored and #1 frame, #
In frame 2, 4 counts of SW bits are detected, in frame #3, 3 counts, in frame #4, 2 counts,
1 count is detected in #5 frame. The count value of the SW bit becomes O in frame #6. As a result, the receiving side knows that the TS table will be switched from frame #6, and can switch the TS table in synchronization with the transmitting side.

Here, it is assumed that the received bit of the #5 frame has an error, as shown in the count value of the received SW bit detected on the receiving side shown in FIG. 2 (indicated by an X in the figure). In this case, the count value of the SW bit of frame #4, which is the previous frame, is 2, and the count value of the SW bit of frame #6, which is the subsequent frame, is 0, so on the receiving side, #
It is possible to estimate that the correct count value of the SW bit of the 5th frame is 1 and to correct it. Based on the modified receive SW bit count value, the receiving side determines that the count value has become O in frame #6, and starts T from frame #6.
Perform S table switching.

In this way, in this embodiment, when there is an error in the received SW bit, if the difference between the SW bit count values of the frames before and after the frame having the SW bit is 2, the correct count value is estimated. TS table switching can be performed correctly.

〔Effect of the invention〕

As explained above, according to the time slot 1-assignment table switching control method of the present invention, when it becomes necessary to switch the TS tables on the transmitting side and the receiving side due to changes in accommodation of low-speed lines, etc., the TS tables can be switched synchronously. Therefore, it is possible to prevent incorrect channel connections or signal errors from occurring.

Furthermore, even if a random error occurs in the transmission path, this effect can be avoided and synchronized TS tables can be switched.

[Brief explanation of the drawing]

FIG. 1 is a time chart diagram showing one embodiment of the present invention; FIG. 2 is a time chart diagram showing another embodiment of the present invention; FIG. 3 is a conventional time division multiplex transmission system. Block Diagram FIG. 4 is a configuration diagram of a frame. 1...Communication control device 2.4...Time division multiplexer 3...High speed multiplex line

Claims (1)

[Claims] (1) The transmitting side and the receiving side using the time division multiplex transmission method,
This is a time slot assignment table switching method that synchronously switches the time slot assignment table that shows the correspondence between the time slots on a low-speed line and a high-speed multiplex line, and on the transmitting side, a switching control bit is inserted in the frame on the high-speed multiplex line. When switching the time slot assignment table on the transmitting side, switching information is added to the switching control bits and transmitted to the receiving side, and the receiving side detects the switching information from the received switching control bits and uses the switching information on the receiving side. A time slot assignment table switching control method characterized by switching a time slot assignment table.