JPS6298842A - Packet switching system - Google Patents

Abstract

PURPOSE:To evade the access competition without raising the input speed of a buffer memory higher than an input circuit speed by providing a buffer memory in correspondence to an output circuit so as to divide it into banks on the share of the number of input circuits, and connecting the input circuit to the buffer memory through a switch every time the transfer request of a packet is issued. CONSTITUTION:If packets PKi and PKj requesting transmission to the same output circuit OUTK (K<n) comes in from the input circuits INi and INj, the packets PKi and PKj are transferred to the banks BMi and BMj of the buffer memory belonging to the output circuit OUTK through a bus in a switch SW set by a decoder part DEC. Accordingly, in order to evade the access competition to the buffer memory or merely access competition multifunction is provided in correspondence to the input circuit, whereby the acceleration of an input to the buffer memory caused by connecting input and output sides through a bus multiplexed in terms of time division can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packet switching system that divides data into blocks of a certain length called packets and exchanges them in units of blocks.

[Conventional technology]

Generally, in a packet switching system that sends packets arriving from multiple incoming lines to a predetermined outgoing line, a buffer memory is provided for each outgoing line, and an input line is used to make the buffer memory accessible from multiple incoming lines. When a line and a buffer memory are bus-coupled, access contention occurs due to the arrival of packets requesting transmission from a plurality of incoming lines to the same outgoing line at the same time.

FIG. 2 is a block diagram showing a conventional packet switching system that takes measures to avoid such access conflicts.

In the same figure, I N+, I Nz, "・, I N-
is m input lines, MUX is a time division multiplexing unit, BUS is a bus, BM is a buffer memory, OUT + , OTJ
T z , '・, I○UT, is 0 outgoing lines, BMC
is a buffer memory control unit that performs control to select a predetermined time slot in the buffer memory BM in response to a connection destination request of an input packet.

In other words, in the conventional system shown in FIG. 2, a time division multiplexing unit MUX is provided for large lines, and a bus BUS is time-divided into time slots corresponding to the number of incoming lines.
X and a buffer memory BM corresponding to the outgoing line are connected.

This conventional switching system has the drawback that the transfer speed between the MUX and the BM becomes (incoming line speed x number of lines), and the faster the number of incoming lines increases, the more complicated the processing becomes.

[Problem that the invention seeks to solve]

Therefore, the present invention aims to solve the problem of making it possible to avoid access contention without increasing the input speed of the buffer memory over the input line speed when accessing the buffer memory from the input line in a packet switching system. There is. It is therefore an object of the invention to provide a packet switching system that makes the above possible.

[Means and effects for solving the problems] The present invention has the following features:
In conventional packet switching systems, the buffer memory provided for outgoing lines is divided into banks for the number of incoming lines, and the incoming lines are connected to each bank via a bus set by a switch. Main characteristics. It can be said that the difference from the prior art is that by dividing the buffer memory in this way, there is no need to multiplex data from a plurality of input lines.

〔Example〕

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, SW is a switch, DET is a detection unit for a connection destination request field in an input packet, DEC is a decoder unit that instructs to set a predetermined bus within the switch S field in response to a connection destination request, and B M,, B Mz,...
, BM are buffer memories divided into banks, SEL is a selector for selecting data to be sent to the outgoing line from m banks, and I N l + I Nz.

,,=, I N, is m incoming lines, oUTl, 0UT
2911. .

OUT is 0 outgoing lines.

Next, the circuit operation will be explained. In FIG. 1, the buses in the switch S field set by the outputs 1, 2, 3.4 of the decoder section DEC are 1', 2', 3'.

4'. With this structure, the incoming line I
N4. A packet (PKi, PK
When the packet PK1.j'') arrives, the packet PK1.
PKJ as the bank BM of the buffer memory belonging to the outgoing line 0UTK.

It can be transferred to BMJ.

The effect of this is the access contention to the buffer memory that occurs when using a conventional system in which there is only one input to the buffer memory without dividing the buffer memory into banks, or multiplexing to support large lines to avoid access contention. With this function, it is possible to avoid an increase in the speed of input to the buffer memory caused by connecting the input side and the output side with a time-division multiplexed bus.

〔Effect of the invention〕

As explained above, according to the present invention, a buffer memory is provided for each outgoing line, and the buffer memory is further divided into banks corresponding to the number of incoming lines, and each time a packet transfer request is made, the buffer memory is connected to the incoming line via a switch. By connecting the to the buffer memory divided into banks, multiple packets that are requested to be sent to the same outgoing line can be transferred to the buffer memory without access contention and without increasing the input speed of the buffer memory over the incoming line speed. It has the advantage of being possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional packet switching system. Explanation of symbols I Nl, I N2+"・+ I Nll-... Input line, OUT, 0UTz,..., OUT,... Output line, DET...
...Connection destination request detection section, DCE...Decoder section, SW
. . . switch, MUX . . . multiplexing unit, BM . . . Panzer memory, BM,, BM2. ..., BMI...
・Bannofa memory divided into banks, SEL...Selector agent Patent attorney Akio Namiki Agent Patent attorney Kiyota Matsuzaki 1 Figure W

Claims (1)

[Claims] 1) A packet switching system that performs packet switching by sending packets input from a plurality of input lines to any of a plurality of output lines, comprising: a switch having an input side and an output side; A buffer memory is provided on the output side of the switch for handling outgoing lines, and each bank is divided into banks corresponding to the number of input lines, and a plurality of input lines accommodated on the input side of the switch are connected via the switch. switching control means that enables connection to a predetermined bank of the buffer memory belonging to any outgoing line, and transfers (exchanges) the plurality of incoming lines to the same outgoing line.
1. A packet switching system characterized in that when a plurality of calls requesting a call occur at the same time, each call is stored in a predetermined bank of the buffer memory belonging to the outgoing line to prevent buffer contention between incoming lines.