JPS6295869A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent generation of alloy spike and attain junction with high resistance voltage by internally forming a second diffusion layer having high impurity concentration at the connecting part with the metal electrode of the diffusion layer provided on the substrate and then inserting a high melting point metal layer between the metal electrode and diffusion layer. CONSTITUTION:A second diffusion layer 5 having high impurity concentration is internally formed at the connecting part with metal electrode 8 of the diffusion layer 2 provided on a semiconductor substrate 1. The coexisting layer 6 of impurity atom and inactive atom is also internally formed within such second diffusion layer 5. This structure does not require the need to increase junction concentration and depth of the diffusion layer 2 more than that required and prevents alloy spike. On the other hand, voltage resistance of junction can also be improved. Moreover, contact resistance may be equalized by improving the contact characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which the junction breakdown voltage at a contact portion between a diffusion layer of a semiconductor substrate and a metal electrode is improved.

[Conventional technology]

Generally, a semiconductor device requires electrical connection between an impurity diffusion layer formed on a semiconductor substrate and a metal electrode such as aluminum. For example, as shown in FIG. 2, when an opposite conductivity type impurity diffusion layer 12 is formed on a negative conductivity type semiconductor substrate 11, a contact hole 14 is opened in an insulating film 13 formed on the semiconductor substrate 11, and this frontage is An aluminum electrode 15 is connected through 14.

However, in this configuration, the aluminum electrode 15 that makes an electrical connection with the diffusion layer 12 reacts with the silicon of the diffusion layer 12 to generate so-called alloy spikes 16, and the diffusion layer 12
It may penetrate through the semiconductor substrate 11 and cause a short circuit.

Therefore, as shown in FIG. 3, a second diffusion layer 17 deeper than this diffusion layer 12 is formed so that even if an alloy spike 16 occurs, it will not penetrate through the second diffusion layer 17. Attempts have been made to prevent the short circuit accident.

[Problem that the invention seeks to solve]

The conventional bonding structure described above is not intended to prevent alloy spikes from occurring per se, but is designed to prevent alloy spikes from reaching the semiconductor substrate 11 even if they occur. Therefore, the second diffusion layer 17 needs to be formed deeper than the original diffusion layer 12, and its impurity concentration is necessarily higher than that of the diffusion layer 12.

Therefore, the breakdown voltage of the junction in the second diffusion layer 17 is lower than that in the diffusion layer 12, and it is difficult to apply it as is to a high breakdown voltage semiconductor device.

[Means for Solving the Problems] In the semiconductor device of the present invention, in order to prevent the occurrence of alloy spikes and obtain a high breakdown voltage junction, impurities are added to the connection portion of the diffusion layer provided on the semiconductor substrate with the metal electrode. The second diffusion layer is formed to include a highly concentrated second diffusion layer, and the second diffusion layer is formed to include a coexistence layer of impurity atoms and inert atoms. A second metal layer made of a high melting point metal is interposed between each layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(d) are diagrams for explaining the semiconductor device of the present invention in the order of manufacturing steps.

That is, first, as shown in FIG. 2A, an impurity diffusion layer 2 of the opposite conductivity type is formed in a negative conductivity type semiconductor substrate 1 at a required impurity concentration and a required depth. Then, as shown in FIG. 2B, an insulating film 3 such as an oxide film is formed on the surface of the semiconductor substrate 1, and a contact hole 4 is formed in the insulating film 3 in a portion where electrical connection with the diffusion layer 2 is made. Open.

Next, as shown in FIG. 4(c), the contact hole 4 is
A second diffusion layer 5 is formed by ion-implanting impurities of the opposite conductivity type into the semiconductor substrate 1 at a high concentration through the contact hole 4, and inert atoms are ion-implanted through the contact hole 4 to form the impurity of the opposite conductivity type. A layer 6 in which atoms and inert atoms coexist is formed.

Ne, Ar, Kr, Xe, etc. are used as the inert atoms. Further, the second diffusion layer 5 is shallower than the diffusion N2,
That is, it is formed so as to be included in the diffusion layer 2, and furthermore, the coexistence layer 6 is formed so as to be included in the second diffusion layer 5. In this case, the second diffusion layer 5 and the coexistence layer 6 may be formed at the same depth depending on the diffusion coefficient of impurity atoms and inert atoms and the heat treatment conditions.

Thereafter, as shown in FIG. 4(d), a first metal layer 7 made of a high melting point metal such as tungsten is formed in the contact hole 4, and a second metal layer 8 made of aluminum or the like is formed thereon. It forms an electrical connection with the diffusion layer 2. The first metal layer 7 is formed only in the contact hole 4 using a selective CVD method or a method of depositing a metal film on the entire surface and then etching the same. Further, the second metal layer 8 is formed using a vacuum evaporation method, a sputtering method, or the like, and then patterned to form a desired wiring pattern.

According to this configuration, since the second metal layer 7 made of a high melting point metal is interposed between the second metal layer 8 made of aluminum and the diffusion layer 2, alloy spikes are also generated by heat treatment. There's nothing to do. Therefore, it is not necessary to form the diffusion layer 2 deeply, and the junction breakdown voltage is determined by the impurity concentration of the diffusion layer 2 and the junction depth, and a high junction breakdown voltage can be obtained. Further, the second metal is formed by the second diffusion layer 5.

The contact potential between the layer 7 and the substrate 1 is low, and the coexistence layer 6 of impurity atoms and inert atoms is provided, which acts as a recombination center, resulting in extremely high contact properties. This makes it possible to reduce variations in contact resistance. Therefore, even if the diameter of the contact hole is reduced as the integration density of semiconductor devices increases, an increase or variation in contact resistance can be prevented.

〔Effect of the invention〕

As explained above, the present invention includes forming a second diffusion layer with a high impurity concentration in the connection portion of a diffusion layer provided on a semiconductor substrate with a metal electrode, and is formed so as to include a coexistence layer of impurity atoms and inert atoms, and a second metal layer such as a high melting point metal is interposed between the metal electrode and each of these layers. There is no need to increase the junction concentration or depth of the diffusion layer more than necessary, and the junction breakdown voltage can be improved while preventing alloy spikes. In addition, by forming a second diffusion layer and a layer coexisting with inert atoms, it is possible to improve contact properties and make contact resistance uniform, etc. Improved electrical connections can be achieved.

[Brief explanation of drawings]

FIGS. 1(a) to (d) are cross-sectional views for explaining the semiconductor device of the present invention in the order of manufacturing steps, and FIGS. 2 and 3 are cross-sectional views for explaining different problems of the conventional structure. . DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Diffusion layer, 3... Insulating film, 4... Contact hole, 5... Second diffusion layer,
6... Coexistence layer with inert atoms, 7... First metal layer (high melting point metal layer), 8... Second metal layer (aluminum layer), 11... Semiconductor substrate, 12 ...diffusion layer, 1
3... Insulating film, 14... Contact hole, 15.
...Metal electrode, 16...Alloy spike, 17...
Second diffusion layer. Figure 1

Claims (1)

[Claims] 1. In a semiconductor device in which a metal electrode is electrically connected to a diffusion layer provided on a semiconductor substrate, the diffusion layer has a second layer having a high impurity concentration at the connection portion with the metal electrode. The second diffusion layer is formed to contain a coexistence layer of impurity atoms and inert atoms, and further between the metal electrode and each of these layers. A semiconductor device characterized by having a structure in which a second metal layer is interposed. 2. The semiconductor device according to claim 1, wherein the metal electrode is made of aluminum and the second metal layer is made of a high melting point metal. 3. The semiconductor device according to claim 2, wherein the second diffusion layer is formed by diffusing impurities of the same conductivity type as the diffusion layer. 4. The semiconductor device according to claim 3, wherein the inert atom is any one of Ne, Ar, Kr, and Xe.