JPS6295078A - Time code field detecting circuit - Google Patents

Abstract

PURPOSE:To rapidly carry out a highly accurate editing operation by providing a comparator circuit for transmitting an output when the output of a divider making the contents of a memory of a latch circuit 1/2 coincides with the output of a counter circuit. CONSTITUTION:The latch circuit 2 latches an N-bit count output signal (b) of the counter circuit 1. The divider 3 makes an N-bit latch output signal C of the N-bit latch circuit 2 1/2 and a magnitude comparator circuit 4 compares a divider output signal (d) of the divider 3 with the N-bit count output signal (b) of the counter circuit 1. A flip flop circuit 5 reset by a frame signal (g) extracted from a time code signal supplied from an input terminal 201 and set by a coincidence signal (e) of the N-bit magnitude comparator circuit 4 outputs a field display signal (f) to an output terminal 301 and the N-bit counter circuit 1 and the N-bit latch circuit 2 are respectively latched by the frame signal (g).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time-need detection circuit used for program production in broadcasting stations, production companies, etc., and particularly relates to a time-need field detection circuit.

[Prior Art] It would be desirable if tape addresses could be used in a collection device that specifies editing points, stores them, and performs dubbing editing using tape addresses recorded in synchronization with television signals recorded on video tapes. Edit points can be treated as data, and harmonic control that completely controls the running of the original tape and master tape during electronic dubbing becomes possible. As a result, editing with high editing accuracy becomes possible.

As a tape address, the SMPTE time code of the television standard system of 525/60 has been standardized through discussions among broadcasting personnel and manufacturers. This time code consists of 80 points per frame of the television signal, and 4 bits of time address and 4 bits of binary group are arranged alternately in a comb-like shape. The start of the need word is synchronized with the frame of the television signal.

[Problems to be Solved] However, conventional editing devices do not include appropriate means for distinguishing between the first field signal and the second field signal that constitute the frame of the television signal. There was a drawback that editing could not be achieved.

[Means for Solving Problems] In order to solve the above-mentioned conventional problems, the present invention provides a device that predicts and displays a first field and a second field from time code information of one frame by utilizing the continuity of time needs. The present invention aims to provide a time code feed detection circuit with a new configuration.

To this end, the present invention provides a counter circuit that performs counting at intervals of one frame of a television signal, a latch circuit that stores the counted value of the counter circuit, a divider that uses the stored contents of the latch circuit as a base, and A comparator circuit that compares the output of the divider and the output of the counter circuit and sends out an output when they match, and a flip-flop circuit that sends out a field display signal in accordance with the output of the comparator circuit. The present invention provides a time code field detection circuit with characteristics.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the time code field detection circuit of the present invention. FIG. 2 is a waveform diagram showing the operation of the embodiment of FIG. 1.

101 and 201 are input terminals. 1 is input terminal 1
01 is an N-bit (N is a positive integer) counter circuit that counts the clock signal a of frequency f (f is arbitrary), and 2 is an N-bit counter circuit that latches the N-bit count output signal S of the counter circuit 1. This is a bit latch circuit. 3 is a divider for repairing the N-bit latch output signal C of the N-bit latch circuit 2, and 4 is a divider for repairing the N-bit latch output signal C of the N-bit latch circuit 2; This is an N-bit magnitude comparator circuit that compares the 5 is a frame signal g (clock signal a) extracted from the time code signal supplied from the input terminal 201.
A flip-flop circuit that is reset by a match signal e of the N-bit magnitude comparator circuit 4 and outputs a field display signal f to an output terminal 301. N-bit counter circuit 1 and N-bit latch circuit 2 are each reset and latched by frame signal g.

Furthermore, the operation of the time code field detection circuit of the present invention will be explained.

V is a television signal that is approximately 3 per second during normal playback.
It is composed of 0 pixel signals, and one pixel is called one frame. The pixels of one frame are interlaced scanned first field signal F1 and second field signal F2.
It consists of two signals: (In FIG. 2, the frame is represented by FR.). A time code signal T is recorded in synchronization with the television signal V in order to perform highly accurate editing. The time code signal T has a synchronization bit synchronized with the frame. Frame signal g is obtained by extracting the synchronization bit of time code signal T, and is synchronized by clock signal a.

Frame signal g is sent to time to t, t2 . , , is supplied to the N-bit counter circuit 1 via the input terminal 201 as a reset pulse generated at , , . On the other hand, a clock signal a having a frequency f (f is arbitrary) is supplied to the N-bit counter circuit 1 as a clock signal via an input terminal 101. The N-bit counter circuit 1 turns O at time to due to the frame signal g.
, and a period of to-t is counted.

Let M be the count value at time tl. The count value M is supplied to the N-bit latch circuit 2, is checked at time tl, and is held for a period from t1 to t2.

That is, the N-pin latch output signal C of the N-pin latch circuit 2 is in the period M of tl-t2. The N-bit latch signal is fed to the next divider 3 and divided into stations. Therefore, the divider output signal d of the divider 3 is tl - t2 period M/
It becomes 2. The divider output signal d is supplied to the input end of the N-bit magnitude comparator 4. On the other hand, the N-bit count output signal of the N-bit counter 1 is supplied to the B input terminal of the N-bit magnitude comparator 4.

Frame signal g supplied to N-bit counter circuit 1
is the N-pin latch circuit 2 and the flip-flop circuit 5
This is somewhat slower than the output operation of . Therefore, time t! After the value M of the N pint counter output signal S is launched in the N pin latch circuit 2, the N bin l' counter circuit l is cleared to O and starts counting again. The counter operation continues during the period tl-t2. The output of the N-bit magnitude comparator circuit 4 is designed to be output when the A input and the B input become equal, that is, when they match. During the period tl-t2, the A input is M/2,
The B input varies from O to M. The match signal e of the N-bit magnitude comparator circuit 4 is output when the counter of the N-bit counter circuit 1 reaches M/2.

Considering that the clock signal a is a clock signal with a constant frequency, the time L'1 at which the coincidence signal e of the N-bit magnitude comparator circuit 4 is output is t'1 = tl + J
-1o/2. Here, if the television signal V is in normal playback (not fast forward or slow playback) ti
-to =t2-t+, so t'+ =tl
−+−L2−tl /2.

That is, time t1. A coincidence signal e will be output in the middle of t2. Since the television signal V is continuously repeated, the time t'2 at which the coincidence signal e is next output can be similarly determined. When the match signal e and the frame signal g are supplied to the next stage flip-flop circuit 5, the frame signal g is used for resetting, and the match signal e is used for setting, the field display signal f is outputted to the output terminal 301. The field display signal f consists of a signal fl for displaying the first field and a signal f2 for displaying the second field.

In the above explanation, the explanation has been limited to the case where the television signal V is in normal playback, but even when the television signal V is in 9-way transmission or slow playback, the synchronization of the frame signal g does not suddenly change, so tl -to ' , t2-t
It can be regarded as i, and even if there is some jitter, it is of no practical use, so the field display signal f can be obtained in the same way.

[Effects of the Invention] As explained in detail above, the present invention has the advantage that highly accurate editing work can be performed quickly because the information of the first field and the second field can be obtained from the information in units of frames. has.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a time code field detection circuit according to the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the block diagram shown in FIG. 1: Counter circuit 2. Launch circuit 3: Divider 4: Comparator circuit 5: Flip-flop circuit 101.201: Input terminal 301: Output terminal

Claims (1)

[Claims] a counter circuit that performs counting at intervals of one frame of a television signal; a latch circuit that stores the counted value of the counter circuit; a divider that halves the stored content of the latch circuit; A timer comprising: a comparator circuit that compares the output with the output of the counter circuit and sends out an output when they match; and a flip-flop circuit that sends out a field display signal in accordance with the output of the comparator circuit. Code field detection circuit.