JPS6267785A - Sound recording and reproducing device - Google Patents

Abstract

PURPOSE:To attain the automatic program searching of an optical musical composition at the time of sound reproducing by multiplying an ID signal having information such as elapsed time from the head of each musical composition with a sound signal converted into a digital signal with time division. CONSTITUTION:As to a clock to be a reference for digital signal processing in a PCM processor, a master clock generated synchronously with the rotational phase of a cylinder is used at the time of normal reproducing, and at the time of rapid searching, a reproducing clock synchronizing with a PCM signal reproduced on the basis of PLL is used during the reproducing period of a PCM signal and a master clock is used in the other period. Consequently, high quality of sound reduced at its time axial variation as low as possible can be reproduced at the normal reproducing, and at the rapid searching, an ID signal can be detected even if the frequency of the PCM signal is sharply changed. In addition, the incorrect detection of the ID signal can be suppressed by stopping an error correcting function of the PCM processor at the rapid searching. Thus, precise and rapid program searching can be attained at the time of sound reproducing.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a helical scan type magnetic recording and reproducing device, and in particular to an audio recording and reproducing device suitable for recording and reproducing a large number of time-axis compressed digital audio signals. Regarding.

[Background of the invention]

In recent helical scan type VTRs, there is a tendency to improve the quality of reproduced audio. One of the specific methods is to convert the audio signal into a digital signal, compress the time axis for each field period, and record the video signal on an extension of the video signal recording track, so that at least two rotating heads can record the tape simultaneously. A method is known in which PCM recording is performed in a track section formed during a scanning period (overlap period).

VT that supports time axis compression PCM recording of such audio signals
For example, as described in Japanese Patent Laid-Open No. 58-222402, a method has been proposed in which a time-base compressed PCM audio signal is recorded also on a track where a video signal is originally recorded. (This method will be referred to as the PCM multi-track recording method below.) This proposal divides the video signal recording track into, for example, five equal parts and records a time-axis compressed PCM audio signal on each, including the overlap period. A total of six PCM audio tracks are formed. Therefore, when this VTR is used as an audio-only device, the recording time can be six times longer than when used for normal video, and high-quality PC and M audio can be recorded and played over a long period of time.

However, if we consider, for example, that this system uses a tape with a recording time of 2 hours, the recording time will be six times as long as 12 hours, making it possible to record more than 100 ordinary songs. Therefore, when playing back, it is very troublesome and time-consuming to search for the song to be played by repeating ``play'', ``rewind'', and ``fast-forward'', as with conventional VTRs, to find the beginning of the song. .

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an audio recording/playback device that can automatically locate the beginning of any song during playback on a tape on which a large number of songs are recorded.

[Summary of the invention]

In order to achieve the above object, the present invention has been developed in the tape width direction (
In a helical scan type audio recording/playback device that divides a track into a plurality of tracks in the longitudinal direction of the track and records at least a time-axis compressed PCM audio signal on the divided tracks, the song number (program number) recorded at the time of recording is ), generates an ID signal having information such as the elapsed time from the beginning of the confession, and time-division multiplexes this ID signal with the audio signal converted to a digital signal, and
Detecting the ID signal with the tape running speed being significantly faster than during normal playback (high-speed search state) during playback,
The tape is quickly fed to the beginning of a predetermined song to locate the beginning of the song.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall block diagram of an audio recording and reproducing apparatus that uses the present invention and is capable of automatically finding the beginning of any song during playback. In Figure 1, 1.2 is an audio signal input/output terminal, 3
is a low-pass door (Lpp) for aliasing noise prevention, 4
is an input audio signal dynamic range compression circuit, 5 is an analog-to-digital conversion circuit (AID converter), and 6 is an input audio signal dynamic range compression circuit.
7 is the system controller that controls modes such as recording, playback, search, and stop, and 7 is the ID that contains information such as recorded content, program number, and tape count.
A signal generation circuit, 8 is a decoder for the ID signal, 27 is an ID information display circuit, 9 is a control circuit for a clock switching switch built in the PCM processor, and 10 is for digital audio during one field period. Memory, 11 is a PCM processor that modulates and demodulates digital audio signals, and detects and corrects errors during playback; 12 is a recording amplifier; 12 is a recording amplifier; 14 is a now multi-controller that controls the selection of recording/playback tracks on the tape 26; A servo circuit that controls cylinder rotation and tape running during playback and playback; 15 is a PC;
16 is a preamplifier, 17 is an equalization circuit for the reproduced PCM signal, 18 is an equalized reproduced PCM signal, a circuit for generating a master clock MCK that is a reference for M signal processing, and 18 for regenerating the cyclic clock and "1" and "O". Data identification and PC
Identification data PBD and reproduced clock PB to M processor 11
A data strobe circuit that supplies CK, 20 a digital-to-analog conversion circuit (D/A converter), and 21 an L that attenuates unnecessary high-frequency components generated by sampling.
PF, 22 is a dynamic range expansion circuit for reproduced audio signals, 23 is a recording/reproduction switch, 24 is a cylinder, 25 is a rotary head, and 26 is a magnetic tape. Note that the dynamic range compression circuit 4 and the dynamic range expansion circuit 20 described above together constitute a noise reduction system.

In FIG. 1, an audio signal R input from input terminal 1
A is a dynamic range compression circuit 4 after sufficiently attenuating high-frequency components that cause aliasing noise by an LPF.
The dynamic range is logarithmically compressed to 1/2. The audio signal whose dynamic range has been compressed is A/
The signal is converted into a 10-bit digital signal by the D converter 5 and supplied to the PCM processor 11. The PCM processor 11 first converts a 10-bit digital audio signal into 8 bits, which is the number of transmission bits.

This 10-bit/8-bit compression deletes the upper 2 bits for small amplitude signals and transmits them in 8 bits with 10-bit precision.As the width of the signal increases, it becomes 9-bit precision, 8-bit precision, and In the vicinity of the maximum width, the data is transmitted as 8-bit data with 7-bit precision. This takes advantage of the characteristic that the sharper the amplitude, the less conspicuous the doji noise becomes.Therefore, an 8-bit transmission pinot+-n can secure a dynamic range equivalent to a 10-bit transmission. be. The bit-compressed digital audio data is stored in the memory 10 for each field period. After being interleaved, it is divided into, for example, 132 blocks, and an error detection/correction code and ID
The ID and node supplied from the signal generation circuit 7 are added,
The time axis is compressed to about 1/6. This time-base compressed digital audio signal is modulated into, for example, a bi-phase mark signal suitable for magnetic recording, and then sent to the multicontroller 1.
P synchronized with the rotational phase of the cylinder 24 supplied from 3
According to CM tying signal PCM 30, 5.79M
The signal is intermittently supplied to the recording amplifier 12 at a transmission rate of hpt, and is recorded on the magnetic tape 26 via the switch 23, which is closed to the REC terminal side during recording.

Now, the above PCM timing signal PCM 3
0 and time axis compressed PCM audio signal, Fig. 2, 9, 3
This will be explained using FIG.

FIG. 2 (A shows the loading state of the magnetic tape into the cylinder, and FIG. 2 (B) shows the tape pattern recorded by the PCM multi-track recording system.

As can be seen from this figure, in the vcpc, w multi-track recording system, the rotational phase of the heads 25α and 25b is synchronized in accordance with the track to be recorded or reproduced (Tτ1, Tτ2...Trb in Figure 2). The timing signal pcy3a is required. Second timing signal PCM3
0 is generated by the multi-controller 13 shown in FIG. 6-phase 5W30 generation circuit 4 that generates 6 types of signals in which the phase of 5rso is delayed by 36°x (#-1) [# is 1, 2°...6]
4, and one signal PCM 30 depending on the track to be recorded or reproduced from among these six-phase timing signals.
The track select circuit 45 selects the time-axis compressed PCM signal period and generates a gate signal SGT representing the time-base compressed PCM signal period at that time. Figure 3 (In the Er tie chart, (1) is the head phase detection signal 5W.
30, (2) is the PCM timing signal PCM 30 ,
Further, (3) is a gate signal SGT representing the time axis pressure mPCM signal period. The PCM timing signal PCM 30 in (2) above and the gate signal SGT in (3) with subscripts 1, 2. ...6 corresponds to the track number selected at the time of recording/playback.

The above head phase detection signal 5W50 is a signal generated by the servo circuit 14 based on the tack pulse rp generated by the rotation of the cylinder 24, and is a signal generated by the servo circuit 14 as shown in FIG. The scanning period is low level, and the head 25b is at 18 on the tape 26.
This signal is at a high level during the period when the 00 area is being scanned.

Time axis pressure M for the track number selected in Figure 4
The generation timing of the PCM signal RD and the data structure of one track are shown. In FIG. 4, (4) is the head phase detection signal 5F30. Is (5) input audio signal 7? ,4. +
61 indicates each selected track (Tγ1.Tγ2...Tr
b) Time axis compressed PCM signal RD generated in response to
In is 132 blocks of data that make up one track,
And (8) is the format of audio data and other additional data constituting one block among 132 blocks. In the data format (8) above, S is a block synchronization signal (equivalent to 3 pins), Ad is an address (8 bits), and Q and P are parity words for error correction (1 bit).
6 bits), ID is the ID signal bit (8 bits), Dl
.

D2...Dl is audio data (56 bits), and CRCC is an error detection pit (16 pins).

Note that the ID signal bits are not included in all blocks, but in the present embodiment, the ID signal bits are included in the first . BOIBl of the second block, No. 45. B44 of the 46th Bronok
．． B45. And the 89th. 90th block B 8B
, B890 are included in a total of 6 blocks, and 6-word ID signals are added to each track.

Now, the ID signal, which plays an important role in cueing during playback, will be explained. As mentioned above, 6 words (48 bits) per track are given to the ID signal, and (
Below, in order to distinguish these 6-word ID signals, IDO,
ID1. For example, the program number (denoted as ID5) is necessary for cueing during playback.
Set the song number) to ID1 (2), and set the elapsed time from the beginning of each program (song) to ID2 (minutes) and ID3 (
seconds). The information of this ID signal is shown in Fig. 1 [7
It is generated by the ID generation circuit 7. During playback, the ID signal ID1. When ID2 and ID5 are detected and the elapsed time of the program number you want to play becomes 0 minutes 0 seconds! The tape is sent through a high-speed search and played from there. The method of detecting the ID signal during high-speed search, which is the most important point in cueing during playback, will be described in detail later after explaining normal playback using FIG.

Next, we will explain the playback system. In FIG. 1, the time axis compressed P reproduced from the tape 26 by the head 25
The CM audio signal is sufficiently amplified by the preamplifier 16 and then supplied to the equalization circuit 17. The equalization circuit 17 is
After compensating for the code amount interference of the reproduced ECM signal due to the differential characteristics and band limit characteristics of the tape system, the reproduced PCM signal PBS is supplied to the data strobe circuit. The data strobe circuit 1B uses a phase-locked loop (PLL) to generate a recovered clock PBC from the recovered PCM signal PBS.
K is generated, and the regenerated PC is activated by this regenerated clock PBCK.
Latch the M signal (“1” of the reproduced PCM signal).

"0" data identification) and supplies PCM data PBD and recovered clock PBCK to the PCM processor 11.

In the case of normal reproduction, the transmission rate of the reproduced PCM signal PBS is 5.79 MApr, which is the same as that during recording, so the voltage controlled oscillator (VC
The center frequency 10 of O) is twice the transmission rate 1 1
．． f so that it becomes 58 MHz. By control circuit 19
It is controlled. The PCM data FED supplied from the data strobe circuit 18 is processed by the PCM processor 11.
After demodulation, error detection/correction, two time base extensions, and dinterleaving, the audio data is bit-expanded into 10-bit data and supplied to the D/A converter 20. Also ID
The signal is separated by the PCM processor 11 and supplied to the ID signal decoding circuit 8. The ID signal decoding circuit 8 is an ID
The information is supplied to the display circuit 27 and the system controller 6. The reproduced digital audio signal of 10 pins is converted into an analog signal by a D/I converter 20, and after sufficiently attenuating unnecessary high frequency components generated by sampling by an LPF, it is supplied to a dynabar range expansion circuit 22. The reproduced audio signal FA expanded to the original dynamic range by the dynamic range expansion circuit 22 is outputted from the output terminal 2.

Next, the ID signal detection method during high-speed search, which is the most important aspect of this patent, will be explained.

The biggest problem during high-speed search is that the frequency of the reproduced PCM signal PBS varies from the frequency during normal reproduction. Since the tape runs at high speed, the relative speed of the tape and the head changes, and as a result, the frequency of the reproduced PCM signal becomes low in forward search, and becomes high in reverse search. For example, in the case of an 8 mm video standard VTR, the amount of frequency fluctuation is approximately -11.0% in a 30x forward search and approximately 118% in a 30x reverse search. As the search speed increases, this frequency variation amount becomes larger and larger. Therefore, under these conditions, the frequency of the reproduced clock PBCK in the data strobe circuit 18 fluctuates by about 11 [7] compared to the frequency of the master clock MCK generated based on the head phase detection signal 5F50, making it difficult to process PCM data accurately. become unable to do so. Therefore, in the present invention, a clock changeover switch 59 is provided in the reproduction data processing system, and the configuration is shown in FIG. The part surrounded by the broken line 11 in FIG. 5 is the PCM processor 11 shown in FIG.

In Figure 5, the PC being played back from the tape head system
After the M signal is amplified and equalized, it is sent to the data strobe circuit 1.
8. The data strobe circuit 18 generates a clock PBCK synchronized with the reproduced PCM signal, and strobes the reproduced PCM signal with this clock PBCK. The recovered clock PBCK and strobe data are supplied to the PCM processor 11t\. In the PCM processor 11, the switch 53 first obtains strobe data only for the selected track section and supplies it to the tuning circuit 54. This also applies to tracks other than the selected track.
If an M signal is recorded, for example, as shown in FIG. 3, select the first track Tr+2 and play it back.
This is to ensure that only the first track Tr+ is demodulated even if it is recorded on the other second track Tr2, third track Trs, etc. The wind pulse generator circuit 60 controls the switch 53.
It is generated by counting the internal clock CK from the erroneous part of the PCM timing signal PCM 30. TV-A of aυ in FIG. 3 is a wind pulse. The strobe data output from the switch 53 is supplied to a synchronization detection circuit 54 and a demodulation circuit 55. The synchronization detection circuit 54 detects the synchronization signal S in, for example, the aforementioned 132 blocks, and determines the boundaries of each block.

Since the detection of this synchronization signal S, in other words, the ability to discriminate block boundaries, is extremely important for data demodulation and error detection/correction, the synchronization detection circuit 54 has a synchronization signal protection function. FIG. 7 shows a specific example of the configuration of the synchronization detection circuit.

FIG. 7 (In J, 71 is an input terminal for strobe data PBD, 72 is an input terminal for internal clock CK, 73 is a pattern comparison circuit, 74 is a synchronization signal pattern generation circuit,
75 is a counter, 76 is a decoder, 77 is a gate circuit,
Reference numeral 78 designates a pseudo synchronization detection signal generation circuit, 79 a select circuit, and 80 an output terminal for the synchronization detection signal. Figure 7 (A
, the strobe data FBI inputted from the input terminal 71 is supplied to the pattern comparison circuit 73, and is compared with the black synchronization signal pattern sent from the synchronization signal pattern generation circuit 74. Then, in the pattern comparison circuit 73, if the signal patterns match, it is determined that it is a synchronous signal, and as shown in FIG.
A synchronization detection signal Sφ as shown at 02 in B) is supplied to the select circuit 79 and the gate circuit 77. Gate circuit 77
is a similar detection signal s1 ((I41) in FIG. 7(B)) of only the gate period (high period) of the synchronous gate pulse GAT as shown by α in FIG. 7(B) sent from the decoder 76.
is supplied to the select circuit 79.

On the other hand, the counter 75 uses the synchronization detection signal BS supplied from the select circuit 79 as a reset signal to
The internal clock CK input from the terminal is detected. This count output is supplied to a decoder, which detects the count value for one block period, and supplies a synchronization gate pulse GAT to the gate circuit 77 near the detection timing of the next synchronization signal.

This can be caused by erroneous detection in the pattern comparison circuit, for example, as shown in Figure 7 (
This is because when a signal of erroneous detection (2) is generated as shown in QX5 of Bl, if this signal is treated as a synchronization detection signal, the strobe data cannot be demodulated correctly. The pseudo synchronization detection signal generation circuit 78 supplies a pseudo synchronization detection signal S2 as shown in (IS) in FIG. 7(B) to the select circuit 79 using the timing signal ST1 supplied from the decoder 76. For example, in Figure 7 (B
) As shown in C16 erroneous detection ■, even if the synchronization detection signal Sφ or Sl is missing due to strobe error etc. at the place where the synchronization signal should originally be detected, the subsequent synchronization detection timing is ensured. It is for. The select circuit 79 selects and outputs the above-mentioned synchronization detection signal Sφ, the synchronization detection signal S1 via the gate circuit 77, and the pseudo synchronization detection signal S2.

In this selection, since the strobe data PBD is a time-base compressed signal and is supplied intermittently as shown in (6) in FIG. 4, the synchronization detection signal Sφ is first selected for each field period. However, from then on, the synchronization detection signal S1 via the gate circuit 77 is selected. If the synchronization detection signal S1 via the gate circuit 77 is missing, the pseudo synchronization detection signal S2 is selected. However, if the synchronization detection signal s1 via the gate circuit 77 is missing multiple times in a row, it is expected that the gate timing is shifted, so in order to return to the initial state, the synchronization detection signal Sφ is selected. .

The internal clock CK in the synchronization detection circuit 54 shown in FIG. PCM
The master clock MCK generated by the master clock generation circuit 15 with reference to 30 is used, and the reproduced clock PECK generated by the data strobe circuit 18 by switching the switch 59 during high-speed cue search is used. ing. During normal playback, this is the strobe data PB.
Since the frequency of D is L-< constant, which is the same as during recording, the master clock MCK, which is not affected by disturbances in the reproduced data, is used, and during high-speed search, the strobe data is Since the frequency of PBD varies, a recovered clock PBCK whose frequency changes in accordance with the frequency variation of strobe data is used.This master clock MCK and recovered clock PBC are used.
Switching of K is performed using a switch 59 shown in FIG. The above clock selection switch 59
is controlled by a control signal SC supplied from the switch control circuit 9. A time chart of the control signal SC is shown in FIG. In Figure 8, Sumi is the strobe data PBD of the selected track, and α barrel is the time axis compressed PCM.
Gate signal SGT indicating signal generation and reproduction timing
. Qυ
is the switching control signal SC of the switch 59, and the slope is the VCO 1 in the clock recovery PLL of the data stroke circuit.
0 control signal fc, and (c) is the activation center frequency VCOf of the above-mentioned VCO. It is. The clock changeover switch 59 is closed to the A side during the period when the changeover control signal SC is high (during high-speed search, and the time-base compressed PCM signal is being regenerated), and outputs the regenerated clock PBCK to control the clock changeover switch 59. During the period when the signal SC is low, it is closed to the B side,
Outputs master clock MCK. Here, the reason why the internal clock CK is set to the recovered clock PECK only during the reproduction period of the time axis compressed PCM signal during a high-speed search is, for example, if the internal clock CK is always set to the recovered clock PBCK during a high-speed search, as shown in FIG. As shown in FIG. 3, the wind pulse Wi generated by the wind pulse generation circuit 60 has a wide pulse width in the case of reverse high-speed search (Wi −B in αυ in FIG. 3). On the other hand, in the case of a high-speed search in the head direction, the pulse width becomes narrower (see Figure 3 (11)).
(Wi-C) This is because the signal of the selected track cannot be sufficiently passed through. Moreover, since the reproduced clock PBCK is generated by the PLL of the data strobe circuit 18, the p'co of the PLL oscillates freely outside the reproduction period of the time-base compressed PCM signal, and the frequency becomes insufficient.

Now, the data strobe circuit 18 will be explained. FIG. 9 shows an example of the configuration of the data stroke circuit 18. The part surrounded by the dotted line 18 is the data stroke circuit. In FIG. 9, 81 is an input terminal for the equalized reproduced PCM signal, 82 is a limiter, 85 is a type 7 lip-flop for data strop, 84 is a phase detection circuit, and 85 is a low-pass p-wave filter (LPF). , 86 is a voltage controlled oscillator (VCO), 87 is a limiter, 88 is a strobe data output terminal, and 89 is a reproduced clock output terminal.

Control signals 51.90 and 91 represent high-speed searches in the forward and reverse directions, respectively. This is an input terminal of Sf. Note that the phase detection circuit 84, LPFB 5, and VCO 86 constitute a clock recovery PLL. P for clock recovery in this data stroke circuit
In the LL, the center frequency fo of the VCO 86 is changed during normal playback and during high speed searches in the forward and reverse directions. What will happen to this in the future?As I have explained, it is a refurbished PC.
This is because the frequency of the 1%i signal changes significantly between normal playback and high-speed search. If an attempt is made to deal with this frequency fluctuation of the reproduced PCM signal by widening the holding/pulling range of the PLL circuit, a so-called pseudo-lock phenomenon may occur, in which the PLL circuit pulls in at a frequency different from the original oscillation frequency.
This increases steady-state errors that increase data identification errors during strobe operation. Therefore, in the clock recovery PLL of the data strobe circuit 18 shown in FIG. Depending on the mode of play according to the VC
The center frequency of O is changed. Control O (M number, Sr
FIG. 8 shows the waveforms of Sf and f0 suppression signal fC for each reproduction mode. The control signal Sr of αl in FIG. 8 is at a high level only during a high-speed search in the reverse direction, and the control signal S/ of υ and 2 is at a high level only during a high-speed search in a forward direction. and (c) f. According to the control signals Sr and Sf, the control signals are set to a higher potential Er during reverse high-speed search than the potential En during normal reproduction, and to a lower potential E/D during forward high-speed search compared to the potential En during normal reproduction. . The center frequency and pull-in range of the cyclic regeneration PLL are as shown in FIG. 10 using the fo control signal fc. In FIG. 10, 1° is the center frequency during normal reproduction, f7 is the center frequency during reverse high speed search, and ff is the center frequency during forward high speed search. (For a 60x speed search with an 8mm video standard VTR, f 0 = 1 t58&Hz, fr =
12.94MHz, f7 = 10.31 J/
It is H2. ) FIG. 11 shows a specific configuration example of a VCO that changes the excavation center frequency according to the f o *J H signal fc. Figure 11 (AJ is a VCO using an LC tank circuit, 100 is an f. input terminal for the control signal 103 is a tank circuit, 104 is an amplifier for obtaining a loop gain, 105 is a buffer, and 106 is a phase shift circuit. FIG. 11(B) shows the tank circuit 103. Now, we will explain the frequency control principle of the VCO shown in FIG. . is tank circuit 10
This is the co-photography frequency of 3.

′°=Dingσ. In this case, the capacitor C1 uses, for example, a variable capacitance diode, and the capacitance of the capacitor C1 changes depending on the I0 suppression signal fc supplied via the input terminal 100.
The oscillation center frequency changes according to the fo control signal fc.

On the other hand, if the phase is delayed by, for example, ψ in the phase shift circuit 106 due to the phase detection output supplied from the input terminal 101, the phase must be advanced by ψ in the tank circuit 103 after t when positive feedback is applied. The onset frequency is shown in Figure 11 (
As shown in B), the frequency f is lower than the center frequency.

By using the clock PBCK reproduced by the data strobe circuit 18 described above as the internal clock CK during high-speed search, the reproduced PCM data whose block synchronization has been accurately detected by the synchronization detection circuit shown in FIG. 5 is demodulated. It is demodulated by circuit 55. The error detection circuit 58 detects an error in each block of the demodulated reproduced data, and if that block has an error, it is replaced with a data pattern representing the error. The reproduced data for which an error has been detected in this manner is processed by a write control signal WE synchronized with the reproduced clock PBCK supplied from the memory control circuit 58.
be written to the internal memory 57 according to the following. After one block of data is written, the data is read out and supplied to the external memory 10 in accordance with a read control signal RE synchronized with the internal clock CX supplied from the memory control circuit 58. The internal memory 57 has a data capacity of two blocks, and during the reproduction period of PCM data, writing and reading are simultaneously performed for each block at any time. The internal memory 57 reads out the reproduced data having time axis fluctuations in synchronization with the internal clock CK so that the internal clock C can be read out in synchronization with the internal clock CK.
We are trying to make it possible to use K. The internal clock CK in this case is switched by a switch 59, and is the master clock MCK with a stable frequency during normal reproduction, and is the reproduced clock PBCK that matches the transmission frequency of the reproduced data during high-speed search.

The reproduced data read from the internal memory 57 is written to the external memory 10 by control signals R and 4C supplied from the memory control circuit 61. (7) When data for one field is written to the external memory 10, error correction using a parity word is performed between the error correction circuit 62 and the error data and correct data are replaced. It will be done.

Then, when the error correction is completed, in order to restore the time axis to the original state, reading is started at a lower frequency than when writing, and the audio data is supplied to the 8-bit/1C pit decompression circuit 63, and the ID The signal is supplied to the ID separation circuit 64. However, in the case of high-speed search reproduction, signals of multiple tracks are reproduced with one scan of the head, and the reproduced data spans several tracks as shown in FIG. Correct error correction may not be performed and erroneous correction may be performed. Therefore, in this embodiment, error correction is stopped during high-speed search. This is done by the memory control circuit 61 prohibiting rewriting of error data and correction data.

The 8-bit audio data supplied to the 8-bit/10-bit decompression circuit is converted to 10-bit f-voice data and sent to output terminal 5.
1 to the DA converter 20 shown in FIG. On the other hand, ID data P output from the ID separation circuit 64
The ID is supplied via output terminal 52 to ID decoder 8 shown in FIG.

The ID decoder 8 decodes the reproduced ID signal PID and supplies information such as the program number and elapsed time to the display circuit 27 and the system controller 6.

Next, a specific method of cueing by high-speed search using an ID signal will be explained.

FIG. 13 shows a flowchart of an example of a cueing process by high-speed search. In FIG. 15, first, the number (hereinafter referred to as SNo.) of the song to be cued is inputted from the outside to the system controller 6. Next, the song number (hereinafter referred to as FBNo) at the time when cueing is started is detected during normal playback, and the SNo and PENo are compared. So(
7, if S)~o > pBso, high-speed search detection is performed in the forward direction. During this high-speed search detection, S is always
A'.

By comparing the magnitude relationship between and P B N o , SN
A high-speed search is performed in the forward direction until the point where PRNo. For search, SNo “” PRN
This is because even if o is detected, it is difficult to stop the tape running at that point instantaneously and "overshooting" occurs. On the other hand, S.N.
o≦P B No If o, SNo ” P, T3No
And, for example, the reverse high-speed search is performed until the elapsed time becomes 0 minutes 30 seconds or less. Then, low-speed search detection is performed until the elapsed time reaches 0 minutes and 0 seconds. The reason why the search is performed at low speed when the elapsed time is detected to be 0 minutes 30 seconds or less is to prevent the elapsed time from exceeding 0 minutes 0 seconds due to the above-mentioned "excessive progress". Note that the above-mentioned "1 overshoot" is determined by the speed of the high-speed search and the time difference between detecting the ID scratch mark and actually stopping the tape running system. For example, if the high-speed search speed is 30x and the above time difference is 0.5 seconds, The "sugi" amount corresponds to 15 seconds of normal playback.

FIG. 14 schematically shows the cueing process by the above-mentioned high-speed search with the tape as a reference.

In addition, the above high-speed search was used to find the beginning (in 7, it was done using the song number (program number) as an ID signal and the elapsed time from the beginning of the 6 songs, but in addition to this, for example, when recording, the interval between each song is detected and the ID is It may be recorded as a signal, and during playback, cueing may be performed by detecting an ID signal representing the interval between songs.

As explained above, according to this embodiment, the oscillation center frequency of the VCO in the clock reproduction PLL is changed according to the tape running speed and the tape running direction during high-speed search, so that when the frequency of the reproduced PCM signal fluctuates. You can even play rock accurately. During normal reproduction, a master clock generated in synchronization with the rotational phase of the cylinder is used as the reference clock for digital signal processing in the PCM processor, and during high-speed search, the PCM signal is reproduced by the PLL during the PCM signal reproduction period. By using a playback clock that is synchronized with the PCM signal and using the above master clock during other periods, it is possible to play back high-quality audio with extremely small time axis fluctuations during normal playback. At the time,
It becomes possible to detect the ID signal even if the frequency of the reproduced PCM signal fluctuates significantly. Moreover, when searching at high speed, use a PC.
By stopping the error correction function in the M processor, detection of an erroneous ID signal can be prevented, which is effective in performing accurate and quick cueing during playback.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to accurately detect an ID signal even during a high-speed search, and automatic cueing during playback can be performed accurately and quickly. It's a dog.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a system showing an embodiment of the present invention;
Fig. 2 is a schematic diagram showing the tape loading state and a tape pattern diagram, Fig. 3 is a block diagram of the multi-controller and a timing chart of control signals, and Fig. 4 is a diagram showing the generation timing of time axis compressed PCM signals and a data model. figure,
Figure 5 is a block diagram of the PCM processor, Figure 3 is a wind pulse generation timing chart, Figure 7 is a block diagram of the synchronization detection circuit and timing chart of main signals, Figure 8 is a timing chart, and Figure 9 is data. A block diagram of the Stroop circuit, Figure 1C is a diagram showing the center frequency and pull-in range of the PLL circuit, Figure 11 (B) is a block diagram showing an example of a configuration of a VCO, and Figure 11 (B) is a diagram showing the frequency of the tank circuit. Figure 12 is a diagram showing the tape pattern and head scanning trajectory during high-speed search, Figure 13 is a flowchart of the system when performing high-speed cueing, and Figure 14 shows the progress during high-speed cueing. It is a diagram. Explanation of symbols 6...System controller 7...
.......ID generation circuit 8........ID decoder 9...
...Switch control circuit 10 ...Memory

Claims (1)

[Claims] 1. An audio recording and reproducing device that divides a track formed by helical scanning into a plurality of parts in the tape width direction and records at least a time-axis compressed pulse code modulated audio signal on the divided tracks. The recording system includes means for generating an ID signal having information related to the recorded signal, and means for recording the ID signal together with the pulse code modulated audio signal using a first clock as a reference, and the reproduction system includes: , high-speed search playback means for making the tape running speed much faster than during normal playback;
D signal, and means for detecting the ID signal using the second clock as a reference during high-speed search playback, and according to the information of the detected ID signal, the tape is played until the beginning of the desired song. An audio recording/playback device characterized in that it is capable of rewinding or fast forwarding by high-speed search playback. 2. The audio according to claim 1, wherein the ID signal includes information such as the number of the song to be recorded, the elapsed time from the beginning of each song, and the inter-song detection signal of each song. Recording and playback device. 3. A patent characterized in that the first clock is a clock synchronized with the rotational phase of the rotary head, and the second clock is a clock synchronized with the time-base compressed pulse code modulated audio signal to be reproduced. An audio recording and reproducing device according to claim 1. 4. The audio recording and reproducing apparatus according to claim 1 or 3, wherein the second clock is a clock for a data stroke of a time-base compressed pulse code modulated audio signal to be reproduced. 5. The second clock is generated by a phase-locked loop into which a reproduced time-base compressed pulse code modulated audio signal is input. Audio recording and playback device. 6. The center frequency of the phase-locked loop is set lower during forward high-speed search playback than during normal playback, and is set higher during reverse high-speed search playback than during normal playback. audio recording and playback device. 7. The audio recording and reproducing apparatus according to claim 1, wherein the ID signal detecting means stops an error correction function during high-speed search reproduction.