JPS625732A - Coding system - Google Patents

Abstract

PURPOSE:To simplify the constitution of a coding and decoding circuit by using a run-length value of n bits obtained at a run-length counter as a coded code and sending it as it is. CONSTITUTION:A change point detection circuit 2 detects a change point of a signal level of a binary-coded picture signal DS and the information of change point is given to counters 41, 42 of a run-length counter 4 as a clear signal. The count of a clock is started from the point of time of detection of a change point by the counter 41, the count is stopped at the incoming point of time of the next change point detection signal and the count is outputted to an output circuit as a terminating code. When the run lengths are 128 or over, the 'H' level signal is generated from a MSB bit output terminal of the 1st counter 41 at each count of 128 and the signal is counted by the 2nd count circuit 42. When the next change point is generated, the count is stopped and the count is outputted as it is to the output circuit 5 as the terminating code and the makeup code.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in encoding methods used, for example, when encoding facsimile signals.

[Technical background of the invention]

For example, the photoelectric conversion output obtained from a facsimile scanner is usually converted into a black and white binary digital signal by sampling and quantization, but since this type of signal has a large degree of redundancy, it is necessary to compress and encode the redundancy. It has become. There are various redundancy compression encoding methods, and one of them is one that detects the continuous length of white and black pixels for each line, that is, the run length, and encodes this run length. Tables 1 and 2 show the Wyle encoding method and Mo
It shows a part of the relationship between the run length and code of the divided Huffman encoding method (MH encoding method).

Table 1 Table 2 [Problems in the Background Art] However, all of these encoding systems require a conversion means to convert the run length into a code, and as is clear from the above tables, the run length Since all the codes are represented by unequal length codes, when transmitting these run-length codes, it is necessary to convert them into the number of transmission bits per byte (for example, 8 bits) defined by the transmission path.

For this reason, the transmission apparatus using the conventional run-length encoding method has the disadvantage that the configurations of the encoding circuit and decoding circuit are complicated and large.

[Object of the Invention] The present invention eliminates the need to convert run lengths into special codes and eliminates the need to match transmission bits, thereby simplifying the configuration of encoding and decoding circuits, thereby improving the efficiency of transmission equipment. The purpose of this invention is to provide an encoding method that can be made smaller and lower in price.

[Summary of the invention]

In order to achieve the above object, the present invention sets the number of bits of the count output to the number of bits per byte specified in the transmission path (
A run length counter is provided which is set equal to n bits), and the n bit run length value obtained by this run length counter is transmitted as it is as an encoded code.

[Embodiments of the invention]

FIG. 1 shows the configuration of an encoding circuit to which an encoding method according to an embodiment of the present invention is applied.

This circuit includes an input circuit 1 for a binary image signal DS, and a change check for detecting signal change points from white to black and from black to white in the binary image signal DS introduced through the input circuit 1. It is composed of an output circuit 2, a clock generation circuit 3 that generates a clock signal whose cycle corresponds to the pixels of the binary image signal DS, a run length counter 4, and an output circuit 5 that outputs a run length code. .

The input circuit 1 and the output circuit 5 each start operating when an encoding start signal C3T is generated from a main control circuit (not shown) that controls the operation of the entire facsimile machine, and there is no communication between the main control circuit and the main control circuit. After a request signal RQ and a response signal ACK are exchanged between them, a binary image signal DS is introduced and a run length code CDS is output.

Further, the clock generation circuit 3 operates when the encoding start signal C3T is generated from the main control circuit and when the above-mentioned change point detection circuit 2
The change point detection circuit starts generating a clock signal when the change point detection circuit is generated.

The run length counter 4 has a first counter 41 that outputs a terminating code and a second counter 42 that outputs a make-up code. The first counter 41 receives the encoding start signal C8T from the main control circuit supplied via the OR gate 43 and the change point detection circuit 2.
It clears the count value every time the change point detection signal and the "H" output of the MSB bit of its own count output are supplied, and starts counting the clocks from the clock generation circuit 3. The value is output to the output circuit 5 as a terminating code. Further, the second counter 42 clears the count value when the encoding start signal C3T of the main control circuit and the change point detection signal of the change point detection circuit 2 are generated, which are supplied via the OR gate 44,
From this point on, counting of the "H" level output of the MSB bit of the count output of the first counter 41 is started, and the count value at the time of clearing is outputted to the output circuit 5 as a make-up code.

Figure 2 shows the configuration of a decoding circuit to which the encoding method of this embodiment is applied. This circuit includes an input circuit 6 that manually inputs the run-length code CDS transmitted from the transmitting side according to instructions from a main control circuit (not shown), and a clock generation circuit 7 that generates a clock corresponding to the pixel period of the image signal. , a run-length down counter 8, an image signal reproduction circuit 9, and an output circuit 10 that outputs the reproduced image signal DS according to instructions from the main control circuit.

The run length down counter 8 has a run length code C.
An M/T determination unit 81 determines whether the DS is a terminating code or a make-up code for each byte, and when a make-up code arrives, this code is added to the subsequently arriving terminating code. adder 8
2 and a down counter 83. This down counter 83 uses the output value of the adder 82 as an initial count value and performs a down count every time a clock is generated from the clock generation circuit 7, and thereby the output value of the adder 82, that is, the run length. A pulse signal corresponding to the length of is output. The image signal reproducing circuit 9 also includes a white/black specifying section 91 that specifies whether the pulse signal represents white or black of the image signal every time a pulse signal is generated from the down counter 83; Image signal generator 9
The image signal generating section 92 outputs the clock from the clock generating circuit 7 by the pulse width of the pulse signal supplied from the down counter 83, and outputs the clock from the clock generating circuit 7 as a reproduced image signal DS to the output section 10. supply Incidentally, at this time, the reproduced image signal DS output from the image signal generating section 92
The signal level of is set to the level designated by the white/black designation section 91.

By the way, the terminating code and make-up code handled by the above encoding circuit and decoding circuit are respectively configured as follows. That is, each of the above codes is set to, for example, 8 bits according to the number of bits per byte specified in the transmission path, and the most significant bit MSB of these 8 bits is set as a make-up code as shown in Figure 3A. It is used as a discrimination bit from the terminating code, and the remaining 7 bits are used as sign bits. Therefore, the length of the run length represented only by the terminating code is 1, which corresponds to 7 bits.
to 127, and 128 and above are represented by make-up codes. For example, if the run length is 300, the run length is 10000010" (llI
2H) and the make-up code 0 shown in Figure 4(b).
0101100' (2CH) is represented by a pair with terminating number 7. When these make-up codes and terminating codes are transmitted, the make-up code is first sent out, followed by the terminating code. Note that if the run length is 127 or less, it is represented by only a terminating code, and only this terminating code is sent.

With such a configuration, in the encoding circuit (Fig. 1), when the encoding start signal C3T arrives from the main control circuit and the request signal RQ is sent from the input circuit 1 in response, the input circuit 1 sends a second signal. The digitized image signal DS arrives, and this binary image signal DS is introduced into the input circuit in synchronization with the simultaneously arriving response signal ACK, and is supplied from the input circuit 1 to the change point detection circuit 2. Then, this change point detection circuit 2
Then, a change point in the signal level of the binary image signal DS is detected, and information on this change point is given to each counter 41, 42 of the run length counter 4 as a clear signal. On the other hand, at this time, the clock generation circuit 3 starts generating a clock in synchronization with the encoding start signal CST, and this clock is introduced into the count pulse input terminal of the counter 41.

As a result, the first counter 41 starts counting clocks from the point of time when the above-mentioned change point is detected. Then, counting is stopped when the next change point detection signal arrives, and the count value at this time is outputted to the output circuit 5 as a terminating code. However, if the run length is 128 or more, 12
Every time 8 is counted, an "H" level signal is generated from the MSB bit output terminal of the first counter 41, and this signal is counted by the second counting circuit 42. Then, when the next change point occurs, the first counter 41 and the second counter
The counters 42 each stop counting and output the count values at this point as they are to the output circuit 5 as a terminating code and a make-up code, respectively.

Therefore, in the case of this embodiment, there is no need for code conversion as in conventional W y l' e encoding or MH encoding. Further, the output circuit 5 to which the above-mentioned terminating code and make-up code are supplied first judges whether or not the make-up code has been output from the second counting circuit 42, and if it has been output, first sends out this make-up code. After that, the terminating code from the first counter 41 is sent out. At this time, since each of these codes is already fixed at 8 bits when output from each counter 41 and 42, the output circuit 5 transmits each of the above codes to the subsequent stage with the same signal configuration. Supplies to the circuit section. Therefore, in the output circuit 5, there is no need for signal processing such as bit alignment as in the prior art.

On the other hand, in the decoding circuit (FIG. 2), when a decoding start signal DST arrives from the main control circuit (not shown), it sends and receives a request signal RQ and a response signal ACK, and inputs a run-length code CDS. This run length code CD
S is supplied to the run length down counter 8. Then, in the run-length down counter 8, the M/T determining section 81 first determines whether or not a make-up code has arrived. If there is a make-up code, this make-up code and its successor (terminating code) are added by the adder 82 and set in the down counter 83.As a result, the down counter 83 is set. 83 uses the set value as an initial value and counts down from the set value every time the clock generation circuit 7 generates a clock, and outputs, for example, an "H" level signal during the down-counting period. As a result, the image signal reproducing circuit 9 synchronizes the pixel signal whose level has been set according to the specification of the white/black specifying section 91 while the output of the down counter 92 is at the "H" level, in synchronization with the clock of the clock generating circuit. This reproduced image signal DS is serial-parallel converted and outputted to the output section 10.The output section 10 sends and receives the request signal RQ and response signal to and from the main control section (not shown). The reproduced image signal DS reproduced by the image signal reproduction circuit 9 is output to.

Therefore, in this decoding circuit, since the make-up code and the terminating code that represent the length of the run length arrive, these codes can be directly provided to the down counter 83, and as a result, the arrived run-length code is There is no need to convert it into a code representing the length, and that circuit becomes unnecessary. Further, since the incoming run-length code has a fixed length of 8 bits, there is no need for the input circuit 6 to extract the code at the time of reception, thereby eliminating the need for that circuit.

As described above, in this embodiment, since the length of the run length is transmitted as it is as a run length code, the code conversion circuit required in conventional encoding methods such as Wyle-encoding and MH encoding is required. This eliminates the need for the circuit configuration and the program for the control circuit that controls it. In addition, by using a run-length code with a fixed number of bits at 8 bits for transmission, there is no need to perform bit alignment and bit extraction during transmission and reception. Coupled with the fact that the code conversion circuit can be omitted, the configurations of the encoding circuit and decoding circuit can be greatly simplified and downsized.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the case where the number of transmission bits per byte specified in the output path of the encoding circuit is 8 bits is explained, but even if the number of bits is larger, such as 16 bits, the run-length code can also be used. It can be implemented similarly by matching the bit numbers of . In this case, when the number of bits is large, and the run length that can be expressed by one byte can also be set large, it is also possible to transmit only the terminating code. In addition, the configuration of the run length counter and the configuration of the run length down counter,
It goes without saying that the present invention can be modified in various ways without departing from the spirit of the present invention.

〔Effect of the invention〕

As detailed above, according to the present invention, a run length counter is provided which is set equal to the number of bits (n bits) for each byte, and the n bit run length value obtained by this run length counter is used as an encoded code. By transmitting the run length as it is, it is not necessary to convert the run length into a special code, and it is also unnecessary to match the transmission bits, which simplifies the configuration of the encoding and decoding circuits. As a result, it is possible to provide an encoding method that can reduce the size and cost of a transmission device.

[Brief explanation of drawings]

The figures are for explaining the encoding method according to an embodiment of the present invention. FIG. 4 and FIGS. 4(a) and 4(b) are schematic diagrams for explaining the structure of a run-length code, respectively. 1.6... Input circuit, 2... Change point detection circuit, 3゜7... Clock generation circuit, 4... Run length counter, 41... First counter, 42... No. 2 counter, 43.44...or gate, 5, 10...
Output circuit, 8... Run length down counter, 81
. . . M/T determination section, 82 . . . Adder, 83 . . . Down counter, 9 . , C3T...encoding start signal, DS...binarized image signal (regenerated image signal)
, RQ...request signal, ACK...response signal, CDS
...Run length code, DST...Decoding start signal. Applicant's representative Patent attorney Takehiko Suzue Figure 1, 9 Figure 2 Figure 3 Figure 4 (a) Figure 4 (b)

Claims (2)

[Claims] (1) In a coding method that detects the run length of a digital signal and encodes and transmits the run length, the number of bits of the count output is defined as the number of transmission bits per byte (n bits) specified by the transmission path. An encoding method characterized in that a run length counter is provided which is set equally, and an n-bit run length value obtained from the run length is transmitted as it is as an encoded code. (2) The run-length counter consists of a first counter that counts make-up codes and a second counter that counts terminating codes, and a predetermined 1 bit of the count output of these counters is used as the make-up code. All remaining bits are used to represent the make-up code and the terminating code, respectively, as identification codes from the terminating code, and run lengths whose length is within n-1 bits are transmitted only by the count output of the first counter. At the same time, a run length of n bits or more is transmitted by adding the count output of the first counter after the count output of the second counter. Encoding method.