JPS6255338B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technology for compensating for cross-polarization interference caused by the shared use of orthogonal polarizations in wireless transmission, and particularly to a cross-polarization compensation circuit.

Radio communications in the microwave band are rapidly developing, centering on terrestrial communications and satellite communications. The demand for wireless communications is expected to further increase in the future due to the expansion of mobile communication services, and along with the development of sub-millimeter wave and higher frequency bands, the idea of so-called frequency reuse of currently used frequency bands with high practical value is being developed. is increasing. CCIR (International Radiocommunication Consultative Committee)
Recommendations for 4-6 GHz FM radio frequency deployment specify the use of orthogonal polarization. Also, in satellite communications, INTELSAT (International Telecommunication Satellite Organization) is expected to put into practical use technology for sharing orthogonal polarization in the 4-6 GHz band, which has been used with single polarization on the V-series satellites.

In order to achieve this shared use of orthogonal polarization, it is important to improve the polarization characteristics of antennas and power supply equipment, as well as develop cross-polarization compensation circuits that compensate for deterioration of polarization characteristics during radio wave propagation due to rain, etc. This has become an issue.

Originally, free space is a transmission line that is independent of two orthogonal polarized waves and can simultaneously transmit both polarized waves, but in actual propagation paths, there is anisotropy in the medium such as rain, so it is difficult to use the orthogonal polarization sharing method. If adopted, coupling between polarized waves due to the generation of cross-polarized waves will cause interference between different polarization channels.

Cross polarization compensation technology automatically compensates for such coupling between polarized waves by providing a compensation circuit within an antenna feeder or wireless device.

Conventionally, microwave band communication has centered on analog transmission centered on FM, so the cross-polarization compensation method described above also restores orthogonality by installing a variable phase shifter and attenuator around the antenna feeder. A number of methods have been well researched and put into practical use, including methods that eliminate interference between different polarized waves by providing an interference wave compensation circuit in the intermediate frequency band.

In recent years, digital transmission has come into use in the microwave band as well, and there is a need to propose a more efficient cross-polarization compensation method that takes advantage of the characteristics of digital transmission.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cross-polarization compensation circuit that performs a cross-polarization compensation method in a baseband band based on demodulated baseband signal information in digital transmission.

According to the present invention, digital transmission for shared orthogonal polarization can be performed through a currently used antenna system for single polarization and intermediate frequency equipment.

Currently, the beam width of satellite antennas is considerably wider than that of terrestrial microcircuits, and
Global beam antennas use asymmetric beams to increase effective transmission power;
Furthermore, due to Faraday rotation in outer space, a high degree of orthogonal polarization discrimination cannot be expected.

In such a transmission system, the present invention is significantly superior to conventional systems, and is more economical in that it does not require any modification to the currently used transmission system. Even when signals from multiple stations are received in a time-division manner using the same antenna, as in TDMA, cross-polarization compensation can be performed for each transmitting station individually.

The circuit of the present invention provides a system for wirelessly transmitting first data and second data, which are independent digital signals, using first polarized waves and second polarized waves that are orthogonal to each other. a pre-discrimination circuit that receives as input an error candidate detection output near the signal discrimination boundary line and generates an estimated discriminant value output for areas other than the vicinity of the discrimination boundary line, and the estimated discrimination value output from the pre-discrimination circuit a storage circuit that supplies a constant other than zero corresponding to the error candidate detection output of the prediscrimination circuit, and a subtracter that subtracts the output of the storage circuit from the first data. and,
a final identification circuit that estimates and identifies the first data from the output of the subtracter; and a storage content modification circuit that corrects and outputs the output of the storage circuit according to the input/output difference of the final identification circuit; From the output of the final identification circuit, first data is obtained from which interference of the second data with the first data due to cross-polarization interference occurring in the wireless transmission path is removed, and from the output of the storage content modification circuit, the The present invention is characterized in that the memory contents of the currently selected memory element of the memory circuit are changed to correspond to changes in the state of cross-polarized interference.

Next, the present invention will be explained in detail with reference to the drawings.

First, regarding the prior art, Figures 1a, b to 7
This will be explained with reference to the figures. Reference numbers 4000, 4001, 4002 and 4 in Figures 1a and b
003 and reference numbers 4100, 4101 and 41
02 and 4103 are 4 of the 4-phase phase modulation signal, respectively.
The two signal points are shown on the orthogonal (IQ) phase plane.

Figure 1a shows the first data desired to be received in the first polarization, and Figure 1b shows the second data, which is another digital signal transmitted in the orthogonal second polarization. . If cross-polarized interference occurs in the transmission path, the signal obtained by synchronously detecting the first polarized wave will be the four signal points shown in Figure 1a and the lower-level interference component shown in Figure 1B. The result is a signal in which four signal points are superimposed.

Figures 2a and 2b are diagrams showing these superimposed signals. Figure 2a is a signal in which the interference component is superimposed in the same phase as the first data, and Figure 2b is a signal in which the interference component is superimposed with a phase difference of 45 degrees. Showing a signal. Figure 2 This a,
It can be seen from b that the interference component included in the first data is a constant value specific to the identification value of the second data.
Therefore, once the identification value of the second data is obtained, a constant value unique to this value is used as an interference component and is subtracted from the detected signal of the first polarization that has received cross-polarization interference, thereby eliminating the interference. It turns out that it can be removed. The above is the operating principle of interference cancellation.

FIG. 3 is a block diagram showing an example of a cross-polarization interference compensation circuit.

In the figure, all the signals of each part are multiple signals. Terminals 100 and 101 have first and second terminals, respectively.
A detection signal of the polarization is added. Therefore, second data as shown in FIG. 2 is superimposed on the terminal 100 as an interference component.

The detected signal of the second polarization input from the terminal 101 is converted into an estimated identification value of the second data by the next pre-identification circuit 1. At this time, if the signal distortion of the second data is below a certain level and the noise is not abnormally large, the error rate of estimated identification is sufficiently small. The obtained estimated identification value controls the signal line selector 34 in the next storage circuit 3, selects one unique to the estimated identification value from among the storage elements 30, 31, 32, and 33, and selects it. Connect to output terminal 104.

On the other hand, the first polarized detection signal is added to the subtracted terminal of the subtracter 20, and the value of the output terminal 104 of the storage circuit connected to the subtraction terminal of the subtracter 20 is subtracted as an interference component.

The output of the subtracter 20 is pure first data from which interference components have been removed. This output is applied to the next final identification circuit, and is applied to the first
The correct estimated discrimination value for the data will be obtained. Similarly, cross-polarization compensation circuits of the same type for the second data can be operated simultaneously.

FIG. 4 is a block diagram of another example of the cross-polarization compensation circuit. When non-regenerative relay is performed in a wireless transmission system, cross-polarization interference occurs multiple times by changing the propagation path length. Not only that, but its own signal also changes its propagation path length and returns as an interference component.

In such a case, the interference component comes to include intersymbol interference, and all values of several symbols before and after the received signal sample value (symbol) corresponding to the first and second data points to be identified are It will have an impact. Here, if the transmission path is linear, the effect is additive. Therefore, the interference components also include the first and second N symbols (N is a positive integer) before and after the identification data.
data needs to be recognized as a unique value.

In the block diagram of FIG. 4, when N=1, the identification value H for the first data H (kT)
Value H(-T) of one symbol before and after (excluding (o)),
H(T), V(-
The purpose is to associate unique values as interference components with the five symbols T), V(o), and V(T). Therefore, the memory circuit 3 includes the memory circuit 3 shown in FIG.
Reference numerals 1030 and 1030 are stored in the memory circuit 3' corresponding to the 5 symbols as those corresponding to the input terminals 103 of
Five input terminals 103' designated 1031, 1032, 1033 and 1034 are provided.

In addition, in order to obtain estimated identification values H^(T) and V^(T) of data subsequent to the time to be identified, a pre-discriminator 1' for the first data and one-symbol delay circuits 400 and 402 are used. A subsequent data identification value supply circuit 4 is provided. Estimated identification value H^(-T), V^(-T) of data preceding the time to be identified
As already determined values, H^(-H) is stored in the delay circuit 403, and V^(-T) is also stored in the same type of cross-polarization compensation circuit for the second data, so input these. Terminal 105 is supplied. As a result, the output terminal 104 of the memory circuit receives the identification values {H^(-T), H^(T), V^(-T), V^(o
)V^
(T)}, a unique interference component is output. Since block 2 in FIG. 4 is exactly the same as block 2 in FIG. 3, a correct estimated identification value of the first data can be obtained at the output terminal.

FIG. 5 is a diagram showing a subsequent data identification value supply circuit for a general value of N, and shows input terminals 107 and 10.
9, 110 and output terminal 108 are the fourth
Output terminal 2000 corresponding to the output terminal in the figure,
2001...(2000+N-1) and output terminal 2
100, 2101, ..., (2100+N) have identification values H(NT), H((N-1)1)T), H
(T) and V(NT), V((N-1))T), V(o)
are obtained and added to the input terminal of the memory circuit 3 as an address.

Next, consider a case where the state of cross-polarization interference changes. At this time, it is necessary to sequentially change each unique constant in the memory circuit.

FIG. 6 is a diagram showing a configuration in which a function for sequentially changing this unique constant is added to the configuration of FIG.
2, the reference numeral 3'' is the third in the memory circuit.
The difference from the diagram is that the contents of the memory element selected by the input terminal 103 can be changed to the value of the input terminal 111 via the signal line selector 35.
It is a graphic representation of a normal random access memory (RAM), and in that sense, the memory circuit 3 in Figure 3 is a read-only memory (ROM = Road Only memory).
Memory) to RAM (RAM = Random Access
Memory).

Here, block 5 represents a memory content modification circuit. First, the input and output of the final discriminator are applied to the input terminals 102 and 112, respectively, and both terminals are applied to the subtracter 51. The output of the subtracter 51 is an error component if input noise is ignored. This is a value specific to the identification value obtained by the pre-discriminator 1. Attenuator 52 multiplies the previous interference component by a constant α such that |α|<<1.

On the other hand, the value of the output terminal 104 of the memory circuit is read into another memory circuit 50 until the new memory content is determined, and this value and the output of the previous attenuator 52 are added by the adder 53 and the output terminal 111 going out to

The value of the output terminal 111 is read into the currently selected storage element of the next instantaneous storage circuit 3'', i.e. the signal to the terminal 103 is applied as an address to this series of active storage elements 3''. does not change, and the unique value selected by the signal is modified toward the output of the subtracter 51, that is, toward the compensated residual.

FIG. 7 is a diagram showing a configuration in which the storage content modification circuit 5 of FIG. 6 is added to the block diagram of FIG. 4.

As can be seen in this configuration example, the storage content modification circuit 5 has a general configuration and is the same as the configuration shown in FIG.

In the above, it has been assumed that the identification results of the pre-identification circuit 1 are always correct; however, in reality, quite a large amount of noise is superimposed on the input signal, so that the previous identification is often erroneous. In this case, the unique value read from the storage circuit is different from what is really needed, and the interference component cannot be removed based on this value.

The present invention is designed to improve this point.

Therefore, the prediscrimination circuit 1 is slightly modified so that when there is a high possibility that the discrimination value is erroneous, an error candidate detection output is output without outputting the normal discrimination value.

FIG. 8 shows identification areas for four signal points on the IQ phase plane for the four-phase phase modulation signal shown in FIG. 1a.

In the figure, 601 and 602 are normal identification boundary lines. A hatched area 600 near this boundary line
is the area for error candidate detection. That is, there is a high possibility that a signal generated within this area will cross the boundary lines 601 and 602 and give an erroneous identification value.

FIG. 9 is a diagram showing an embodiment of the present invention. The overall configuration is the same as that shown in FIG.

The difference from the same figure is that the prediscriminator 1 has an error candidate detection output as shown in FIG.
The point is that when the error candidate detection output is applied to the input terminal 103 of the storage circuit 3'', the value guided to the output terminal 104 by the signal line selector 34 is always zero.

Therefore, if the pre-discrimination circuit 1 makes an error discrimination, in most cases an error candidate detection output will be output. Therefore, the output terminal 10 of the memory circuit 3''
4 will have a zero output, and input terminal 1
This means that there will be no adverse effect on the signal coming into 00.

It is very easy to apply this idea to the more complex block diagram of FIG. First, the front identification circuit 1 of FIG. 4 is replaced with the one shown in FIG. 8, and the storage circuit 3' is replaced with the storage circuit 3'' shown in FIG. 9.

At this time, the error candidate detection output is also input to the subsequent data identification value supply circuit shown in FIG. Therefore, when an error candidate detection output appears in the output of the subsequent data identification value supply circuit, this is 'DON'T.
It is optional whether to ignore it as CARE' (unnecessary input) or to output zero output to the output terminal 104.

As described above, according to the present invention, cross-polarization interference compensation for digital signals can be performed in a perfect manner.
Moreover, since the circuit configuration is suitable for a digital circuit configuration, it can be said that it is suitable for deviceization.

Furthermore, as mentioned above, the present invention is based on compensation-based
Since it is performed in a band, there is no need to make any changes to circuits such as intermediate frequency circuits, and it is also characterized in that it operates effectively even with time-division signals from multiple stations.

[Brief explanation of the drawing]

Figure 1 a and b show the signal points of four-phase phase modulation.
A diagram for explaining the IQ phase plane, Figures 2a and b are diagrams for explaining a synchronous detection signal subjected to cross-polarization interference, and Figure 3 is a block diagram showing an example of a cross-polarization interference compensation circuit. , FIG. 4 is a block diagram showing another example of a cross-polarization interference compensation circuit, FIG. 5 is a diagram showing an example of a subsequent data identification value supply circuit, and FIGS. 6 and 7 are cross-polarization interference compensation circuits. FIG. 8 is a diagram for explaining the relationship between the discrimination boundary line of the prediscrimination circuit and the error candidate detection output, and FIG. 9 is a block diagram of one embodiment of the present invention. FIG. In the figure, 1... pre-identification circuit, 3, 3',
3''...Storage circuit, 20...Subtractor, 21...Final identification circuit, 5...Memory content correction circuit.

Claims (1)

[Claims] 1. A system for wirelessly transmitting first data and second data, which are independent digital signals, using first polarized waves and second polarized waves that are orthogonal to each other. a pre-discrimination circuit that receives the data of 2 as input and generates an error candidate detection output near the signal discrimination boundary line and outputs an estimated discrimination value for areas other than the vicinity of the discrimination boundary line; a storage circuit that supplies a constant other than zero corresponding to the discrimination value and supplies zero to the error candidate detection output of the prediscrimination circuit; and a subtraction that subtracts the output of the storage circuit from first data. a final identification circuit that estimates and identifies the first data from the output of the subtracter; and a storage content correction circuit that corrects and outputs the output of the storage circuit according to the input/output difference of the final identification circuit. obtaining first data from which interference of the second data with the first data due to cross-polarization interference occurring in the wireless transmission path is removed from the output of the final identification circuit; A cross-polarization compensating circuit, characterized in that the memory content of the currently selected memory element of the memory circuit is changed in response to the output, so as to correspond to a change in the state of cross-polarization interference.