JPS625504B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention receives a multiplexed information signal such as character information and graphic information that is superimposed and transmitted during the vertical retrace period of a television signal, and stores the pattern data signal in a memory. Regarding a multiplexed information receiving device that stores and displays images of multiplexed information on a display means such as a CRT, program signals of information images of a plurality of transmitted programs are stored in advance in a program memory and program selection is performed. If a program to be received and displayed is inputted from the circuit, but that program has not yet been transmitted, a menu of all the programs being transmitted at that time is displayed, and the receiving device The object of the present invention is to provide a device which reduces the psychological burden on the user due to only the television screen being displayed indefinitely in a standby state, and which facilitates the re-designation of programs. be.

EMBODIMENT OF THE INVENTION Hereinafter, the present invention will be described in detail with reference to the drawings showing one embodiment thereof.

First of all, Fig. 1 is a block diagram showing the general configuration of the entire system, in which 1 is a video detection circuit of a television receiver, and 2 is a circuit for transmitting multiplexed information such as characters and graphics.
A video signal is obtained in which a value information signal is superimposed on a horizontal scanning period during a vertical retrace period. 2, since the transmitted binary information signal is subject to waveform distortion due to the frequency characteristics of the transmission system and various distortions, the received signal is sliced at an appropriate level, etc.
This is a waveform shaping circuit that shapes a predetermined binary signal waveform as shown in the figure. 3 is a sync separation circuit, 4 is a color subcarrier (FSC) regeneration circuit, and 5 is a sync separation circuit 3.
vertical sync pulse and horizontal sync pulse from 2
To extract the signal during the period when the value information signal is superimposed (for example, the 20th H during the vertical retrace period)
A circuit that generates a 1H width gate pulse, and 6 a sampling clock for sampling the received binary information signal based on the color subcarrier etc. from the fcs regeneration circuit 4 and writing the received signal to the main memory. and a circuit that generates various clock pulses such as a memory clock for reading out the data.

7 is a sampling circuit, and 2 is a waveform shaping circuit 2.
The received binary information signal, which has been shaped into a value waveform, is sampled using a sampling clock, and then converted into serial and parallel signals, and is output as an 8-bit parallel output. Further, 8 is a detection circuit that detects a framing code FC signal of a specific code in the binary information signal from the output signal of the sampling circuit 7.
The phase of the generated clock is controlled by controlling the clock. That is, in the clock generation circuit 6, the clock line in CRI placed at the beginning of the received binary information signal is used until the FC signal is detected.
The fsc signal is used to generate a sampling clock synchronized with the fsc signal.
The color subcarrier from the reproducing circuit 4 is frequency-multiplyed and the frequency division phase is controlled by the FC detection output to receive 8/5 fsc synchronized with the color subcarrier and the FC detection output. Generates main memory clock.

Reference numeral 9 denotes a control circuit for controlling the writing and reading of pattern data in the binary information signal into the eight sets of main memories 10a to 10h, and this part is realized using processing calculation means such as a microcomputer.

In this device, first to eighth main memories 10a to 10h are used as main memories for storing pattern data in received binary information signals and displaying images of characters and figures as multiplexed information. 13 is a CRT for displaying the multi-page memory. Here, the multiplexed information to be received and displayed is character information or graphic information that consists of 248-bit picture elements in the horizontal direction and 204 horizontal scanning lines in the vertical direction. Then, main memory 1
0a to 10h are each at least 50592 (=248
×204) It has a storage capacity of more than 204 bits. And here, the sampling circuit 7 is 8
Since it is a bit parallel output type, the main memory 1
It is preferable to use eight 8K-bit memories in parallel as 0a to 10h, and perform parallel-to-serial conversion before outputting when reading.

On the other hand, numeral 12 is a program selection circuit that specifies what you wish to receive from the types of multiplexed information (hereinafter referred to as programs) such as multiple types of character information and graphic information that are multiplexed and transmitted in the television broadcast signal. ,
When a program is selected by a viewer, an 8-bit code signal representing the program is generated, and this is applied to the W/R control circuit 9, which controls only the pattern data of the binary information signal of the selected program. memory 1
This is a command to read and display from 0a to 10h.

In addition, 11 is the main memory 1 of the multi-page memory.
Eight sets of program number memories are stored at 0a to 10h to indicate which programs are stored therein using program number signals, and 14 is a main memory in which programs selected for display from the program designation circuit 12 are stored. 1
If the programs are not stored in 0a to 10h, the menu display screen of all the programs sent at that time (an example is shown in Figure 3) is displayed on the CRT.
This is a display control circuit for controlling the information image of the program to be displayed on the screen of No. 13 and, when the program is stored, to display the information image of the program. This display control circuit 14 does not receive the video signal from the video detection circuit 1 until the signal of the program that is instructed to be input is received.
It enters a standby state where it supplies the CRT 13 to display the television image, and after the signal of the program is received, the multiplexed information signal is transferred from the main memory 10.
It has the function of supplying it to the CRT 13 and displaying it.

FIG. 2 shows an aspect of the binary information signal multiplexed into the television signal received in the present invention. As shown in A, this binary information signal is superimposed on one of the horizontal scanning periods during the vertical retrace period of the television signal, here at the 20th H, and depending on the signal content, B, There are three types such as C and D. B is PCP (Page
Control Pdcket) signal is sent to the first field of each multiplexed information prior to transmitting the binary information signal for one page. C is
This is a CCP (Color Control Packet) signal, which is sent to the first field prior to transmitting a binary information signal for one line of character or graphic information to be transmitted and displayed. However, when displaying text or graphic information images only in black and white, this CCP
The signal is omitted. Furthermore, D is PDP (Pattern
This is a 248-bit pattern data signal for one line in the horizontal direction of an information image of characters and figures to be transmitted and displayed.
In this PDP signal, the data identification signals DI ₁ and DI ₂ are inserted into the control signal portion, each consisting of 4 bits each for a total of 8 bits (excluding parity bits), so that the pattern data signal can be used to identify one page of information image. The number of lines from the top is indicated.

The transmission mode of these signals is determined by the Radio Technology Council No. 4.
This is similar to what was written in the subcommittee's report for 1978.

Next, the detailed configuration and operation of the multi-page memories 10a to 10h, program memories 11a to 11h, and display control circuit 14, which are the characteristics of this device, will be described in the fourth section.
This will be explained with reference to Figure 5. Here, program numbers “15”, “90”, “01”, “32”, “71”, “47”, “
It is assumed that the information on the programs 55" and 55" is transmitted alternately in this order.

First, the received binary signal obtained by the sampling circuit 7 is supplied in the form of an 8-bit parallel signal, and is sent to eight sets of page memories 1 through a buffer amplifier 10B.
It is added to the input/output terminals 0a to 10h, and eight sets of program number memories 11 are sent via the buffer amplifier 11B.
It is added to the input/output terminals of a to 11h, and
It is added to the W/R control circuit 9W and the PCP detection circuit 11P. On the other hand, from the memory selection circuit 9S,
Page memories 10a to 10h and program number memory 1
A signal indicating which set of 1a to 11h is to be operated is added. During normal multiplexed information storage, the memory selection circuit 9S sequentially switches each memory each time a PCP detection output is generated from the PCP detection circuit 11P.

Now, it is assumed that all the circuits are reset manually from the program selection circuit 12 or are in an initial state due to automatic reset immediately after power is turned on. At this time, the memory selection circuit 9S
The flip-flop 9F inside is reset, and its Q output causes the counter selector 9CS to apply the output from the write counter 9WC to the decoder 9D. This write counter 9WC is reset at the same time as the above reset, and then the PCP detection circuit 1
Each time a PCP signal is detected in 1P, it is counted up by "1".

In this state, when the PCP signal of program "15" of the binary information signals is received for the first time after reset,
The PCP detection circuit 11P identifies the DI ₁ and DI ₂ signals, generates a PCP detection output, and then outputs the program number memory 11 only during the period of the program number signals PR ₁ and PR ₂ immediately after that.
Set a to 11h in a writable state. On the other hand, this
The write counter 9WC generates the first output "0001" due to the PCP detection output, which is applied to the decoder 9D via the selector 9CS, and an output is generated at its first terminal to be sent to the first program number memory 11a. added to. As a result, only the first program number memory 11a becomes writable at this time, and the program number signals PR ₁ and PR ₂ of the received PCP signal, that is, "15" are written therein. Furthermore, the output of this decoder 9D causes the first
The th page memory 10a is brought into operation,
Each time the PDP signal of the "15" program is received following the PCP signal, the writing state is set by the control signal from the W/R control circuit 9W, and the pattern data signals in the received PDP signal are sequentially written. be included.

Thus, the program number "15" is stored in the program memory 11a.
However, pattern data signals for one page of the program are written and stored in the page memory 10a.

Then, when a new PCP signal for the "90" program is received, the write counter 9WC is counted up based on the PCP detection output, and the 2nd bit of the decoder 9D is counted up.
An output is generated from the second terminal, the second program memory 11b and the page memory 10b are put into operation, and the program number "90" and the first page of the program are displayed.
Pattern data signals for pages are accumulated.

Similarly, when binary information signals of programs "01", "30"..."55" are received, those program numbers and pattern data signals are stored in the program memory.
1C... is stored in 11g and page memory 10g.

Next, when the binary information signal of program "15" is received again, it is stored in program memory 11h and page memory 1.
0h, and from now on, each program is stored in the program memory 11.
A... and the page memory 10a... are written and stored one by one with a difference of one.

In this way, the program numbers of the seven types of programs that have been transmitted and the pattern data signal for one page are stored in the program memories 11a to 11h and the page memories 10a to 10a.
10 hours, respectively.

Next, the display of information accumulated in this way will be explained.

First, the number of the program desired to be displayed is input from the keyboard 12K of the program selection circuit 12. Then, the input program number is transferred to the latch circuit 12.
After being latched to L, it is applied to the program comparison circuit 14PC of the display control circuit 14. This program comparison circuit 14PC includes the program number memories 11a to 1 described above.
The program numbers sequentially read from 1h are added as the other input and compared here.

At this time, the flip-flop 9F of the memory selection circuit 9S is selected by inputting an instruction from the keyboard 12K.
is set, and counter selector 9CS is switched to apply the output from search counter 9SC to decoder 9D. This search counter 9
The SC is cleared by a vertical pulse and counts 8 or more horizontal pulses during the vertical retrace period, and here it is assumed that 15 horizontal pulses are counted from the 10th H to the 25th H. First, when a count output of "0001" is output from the search counter 9SC in the 10th H, this is added to the decoder 9D via the selector 9SC, and the program memory 11a and page are output from the first terminal. memory 10
a is put into operation. Then, the program number "15" read from the program memory 11a and the program number input from the keyboard 12K are compared, and if they do not match, the program moves to the 11th H, and a count of "0010" is generated from the search counter 9SC. The output puts the second program memory 11b and the page memory 10b into an operating state, and the program number "90" in the program memory 11b is read out and compared. From then on, this sequential search comparison operation is repeated until the 24th H.

If the program number input from the keyboard 12K matches the program number from the program memories 11a to 11h during this process, a match output is generated from the program comparison circuit 14PC, and the search counter 9SC is thereby set to the counting state at that time. From then on, the program memory 11a at that time is
Page memories 10a to 10h corresponding to ~11h
A pattern data signal is read out from the selector 14S of the display control circuit 14 and applied to the CRT 13 via the buffer amplifier 14B. For example, if program number "90" is input from the keyboard 12K and the same program number is stored in the program memory 11b, a match output is generated at the output "0010" of the search counter 9SC, and from then on, the page memory 10b The pattern data signal of the "90" program is read out from the program.

When a new binary information signal of the program is further transmitted and received after the display is started due to the matching of the program desired to be received, the page memory 10a in which the pattern data signal in the PDP signal is selected ~10h New data is written to, for example, 10b, and the display contents are updated one after another.
Of course, when a desired program to be displayed is specified using the keyboard 12K, only the pattern data signal of the desired program is written into the page memories 10a to 10h selected at that time.
A write clock controlled by a W/R control circuit is applied.

However, in this way, the page memory 10a~
Even if the pattern data signal is read from 10h, if an input to instruct standby display is given from the keyboard 12K of the program selection circuit 12, the standby control circuit 14SB outputs a low level output at the beginning of input of the program selection instruction. occurs, and at that time the output of the timer circuit 14T, which will be described later, is also at a low level.
Buffer amplifier 14B via OR gate 14G
is switched to the television side, and the television video signal from the video detection circuit 1 is supplied to the CRT 13 to display a normal television screen. Then, when the PCP signal of the specified program is received, a high level output is generated by the detection output from the program comparison circuit 14PC, the buffer amplifier 14B is switched to the information display side, and from then on, the information of the program is displayed. It is displayed for a certain period of time and then returns to the TV screen display. This is called a standby reception state.

The above is the operation when the program inputted by the program selection circuit 12 has been transmitted and stored, but if the program inputted by the instruction is actually a program that has not been transmitted, A specific character image as shown in FIG. 3 indicates that the designated program has not been transmitted. The parts for this will be explained below.

In order to display a character image as shown in FIG. 3, a program display circuit 14P for creating a video signal for displaying the program display image and a control circuit 14C for controlling the program display circuit 14P are used. First, in the program display circuit 14P, a pattern signal for displaying "The program being sent now is" and "is." shown in FIG. 3 is stored in the fixed pattern memory 14FM made up of ROM. has been done. On the other hand, in the variable pattern memory 14AM composed of RAM, "01, 15, 32, 47, 55, 7" in FIG.
1,90'' is stored, which is a pattern signal for displaying a program of multiplexed information that is currently being transmitted and stored.

In order to store the program number in the variable pattern memory 14AM in this way, the above-mentioned program memories 11a to
When storing the program number and pattern data signal of the received binary information signal in the program memories 11a to 11h and the page memories 10a to 10h,
Received program number signals PR ₁ , PR ₂ supplied to
The reset pulse is generated at the 9th self-reset when the data is taken into the circuit 14IC that performs size judgment and editing in synchronization with the count of the write counter, and the write counter 9WC has finished storing it in 8 sets of memories. At that time, the circuit 14IC that performs size judgment and editing judges the size of the seven types of program numbers taken in, rearranges them in ascending order, and outputs them. A microcomputer or the like may be used as this circuit 14IC. Then, the character generator 14CG generates a display pattern signal corresponding to this program number and writes it into the variable pattern memory 14AM. The control circuit 14C controls writing to the variable pattern memory 14AM using both horizontal and vertical pulses, clock pulses, a chip select signal from the decoder 9D, and the like.

Then, as described above, the program number desired to be displayed is input from the keyboard 12K of the program selection circuit 12, and the program memory 1 is input by the search counter 9SC.
Sequential selection of 1a to 11h and program comparison circuit 14PC
However, if a program that has not been transmitted is specified, the program comparison circuit 14PC will not output any matching output. For this reason, the search counter 9SC can only read counts up to the 24th H, and is self-reset at the 25th H. Therefore, when the search counter 9SC is self-reset and no output is output from any terminal of the decoder 9D, and when no matching output is generated from the program comparison circuit 14PC, the control recirculation 14 operates to・Variable pattern memory 1 from both vertical pulses and clock pulses
4AM and the fixed pattern memory 14FM to read out the pattern signals stored in each, and switch the pattern selector 14PS to create a pattern signal for displaying a specific character image as shown in FIG. The signal is supplied to the selector 14S.

This selector 14S includes a program comparison circuit 14.
The flip-flop 14 is reset by the coincidence output signal from the PC and the self-reset pulse of the search counter 9SC, which is reset by the vertical pulse.
A gate pulse is added to display an information image such as a character image only after the 25th H in the vertical scanning period from FF.

Therefore, when the designated input program is not being transmitted, the pattern signals of the pattern memories 14AM and 14FM are taken out from the selector 14S. At this time, a timer 14T consisting of a time constant circuit and a flip-flop is controlled by the self-reset pulse of the search counter to generate a high level output for a certain period of time, for example, one minute, and switch the buffer amplifier 14B to the information display side. By supplying the display signal of the character and figure image from the display selector 14S to the CRT 13 from the buffer amplifier 14B, the character and figure image as shown in FIG. 3 is displayed for a certain period of time. Then, the screen is switched again to the television side and a normal television screen is displayed.

Therefore, by looking at the screen of the program menu image as shown in Figure 3, the user can immediately know that he has input an instruction for a program that has not been transmitted, and by looking at the menu for that program, he can select the program that is being transmitted. Since the selection of instruction input can be re-selected, it is possible to obtain something very convenient. In addition, no image appears even when an instruction is input, which reduces the psychological burden on the user and provides a good usability.

In addition, in the above embodiment, a maximum of 8 programs can be stored in the multi-page memory.
Although the number of programs is set as 1, it is also possible to have more. Further, the number of program numbers stored in the program memory or the size determination and editing circuit may be greater than the number of programs stored in the multi-page memory. Further, instead of a multi-page memory, a memory for only one page may be used, and even a program number memory that can store program signals of all transmitted programs is sufficient.

As described above in detail, according to the present invention, in a multiplexed information signal receiving device having a function of standby reception display state, when it is input from the program selection circuit that a program that has not been transmitted should be received and displayed. By displaying a menu of all programs being transmitted at that time, it is possible to clearly indicate that the program is not being transmitted, and also displaying a menu of all programs that can be selected at that time. By doing so, it is possible to obtain a convenient device that can notify the user of re-input or changes to the program being transmitted. Furthermore, it is possible to prevent the situation where the information image is not displayed only on the TV screen even if the input is made by mistake during the standby reception display state, which reduces the psychological burden on the user and improves the usability. It is possible to obtain good equipment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multiplexed information receiving device according to an embodiment of the present invention, FIG. 2 is a waveform diagram of a received signal, FIG. 3 is a front view of the display state of the same device, and FIGS. The figure is a detailed block diagram of the main parts. 1... Video detection circuit, 2... Waveform shaping circuit, 3
... Synchronization separation circuit, 4 ... fsc regeneration circuit, 5 ...
Gate pulse generation circuit, 6... Clock generation circuit, 7... Sampling circuit, 8... FC detection circuit, 9... W/R control circuit, 10... Main memory (multi-page memory), 11... Program memory ,1
2...Program selection circuit, B...CRT, 14...Display control circuit.

Claims (1)

[Claims] 1. In a device that receives a multiplexed information signal such as character information of a plurality of programs transmitted in a superimposed manner during the vertical retrace of a television signal and displays the multiplexed information, the transmitted multiplexing A program storage means for storing program signals of all programs of information, and when a program of multiplexed information to be received and displayed is inputted from a program selection circuit until the multiplexed information signal of that program is received. display control means for displaying a normal television image on the display means and for displaying the multiplexed information signal of the designated program when the multiplexed information signal is received; menu display means for displaying on the display means a specific character image indicating a menu of all programs stored in the program storage means for a certain period of time when the program stored in the program is not a program stored in the program storage means; A multiplexed information receiving device comprising: