JPS6254891A - Write recovery circuit - Google Patents

Abstract

PURPOSE:To shorten write recovery time and to read at high speed by providing a shift-detection circuit, letting it to generate a pulse when detecting a timing when the control signal of a memory shifts from writing state to reading state, and equalizing a compensation data line by using the said detection pulse. CONSTITUTION:The shift detection signal WEP is supplied to the gate of the equalizer MOS transistor 51 of the write recovery circuit 50, and the transistor 51 turns on, then a current flows from the stray capacity C17 of a data line 21 to the stray capacity C18 of a data line 22 to lower the potential V21 of the data line 21. At the same time, the potential V22 of the data line 22 begins to rise. Because the MOS transistor 51 is comparatively a small area, its driving capability is comparatively small, but it becomes much more smaller with the lapse of time because, the voltage VDS between the drain and source of the transistor 51 decreases with the lapses of time. Accordingly, during the period when the signal WEP is 'Hi', the potentials V21 and V22 of both data lines 21 and 22 approach closer each other.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a memory write recovery circuit.

[Summary of the invention]

The present invention detects the point in time when a memory control signal transitions from a write state to a read state, generates a pulse, and uses this detection pulse to equalize complementary data lines, thereby shortening write recovery time and increasing speed. This enables reading.

[Conventional technology]

Conventionally, electronic computers' internal storage devices or external storage devices (
A data line driving circuit is used to obtain a read signal from the memory.

First, a conventional data line drive circuit will be described with reference to FIG.

FIG. 5 shows an example of the configuration of the main parts of a conventional memory (RAM).

In this FIG. 5, (10) shows the memory matrix as a whole, and any memory cell (
11) is connected to a word line (12), and is also connected to a pair of bit lines (13) and (14). This memory cell (11) has a flip-flop circuit consisting of a load resistor (not shown) and a MOS (MOS) transistor, and is of a static type that stores information by turning on and off a current. One end of each of the bit line (13) and bit line (14) is connected to the sources of a pair of N-channel MOS transistors (15) and (16) as active loads, respectively.
and (16) have their gates and drains both connected to the power supply terminal P, and are each turned into a diode.

The other ends of the bit line (13) and bit line (14) are connected to the drains of N-channel MOS transistors (17) and (18), respectively, and both MO3) transistors (1
The gates of 7) and (18) are connected to a column selection terminal (19).

(20) shows the data line driving circuit as a whole, and a pair of data lines (2
1) and a data line (22) are respectively connected to the power supply terminal P via the sources and drains of N-channel MO3I transistors (23) and (24) as a pair of active loads. The gates of the MOS transistors (23) and (24) are both connected to the WE signal input terminal (25). W
Since the π signal becomes 1H1'' at the time of reading, both MO3
) At the time of reading, the transistors (23) and (24) are respectively converted into diodes as shown by broken lines.

(31) is a readout amplifier, for example, current t
The inverting input terminal and the non-inverting input terminal are connected to a data line (21) and a data line (21), respectively.
22). The output of the read amplifier (31) is sent to the data input/output terminal (3) via the inverting amplifier (32).
0).

(40) shows the write circuit as a whole, and the data signal supplied from the input/output terminal (30) is inverted by the first inverter (41) and sent to one NOR circuit via the second inverter (42). (43) and directly to the other NOR circuit (44) (
The outputs of 43) and (44) are connected to the data line (
21) and data line (22). Further, the WE multiplied signal is supplied from the terminal (47) to both NOR circuits (43) and (44), respectively.

In write mode or read mode, a word line (12) is selected by an X decoder (not shown), and all memory cells connected to this word line (12) are activated, and a Y decoder (not shown) A predetermined pair of bit lines (13) and bit lines (14) from
) is supplied to the terminal (19), and the MOS transistors (17) and (18)
is turned on, and a desired memory cell (11) is selected.

In the case of writing, the terminal (2) of the data line drive circuit (20)
5) and the WE (inverted write enable) signal supplied to the terminal (27) of the write circuit (40) is set to Lo''', and "Hi" data is sent from the input terminal (30) to the write circuit (40). A signal is provided.

Both MO3I transistors (
23) and (24) are turned off, the two inputs of one NOR circuit (43) of the write circuit (40) are set to "Hi" and "Lo", and the other NOR circuit (43) is set to "Hi" and "Lo".
Both of the two inputs in 4) are set to "@Lo".

The “Lo” output of one NOR circuit (43) is inverted by the inverter (45), and the potential of the data line (21) is “H”.
i”, the “Hi” output of the other NOR circuit (44) is inverted by the inverter (46), and the data line (2
The potential of 2) becomes “Lo”. At this time, the MOS transistors (15) to (18) of the memory matrix (10)
are all in the on state, and the desired memory is connected from the input terminal (30) through the third inverter (45) of the write circuit (40), the data line (21), the MOS transistor (17), and the bit line (13). A first write path reaching the cell (11) is formed, and the memory cell (11) is connected from the fourth inverter (46) through the data line (22), the MOS transistor (18) and the bit line (14).
) is formed to write data into the memory cell (11).

In the case of reading, the terminal (2) of the data line drive circuit (20)
5) and the WE multiplier signal "Hi" supplied to the terminal (47) of the write circuit (40), both MO3) transistors (23) and (24) of the data line drive circuit (20).
is turned on, and the outputs of both NOR circuits (43) and (44) of the write circuit (40) are set to "Lo" regardless of their other inputs, and data writing is prohibited. be done. Note that in this case, the write circuit (4
0) is appropriately placed in a high impedance state.

Assuming that the MOS transistor connected to the bit line (13) of the flip-flop (not shown) in the memory cell (11) is in the on state, the data line drive circuit (20
) from the MOS transistor (23) to the data line (21)
, selection MO3) transistor (17) and bit line (
The data line current 10 flows into the memory cell (11) through the path 13). Further, the active load MOS transistor (15) connected to one end of the bit line (13) is in an on state as the power supply voltage vDD is supplied to its gate, and the memory cell ( Bit line current 1B flows into 11). The sum of this bit line current 1B and the above-mentioned data line current 1o becomes the sink current IN of the memory cell (11).

On the other hand, the MOS transistor (not shown) connected to the bit line (14) in the memory cell (11) is in an off state, and the bit line (14) and data line (22) are connected to the memory cell (11). No current flows.

Therefore, the potentials V13 and V14 of the bit line (13) and the bit line (14) are different, and these two different potentials are used as information of the desired memory cell (11) on the data line (21).
and a read amplifier (31) through the data line (22).
is supplied to both input terminals of The difference signal between the input signals is amplified, and the unbalanced output signal of the read amplifier 1B (31) is supplied from the inverting amplifier (32) to the input/output terminal (30).

When the power supply voltage VDD is, for example, 5v, (the higher one)
The potential Vt4 of the bit line (14) becomes, for example, about 3.2 V due to the influence of the threshold voltage Vth (about 0.7 V) of the MOS transistor (16) and the substrate effect Δv th (about 1.IV). Further, the potential vt3 of the bit line (13) is the sink current IM of the memory cell (11).
is, for example, 100 μA, it becomes slightly lower than V14, for example, about 2.9 V, due to the voltage drop within the MOS transistor (15).

Also, the potential V of the data line (21) and the data line (22)
21 and V22 are approximately equal to V13 and Vt+, respectively, for the same reason as described above.

[Problem that the invention seeks to solve]

However, in the conventional memory shown in FIG. 5, the junction capacitances Ctt and Cts of the column selection MO5 transistors (17) and (18) are equal to the stray capacitances of the data line (21) and data line (22), respectively. Become.

For example, in a memory with a capacity of 64 bits, the number of columns is 256, with data lines (21) and data lines (22).
A fairly large stray capacitance is added to the .

Therefore, when transitioning from the write mode to the read mode, the WE double signal becomes "Hi" and the active load MO3
Even if the I-transistors (23) and (24) are turned on, the potential v2 of the data line (22)! is the stray capacitance C1e and the equivalent resistance value R2 of the MOS transistor (24).
According to the time constant Ct@R24 determined by 4, from Ov,
It takes quite a long time, for example 50 nS, to recover (write recovery) to a predetermined value, for example about 3V, which is suitable as the input potential of the read amplifier (31).

Therefore, the conventional memory has a problem in that the write recovery time T wrc is long as shown in FIG. 6, which hinders high-speed data reading.

In view of the above, an object of the present invention is to provide a write recovery circuit that shortens write recovery time.

[Means for solving problems]

The present invention provides a complementary data line having one end connected to a power supply via an active load and the other end connected to a column selection switching element and a write circuit of a memory matrix;
It is equipped with an equalizing switching element connected between the complementary data lines and a transition detection circuit that detects the transition of a control signal that controls the write state and read state of data and generates a detection pulse. This is a write recovery circuit configured to supply a detection pulse from a transition detection circuit to an equalizing switching element when the state transitions from a read state to a read state.

[Effect]

According to this configuration, the data lines are equalized when the memory transitions from the write state to the read state, so the time for the data line potential to recover to a predetermined value is shortened, and high-speed reading is performed. .

〔Example〕

Hereinafter, one embodiment of the write recovery circuit according to the present invention will be described with reference to FIGS. 1 to 4.

FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals and redundant explanation will be omitted.

In FIG. 1, (50) shows the write recovery circuit as a whole, and the drain and source of the N-channel MOS transistor (51) for equalization are connected to both data lines (2
1) and (22), and its gate is connected to the terminal (52). Both data lines (21) and (22) are connected to the power supply terminal P via the sources and drains of active load MOS transistors (53) and (54), respectively.
O3) The gates of transistors (53) and (54) are connected to terminal (55). The area of the equalizing MOS transistor (51) is the same as that of the active load MOS transistor (53).
), (54) is set to, for example, 1/4 of the area. The write/read MR) transition detection circuit (60) is supplied with the WE times signal from its input terminal (61), and
The W/R transition detection signal WEP is supplied to the terminal (52) of the write recovery circuit (50), and the write circuit (4
A signal WEI delayed by WE times the signal is commonly supplied to the terminal (47) of the write recovery circuit (50) and the terminal (55) of the write recovery circuit (50). The rest of the structure is the same as that shown in FIG.

The details of the configuration of the −/R transition detection circuit (60) are shown in FIG. 2. In FIG. ) is supplied to one input terminal of the NAND circuit (65) and directly to the other input terminal.A capacitor of an appropriate capacity is loaded on the output terminal of the first stage inverter (62). The required delay time τ is set.The output of the NAND circuit (65) is connected to the inverter (66).
) and output as a transition detection signal WEP. Further, the WE multiplied signal at the terminal (61) is subjected to a predetermined delay by an inverter (67) loaded with an appropriate capacitor, and is inverted by an inverter (68), so that WE! Output as a signal.

The operation of this embodiment is as follows.

As shown in Fig. 3, the V/E signal ■ of the terminal (61) is
At the transition start time to, the voltage starts to rise from @Lo to Hl, and when it reaches Hl at the transition end time t1,
As shown in FIG. 3B, the signal (2) of the third inverter (64) starts falling from "Hi" to "Lo" at a delay time t2 delayed by a predetermined time τ from the transition start time to. As shown in FIG. 3C, the output ◎ of the NAND circuit (65) is "Lo" only during the period from the transition end time t1 to the delay time t2 when its input is simultaneously "Hi".
becomes.

The negative output pulse ◎ of this NAND circuit (65) is inverted by the inverter (66), and a positive pulse ◎ as shown in the third diagram is output as the transition detection signal WBP. The pulse width of this transition detection signal WEP is set to, for example, 5 nS.

As shown in FIG. 4B, the above-described transition detection signal WEP is supplied to the gate of the equalizing MO3 transistor (51) of the write recovery circuit (50), and the MO3I transistor (51) is turned on.

Then, the stray capacitance CL of the data line (21) passes through this MOS transistor (51)? to the data line (22
) current flows into the floating capacitance i1 Ct@, and as shown in Figure 4A, the potential V21 of the data line (21) begins to fall, and at the same time the potential V22 of the r;T line (22) begins to rise. . As mentioned above, since the MOS transistor (51) has a relatively small area, its driving capability (equivalent conductance) is also relatively small, and furthermore, its drain-source voltage VOS decreases over time. MOS)
The driving ability of the transistor (51) further decreases over time. Therefore, as shown in FIGS. 4A and 4B, during the period when the transition detection pulse WEP is 1H1'', the potentials V2 and V2t of both data lines (21) and (22) approach each other but match. In other words, in this embodiment, it is weakly equalized.

On the other hand, as shown in FIG. 3E, at time t2 when the transition detection pulse WEP starts to fall, the WBI signal becomes @ n
Since t is 11, the active load MOS transistor (5
3) and (54) are turned on, and as shown in FIG.
31) has an appropriate potential as an input.

In this embodiment, since the potential V22 of the data line (22) is considerably increased by the equalization operation as described above, the time for recovery to a required value is shortened to, for example, 40 nS.

〔Effect of the invention〕

As described in detail above, according to the present invention, a pulse is generated by detecting the WE multiplication signal transition that controls writing and reading of the memory, and this detection pulse is used to equalize the complementary data line. Therefore, a write recovery circuit can be obtained in which the time required for the potential of the data line to recover to a predetermined value is shortened.

[Brief explanation of drawings]

Figure 1 is a wiring diagram showing the configuration of an embodiment of the ° write recovery circuit according to the present invention, Figure 2 is a wiring diagram showing the configuration of the main part of the embodiment of Figure 1, and Figure 3 is the wiring diagram of the embodiment of Figure 2. 4 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 1, and FIG. 5 is a configuration example of the main part of a conventional memory. The connection diagram shown in FIG. 6 is a waveform diagram for explaining the present invention. α [is the memory matrix, (17), (18) is the column selection MO3) transistor, (21), <2
2) is a complementary data line, (40) is a write circuit, (50
) is the write recovery circuit, (51) is the equalization MO
S transistors, (53) and (54) are active load MOS transistors, and (60) is a transition detection circuit. Figure 2 Kazumi, Ikotsu n4L4A time chart Figure 3 1'X81! ! Refer to figure 4 of Tsubasu's skin pattern.

Claims (1)

[Claims] One end is connected to a power supply via an active load, and the other end is connected between a complementary data line connected to a column selection switching element and a write circuit of a memory matrix, and the complementary data line. an equalizing switching element, and a transition detection circuit that detects a transition of a control signal that controls a data write state and a read state and generates a detection pulse, when the control signal transitions from a write state to a read state. A write recovery circuit characterized in that: the detection pulse of the transition detection circuit is supplied to the equalization switching element.