JPS6253848B2 - - Google Patents

Info

Publication number
JPS6253848B2
JPS6253848B2 JP60001615A JP161585A JPS6253848B2 JP S6253848 B2 JPS6253848 B2 JP S6253848B2 JP 60001615 A JP60001615 A JP 60001615A JP 161585 A JP161585 A JP 161585A JP S6253848 B2 JPS6253848 B2 JP S6253848B2
Authority
JP
Japan
Prior art keywords
reset
switches
microcomputer
command
point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP60001615A
Other languages
Japanese (ja)
Other versions
JPS60167018A (en
Inventor
Noryuki Sakamoto
Fuminori Hirose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60001615A priority Critical patent/JPS60167018A/en
Publication of JPS60167018A publication Critical patent/JPS60167018A/en
Publication of JPS6253848B2 publication Critical patent/JPS6253848B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明はマイクロコンピユータ等の電子回路を
初期状態に設定するためのリセツト装置に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reset device for setting an electronic circuit such as a microcomputer to an initial state.

マイクロコンピユータを用いる機器において
は、動作を開始する前にマイクロコンピユータを
リセツトし、プログラムを初期状態に戻す必要が
ある。
In devices that use a microcomputer, it is necessary to reset the microcomputer and return the program to its initial state before starting operation.

このため、従来より、第1図に示すようにマイ
クロコンピユータ1のリセツト端子1aを電源ラ
イン2とアース間に接続され抵抗Rとコンデンサ
Cの接続点に接続し、電源投入時、電源ライン2
の電位が第2図aに示すように瞬時に立上るのに
対して、リセツト端子1aの電位を第2図bに示
すように抵抗RとコンデンサCで決まる時定数に
したがつてゆるやかに立上らせ、両電位a,bの
立上り時間差を利用してリセツト端子1aを瞬間
的に“L”レベルにしてマイクロコンピユータ1
をリセツトするようにしている。ところが、この
場合には電源の立上り時に一度電圧が下がつたり
するいわゆるチヤタリングによる誤動作が生じ、
確実にリセツトできない場合がある。
For this reason, conventionally, as shown in Fig. 1, the reset terminal 1a of the microcomputer 1 is connected between the power supply line 2 and the ground, and connected to the connection point between the resistor R and the capacitor C.
While the potential at the reset terminal 1a rises instantaneously as shown in Figure 2a, the potential at the reset terminal 1a rises slowly according to the time constant determined by the resistor R and capacitor C as shown in Figure 2b. The microcomputer 1 uses the rise time difference between the potentials a and b to momentarily set the reset terminal 1a to the "L" level.
I am trying to reset it. However, in this case, malfunctions occur due to so-called chattering, where the voltage drops once when the power is turned on.
It may not be possible to reset reliably.

これを防止するためには、手動で操作されるリ
セツト釦を設け、このリセツト釦によつてリセツ
トスイツチを閉じ、マイクロコンピユータ1のリ
セツト端子1aを所定の電位点(たとえばアー
ス)に接続するようにしてもよいが、特にメモリ
ー機能をもつ場合には、誤つてリセツト釦を操作
するとメモリーされた内容自体が消されてしまう
おそれもあり、そのためリセツト釦を機器の裏側
など操作しにくい場所に設ける必要があり、その
結果リセツト操作自体を忘れてしまうという不都
合がある。
In order to prevent this, a manually operated reset button is provided, which closes the reset switch and connects the reset terminal 1a of the microcomputer 1 to a predetermined potential point (for example, ground). However, especially if the device has a memory function, there is a risk that the stored contents will be erased if the reset button is pressed by mistake, so it is necessary to place the reset button in a location that is difficult to operate, such as on the back of the device. This results in the inconvenience of forgetting the reset operation itself.

もちろん、第3図に示すようにマイクロコンピ
ユータ1に3つのリセツト端子1a,1b,1c
を設け、これら3つのリセツト端子1a,1b,
1cに3個のリセツトスイツチ3,4,5を接続
し、これら3つのスイツチを同時に閉じたときの
みリセツトがかかるようにすることも考えられ
る。このようにすればスイツチ3,4,5のリセ
ツト釦を機器の前面に配置しても誤操作のおそれ
はなく、またリセツトのかけ忘れも防止できる
が、このときにはマイクロコンピユータ1内にス
イツチ3,4,5の開閉状態を識別する特別なプ
ログラムを組込まなければならないという新たな
問題が発生する。
Of course, as shown in FIG. 3, the microcomputer 1 has three reset terminals 1a, 1b, 1c.
are provided, and these three reset terminals 1a, 1b,
It is also conceivable to connect three reset switches 3, 4, and 5 to 1c so that the reset is applied only when these three switches are closed at the same time. In this way, even if the reset buttons for switches 3, 4, and 5 are placed on the front of the device, there is no risk of erroneous operation, and it is also possible to prevent forgetting to reset them. , 5, a new problem arises in that a special program must be installed to identify the open and closed states of the terminals.

本発明はこのような問題を解決するリセツト装
置を提供するものである。
The present invention provides a reset device that solves these problems.

以下本発明の一実施例を第4図とともに説明す
る。
An embodiment of the present invention will be described below with reference to FIG.

第4図において、S1〜S5はマイクロコンピユー
タ1にデータの書き込み、読み出し等の所定の指
令を与えるための指令スイツチであり、このうち
スイツチS1,S3,S5は互に連動する2回路のスイ
ツチS1-1,S1-2,S3-1,S3-2,S5-1,S5-2で構成
されている。このうち一方のスイツチS1-1
S3-1,S5-1は他の指令スイツチS2,S4と同様に所
定の指令を与えるためのスイツチとして動作し、
他方のスイツチS1-2,S3-2,S5-2は、マイクロコ
ンピユータ1のリセツト端子1aとアース間に直
列に接続されている。
In FIG. 4, S 1 to S 5 are command switches for giving predetermined commands such as writing and reading data to the microcomputer 1, and among these, switches S 1 , S 3 , and S 5 are interlocked with each other. It consists of two circuit switches S 1-1 , S 1-2 , S 3-1 , S 3-2 , S 5-1 , and S 5-2 . One of these switches S 1-1 ,
S 3-1 and S 5-1 operate as switches for giving predetermined commands like the other command switches S 2 and S 4 ,
The other switches S 1-2 , S 3-2 , and S 5-2 are connected in series between the reset terminal 1a of the microcomputer 1 and ground.

上記構成において、スイツチS1〜S5をそれぞれ
単独に閉じれば、マイクロコンピユータ1に所定
の指令を与えることができ、スイツチS1,S3,S5
を同時に閉じたときのみリセツト端子1aがアー
スに接続され、マイクロコンピユータ1がリセツ
トされる。
In the above configuration, if the switches S 1 to S 5 are individually closed, a predetermined command can be given to the microcomputer 1, and the switches S 1 , S 3 , S 5
Only when both are closed at the same time, the reset terminal 1a is connected to ground, and the microcomputer 1 is reset.

このように本発明によれば、 (1) スイツチの手動操作によつてリセツトをかけ
ることができるから、電源の立上りを利用する
ものに比べてリセツト動作を確実にすることが
できる。
As described above, according to the present invention, (1) Since the reset can be performed by manual operation of the switch, the reset operation can be performed more reliably than when the power supply is turned on.

(2) 電子回路のリセツトポイントを直接所定の電
位点に接続してリセツトをかけるものであるか
ら、複数のスイツチの開閉状態を識別するため
のプログラムも不要になる。
(2) Since the reset point of the electronic circuit is directly connected to a predetermined potential point to apply a reset, there is no need for a program to identify the open/closed states of multiple switches.

(3) 複数のスイツチが同時に閉じたときだけリセ
ツトがかかるから、リセツト釦を機器の前面等
に設けても誤つてリセツトしたり、リセツトし
忘れたりするおそれがなくなる。
(3) Since the reset is activated only when multiple switches are closed at the same time, there is no risk of accidentally resetting or forgetting to reset even if the reset button is provided on the front of the device.

(4) リセツト用のスイツチが指令スイツチと連動
しているから、リセツト釦を指令釦で兼用する
ことができ、したがつて部品の取付スペースの
点でも有利になる。
(4) Since the reset switch is interlocked with the command switch, the reset button can also be used as the command button, which is advantageous in terms of mounting space for parts.

という優れた効果が得られる。This excellent effect can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の回路図、第2図はその動作説
明図、第3図は他の従来例の回路図、第4図は本
発明の一実施例の回路図である。 1…マイクロコンピユータ、1a…リセツト端
子、2…電源ライン、S1-1,S2,S3-1,S4,S5-1
…指令スイツチ、S1-2,S3-2,S5-2…リセツトス
イツチ。
FIG. 1 is a circuit diagram of a conventional example, FIG. 2 is an explanatory diagram of its operation, FIG. 3 is a circuit diagram of another conventional example, and FIG. 4 is a circuit diagram of an embodiment of the present invention. 1...Microcomputer, 1a...Reset terminal, 2...Power line, S1-1 , S2, S3-1 , S4 , S5-1
...Command switch, S1-2 , S3-2 , S5-2 ...Reset switch.

Claims (1)

【特許請求の範囲】[Claims] 1 回路網中のリセツトポイントを所定の電位点
に接続したとき、この回路網を初期状態にリセツ
トするように構成した電子回路と、上記電子回路
に所定の動作を指令する複数の指令スイツチと、
上記複数の指令スイツチに連動する複数のリセツ
トスイツチとを備え、上記複数のリセツトスイツ
チを、上記回路網中のリセツトポイントと上記所
定の電位点との間に直列に接続したリセツト装
置。
1. An electronic circuit configured to reset the circuit network to an initial state when a reset point in the circuit network is connected to a predetermined potential point, and a plurality of command switches that command the electronic circuit to perform predetermined operations;
A reset device comprising a plurality of reset switches interlocked with the plurality of command switches, the plurality of reset switches being connected in series between a reset point in the circuit network and the predetermined potential point.
JP60001615A 1985-01-09 1985-01-09 Resetting device Granted JPS60167018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60001615A JPS60167018A (en) 1985-01-09 1985-01-09 Resetting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60001615A JPS60167018A (en) 1985-01-09 1985-01-09 Resetting device

Publications (2)

Publication Number Publication Date
JPS60167018A JPS60167018A (en) 1985-08-30
JPS6253848B2 true JPS6253848B2 (en) 1987-11-12

Family

ID=11506417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60001615A Granted JPS60167018A (en) 1985-01-09 1985-01-09 Resetting device

Country Status (1)

Country Link
JP (1) JPS60167018A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03127937U (en) * 1990-03-31 1991-12-24

Also Published As

Publication number Publication date
JPS60167018A (en) 1985-08-30

Similar Documents

Publication Publication Date Title
US5382839A (en) Power supply control circuit for use in IC memory card
EP0426663B1 (en) Apparatus for defined switching of a microcomputer to standby mode
JPH0697429B2 (en) Low voltage blocking controller
US4463271A (en) Transistor switching circuitry having hysteresis
JPS6253848B2 (en)
EP0661714B1 (en) Circuit device and corresponding method for resetting non-volatile and electrically programmable memory devices
JPH0142002B2 (en)
JPS587710Y2 (en) indicator device
JPH0249040Y2 (en)
KR890001224B1 (en) Reset and data protecting circuit
JPH069553Y2 (en) Power supply circuit
JPS59152836U (en) electronic circuit equipment
JPS5937868Y2 (en) reset circuit
KR870001256Y1 (en) Reset circuit
JP2588270Y2 (en) Digital switch
JPH0534040Y2 (en)
JPS6226111B2 (en)
JPH07182070A (en) Controller
JPH0746298B2 (en) Reset circuit
JPS5897721A (en) Power supply circuit
JPS62138943A (en) Storage device
JPH0315767B2 (en)
JPH0342494Y2 (en)
JPS6135124A (en) Switch circuit
JP2501666Y2 (en) Unit duplication device