JPS625310B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an average time interval measuring circuit that measures the average time interval of start/stop input signals using a digital counter.

FIG. 1 is an example of a conventional average time interval measuring circuit. On the reference clock side, the output of the reference oscillator 1 is connected to one input terminal of the gate circuit 2. Start signal input terminal b and stop signal input terminal c
A gate control signal d is generated by a gate control circuit 3 consisting of a flip-flop having a gate control circuit 3, which is applied to the other input terminal of the gate circuit 2. The output pulse e of the gate circuit 2 is sent to a counter 4 and counted. The frequency of the gate control signal d is divided by 1/10 ⁽ⁿ frequency divider) 5 (n is a positive integer), and the output signal is used as the monostable multivibrator 6.
is driven, the counting of the counter 4 is stopped by the output of the monostable multivibrator 6, and the count content of the counter 4 that has stopped counting is divided by the above number of times by the internal attached circuit, and a start signal is generated. After taking out the measurement data of the average time interval of the stop signal and storing and displaying it in the attached storage and display means, the counting contents are reset by the monostable multivibrator 7 to return to the initial state and the measurement is completed. The counter 4, its auxiliary circuit, and display means can be realized using the averaging processing technique using the averaging means and count display means described in, for example, US Pat. No. 3,631,34.

As for the measurement, one time interval measurement is performed using a start signal b and a stop signal c, and an average measurement is performed 10 ⁿ times. At this time, a quantization error of ±1 count occurs in one time interval measurement, so 10 ⁿ
A quantization error of up to ±10 ⁿ counts is added to each measurement, and the measurement resolution does not improve even if average time interval measurements are performed.

In particular, when the reference clock a and the start/stop signals b, c are synchronized, the quantization error is maximum, so a configuration in which the reference clock a and the start/stop signals b, c are asynchronous has been conventionally used. Ta. Figure 3 shows an example of this (US
Pat.No.3938042), 8 is a noise source using a Zener diode, and its output randomly changes the phase of the output of the reference oscillator 9.
The frequency of the output from the phase modulation circuit 10 is multiplied by several tens of times by a frequency multiplier 11 to create an appropriate reference clock a.
I am getting . As a result, the reference clock a is output asynchronously with the start/stop signal, and the quantization error becomes a statistically very small value, but this is only a statistical point of view and cannot be guaranteed. It has the disadvantage of not having

The present invention provides an average time interval measuring circuit that significantly increases resolution by significantly reducing quantization errors.

In the present invention, the times T ₁ and T ₂ before and after the reference clock period T ₀ of the start/stop signal, that is, the time T ₁ from the end of the gate output waveform to the stop pulse, and the time from the start pulse to the beginning of the gate output waveform ( T ₂ ) is always equal to the period T ₀ of the reference clock (T ₁ + T ₂ = T ₀ ), even if the quantization errors of multiple consecutive time interval measurements are added, the result is ±1 count. It focuses on the fact that

The present invention will be explained in detail below.

FIG. 4 shows an example of a phase holding oscillator circuit which is a part of the present invention, 12 is a holding signal input terminal, 13 is a switch circuit, 14 is a constant current source, 15 is a capacitor, 16 is a Schmitt trigger inverter circuit,
17 is an OR gate, 18 is a switch circuit, and 19 is a constant current source which has a polarity opposite to that of the constant current source 14 and has a current value twice as large in absolute value. 2
0 is the output terminal of this oscillation circuit.

The operation of this circuit is that in the initial state, if the hold signal input from the input terminal 12 is OFF (“L”), the switch circuit 13 is turned ON, and the constant current source 14 is turned ON.
The capacitor 15 is charged by this. Next, when the amount of charge in the capacitor 15 increases and the input of the Schmitt-triggered inverter circuit 16 exceeds the threshold, the output of the inverter circuit 16 becomes "L" and the input of the OR gate 17 becomes "L" and "L". ”, the output also becomes “L”, and the switch circuit 18 is turned on. As a result, the constant current source 19 connected to the capacitor 15 has the opposite polarity to the constant current source 14 and has twice the current value in absolute value, so that the capacitor 15 is discharged. Next, the amount of charge in the capacitor 15 decreases,
When the input of the Schmitt-triggered inverter circuit 16 becomes lower than the threshold value, the output of the inverter circuit 16 is inverted and becomes "H". As a result, the output of the OR gate 17 becomes "H" and the switch circuit 1
8 is turned off, and the capacitor 15 returns to its charged state. In this way, an oscillation waveform can be seen at the output 20 of this circuit, and here the holding signal input terminal 12
When a hold signal (“H”) is applied to the switch circuit 13, the switch circuit 13 is turned OFF, and the output of the OR gate 17 is also “H”, so the switch circuit 18 is also turned OFF.
becomes. Thereafter, the amount of charge accumulated in the capacitor 15 is held until the holding signal becomes "L", and oscillation is stopped. Next, when the holding signal becomes "L", oscillation is restarted based on the amount of charge accumulated in the capacitor 15, so that the oscillation phases immediately before stopping oscillation and when oscillation is restarted are apparently continuous.

FIG. 5 shows an embodiment of the present invention, in which the same reference numerals as in FIG. 1 or 4 indicate corresponding parts, and 21
2 is a NOR gate, 22 is a phase holding oscillator capable of holding the phase as shown in FIG. 4, and 23 is a pulsing circuit including functions such as waveform shaping, differentiation, and rectification.

The operation of this circuit will be explained with reference to the waveform diagram in FIG. When a start signal is input in the initial state, the output d of the gate control circuit 3 made up of FF becomes "H", the output of the NOR gate 21 becomes "L", and the phase holding oscillator 22 starts oscillating. The output of the oscillator 22 is pulsed by a pulse generator 23 and then passed through a gate circuit 2 and counted by a counter 4. Next, when a stop signal is input, the output d of the gate control circuit 3 becomes "L", the gate circuit 2 closes, and the output of the gate 21 becomes "H", and a holding signal is applied to the oscillator 22, stopping oscillation. do. Next, when the start signal b is input, the output d of the gate control circuit 3 becomes "H", the oscillator 22 restarts oscillation, and the gate output signal e is counted by the counter 4. Similarly, 10 ⁿ
When counting is performed, the monostable multivibrator 6 is driven by the output signal of the 1/10 ⁿ frequency divider 5, and the contents of the counter 4 are averaged by an internal attached circuit as in the conventional example. After storing and displaying on the storage and display means attached to the unit, the monostable multivibrator 7 resets the counter 4 and the frequency divider to return to the initial state. Since the oscillator 22 has a structure as shown in FIG. 4, a time interval measuring circuit is constructed in which the phase of the oscillation appears to be continuous even if the oscillation is intermittent.

As explained above, in the present invention, m
(m is a positive integer and m < 10 ⁿ ) The phase of oscillation at the end of the time interval measurement and the start of the m+1 time interval measurement is the same, and the phase of the output waveform appears to be continuous. Therefore, the above T ₀ , T ₁ , T ₂
The relationship is always T ₀ = T ₁ + T ₂ . Therefore, the quantization error when 10 ⁿ counting results are added is ±1.
It is only a count, and has the advantage that the resolution of average time interval measurement is higher than conventional methods.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional average time interval measuring circuit, Fig. 2 is a waveform diagram of each part of Fig. 1, and Fig. 3 is a block diagram showing an example of a conventional average time interval measuring circuit.
FIG. 4 is a block diagram showing an example of a conventional quantization error reduction circuit for average time interval measurement; FIG.
FIG. 5 is a block diagram showing one embodiment of the circuit of the present invention, and FIG. 6 is a waveform diagram of each part of FIG. 1... Reference oscillator, 2... Gate circuit, 3...
Gate control circuit, 4... Counter, 5... 1/10 ⁿ
Frequency divider, 6, 7...monostable multivibrator,
8... Zener diode, 9... Reference oscillator,
10... Phase modulation circuit, 11... Frequency multiplier,
12... Holding signal input terminal, 13... Switch circuit, 14... Constant current source, 15... Capacitor, 1
6...Inverter circuit, 17...OR circuit, 18
...Switch circuit, 19... Constant current source, 20...
Output terminal, 21...NOR gate, 22...phase holding oscillator, 23...pulsing circuit.

Claims (1)

[Claims] 1. The holding signal applied to the input terminal of the holding signal stops the generation of pulses of a predetermined period, and when the holding signal disappears, the pulse of the predetermined period is generated again from the oscillation phase at the time of stopping. a phase-holding pulse oscillator for starting a phase-holding pulse oscillator, having an input terminal for a start signal and an input terminal for a stop signal, and applying a gate control signal starting from the start signal and ending at the stop signal to the input terminal for the holding signal as the holding signal; a gate control circuit for counting the pulses of the predetermined period obtained from the phase holding pulse oscillator during the connection time of the gate control signal; a counter control circuit that stops the counting of the counter when the count is reached; and a counter control circuit that calculates the count value of the counter that stopped counting according to the number of measurements to calculate the average of the start signal and the stop signal. and a counter-attached circuit for measuring time intervals. 2. A capacitor, a first constant current source, a second constant current source having an output current value with a large absolute value and a polarity opposite to that of the current of the first constant current source, and inputting the terminal voltage of the capacitor. a Schmitt trigger circuit comprising: an input terminal for a hold signal; a first switch for connecting the output of the first constant current source to the capacitor when the hold signal is not applied to the input terminal; a second switch for connecting the second constant current source to the capacitor when the holding signal is not applied to the terminal or when there is no operational output of the Schmitt trigger circuit; 2. The average time interval measuring circuit according to claim 1, wherein said phase-holding pulse oscillator is constituted by a pulsing circuit for converting an oscillation output into pulses and taking out the pulses.