JPS6252975B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of transmitting a digital signal in which one word has a plurality of bits and each word has data bits and other control bits, and it is possible to substantially reduce the number of control bits other than the above data. This will be expanded to.

For example, in the case of a PCM signal of an audio signal such as music as a digital signal of multiple bits per word, one word of the audio signal is
Along with the sampling data, data for control etc. is arranged.

To briefly explain how to convert audio signals such as music into PCM, an analog signal such as an audio signal, which is continuous in time and amplitude, is extracted using sampling pulses of a fixed period and so-called sampling is performed. By converting the amplitude of the quantized signal into discrete amplitudes and performing so-called quantization, and then expressing and encoding the quantized amplitude values using, for example, a binary code,
Use PCM (Pulse Code Modulation) signal. The above sampling pulse is, for example, 44kHz, 50k
Hz, etc., and one word of the digital signal is constructed for each sampling data. In addition to the sampling data bits mentioned above, one word also includes control bits, user bits, etc. (hereinafter referred to as control bits). This converts the above digital signal into
This is because when transmitting between multiple devices such as PCM recording/playback machines, electronic editing machines, and special effect generators such as digital reverberators, it is necessary to include information to automatically control each device in the signal. be. In these control bits, control information such as dubbing prohibition information and emphasis designation information, and user information for the user to control the equipment as necessary are written.

One word of such a digital signal is, for example, 32 bits, 20 bits are allocated for sampling data, and 12 bits are allocated for control, but when control information and user information increase, the number of control bits mentioned above becomes insufficient. There are things to do. Therefore, increasing the number of bits in one word increases the bit clock frequency, so
This is undesirable because it requires high-speed circuit response and makes it difficult to synchronize the clocks.

The present invention was made to eliminate these conventional drawbacks, and even if the amount of control information and user information increases, this information can be written without increasing the number of control bits in one word. It is an object of the present invention to provide a digital signal transmission method that enables effective transmission.

That is, according to the digital signal transmission method according to the present invention, each word including a plurality of information bits is provided with at least one control bit and a flag bit, and blocks are configured for each predetermined number of words. The signal form of the flag bit of the word located at the end of the block is different from the flag bit of the word located elsewhere, and significant information consisting of a plurality of control bits included in the plurality of words of each block is transmitted. It is characterized by

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As a preferred embodiment of the present invention, a method for serially transmitting a digital signal obtained by converting an audio signal such as music into PCM will be described below with reference to the drawings. When converting this audio signal into PCM, it is sampled at a sampling frequency of 50.1 kHz, encoded with 20 bits, and 12 bits are added as control bits for control and user use, resulting in a digital signal of 32 bits per word. .

First, FIG. 1 is a schematic diagram showing an example of mapping when a plurality of words are made into blocks.
One block consists of 32-bit data per 256 words. In FIG. 1, the numbers arranged on the horizontal axis indicate the bit numbers of each word, and the numbers on the vertical axis indicate the word numbers. Furthermore, “1” and “0” at the 29th bit indicate data values. Here, from the first bit (MSB) of the 32 bits in one word,
The 20th bit up to the 20th bit is used for the data obtained by sampling the audio signal and converting it into PCM, and the remaining 21st and subsequent bits are used as control bits, but the 29th bit is used to display the block unit. The 30th, 31st, and 32nd bits are used as block flag bits, and the 30th, 31st, and 32nd bits are used as word sync signals (word sync signals) in the data as described later.
Sync.in Data, hereinafter referred to as WSD. ). Therefore, the control bits (information for the user are also written) are from the 21st bit to the 28th bit.
The first 8 bits are 1 block.
Since 8 bits can be used for each of 256 words, as many as 2048 bits can be used as the control bits. Furthermore, only the block flag bit of the word in which control information is written is set to "1" and placed at the forefront position (first word position) of one block, and the remaining words from the second to the 256th word are controlled. The block flag bits are each set to "0" by writing information on the user side into the bits. If it is desired to increase the control information, the block flag bit of the second word is also set to "1", and the control information is also written to the control bit of this word.
Furthermore, control information may be written in the third, fourth, etc. words in the same manner as above. By reading this 29th bit, the constituent unit and position of the block can be determined, and the information of the control bits within one block can be read accurately.

As described above, by forming a plurality of words into blocks and writing control information etc. in units of blocks, the number of control bits can be greatly increased without increasing the number of bits in one word. In addition, like this 256
The control bit reading speed (or transmission speed) when one word is one block is 1
This is 256 times the word reading speed, and when the sampling frequency above is approximately 50kHz, it is approximately 5msec.
becomes. Therefore, it is sufficiently fast as control information and does not cause any inconvenience in use.

Next, the word sync signal inserted into each word will be explained.

1A to 1D are schematic diagrams for explaining the format of one word of a digital signal, where A is a word sync signal with a duty of 50%, B is a 32-bit data, and C is a diagram of the embodiment. The format of one word of the digital signal is shown, and D and E show examples of specific digital signals of C, respectively.
The numbers in FIG. 2 indicate bit numbers.

In FIG. 2, the period Tws of the word sync signal A is equal to the sampling period of the PCM audio signal, and is approximately 20 μsec when the sampling frequency is 50.1 kHz. The unit time T of data bits is the word sync period Tws divided into 32 equal parts. Of these 32 bits in one word, 20 bits from the first bit MSB are used for the sampling data, and the remaining 32 bits are used for the sampling data. from 21 of
The 8 bits up to the 28th bit are control bits, the 29th bit is a block flag bit, and
The 30th, 31st, and 32nd bits are used as a word sync signal (WSD) in the data, and this WSD is a signal in a format different from that of the data. For example, as shown in Figure 2C, MSB
The 29th bit (29SB) is an NRZ (Non Return to Zero) signal with a unit time of T, and the next 3 bits are divided into two to create a signal with a unit time of 1.5T.
In the NRZ signal, inverted (negative) data and non-inverted (affirmed) data of the 29th bit data are sequentially arranged to form the WSD signal. Therefore,
When the 29th bit is "0", the WSD signal becomes "1" and then "0" as shown in Figure 2D, and when the 29th bit is "1", the WSD signal is as shown in Figure 2E.
The WSD signal is in the order of "0" and "1" as shown in FIG.

Such digital signal C is serially transmitted via one transmission line to a receiving side device having a receiving circuit section (or input circuit section) as shown in FIG. This receiving circuit section extracts the word sync signal and reads each data within one word based on the extracted word sync signal.

That is, the input terminal 1 in FIG. 3 has the above-mentioned
A digital signal (see Figure 2C) with WSD is being sent. This input digital signal is sent to a word sync extracting circuit 2, which outputs a word sync signal from an output terminal 3, a data bit clock signal from an output terminal 4, and a serial signal from an output terminal 5. Data signals are respectively taken out. The serial data signal from the output terminal 5 of the word sync extraction circuit 2 is sent to a serial-to-parallel conversion type shift register 6, and is sent to a parallel flip-flop 7 as a parallel data signal for each word. A bit clock signal from the output terminal 4 of the word sync extraction circuit 2 is sent to the shift register 6 and flip-flop 7. The circuitry up to this flip-flop 7 is operated by the word sync signal of the input digital signal and the corresponding clock signal, but after the data is latched into the flip-flop 7, the internal clock signal and clock signal on the receiving side are operated. Word sync signal (input terminals 11 and 12, respectively)
supplied to ), such as a parallel-to-serial conversion type shift register 8,
The signal can be sent to the parallel flip-flop 9 and subjected to convenient signal processing on the receiving side.
The shift register 8 synchronizes the word-by-word parallel data from the flip-flop 7 with the internal clock of the receiving side, converts it into serial data in a format convenient for signal processing in the receiving side equipment, and sends it out from the output terminal 13. Similarly, the flip-flop 9 converts the digital data into digital data suitable for internal processing in the receiving device and sends it out from the output terminal 14. Only one of the shift register 8 and flip-flop 9 may be used. Furthermore, the word sync signal from the output terminal 3 of the word sync extraction circuit 2 is supplied to the clock enable (clock inhibit) terminal of the flip-flop 7, so as to maintain the normal relationship between the data of each word and the bit order. act. In addition, the word sync extraction circuit 2 has n times the bit clock (n
is an integer greater than or equal to 5) is supplied via terminal 15.

Note that if the distance between devices is short and the length of the signal transmission line is short, the parallel type flip-flop 7 may be omitted and the parallel signal from the shift register 6 may be transferred to the shift register 8 or the flip-flop 9.
In this case, the shift register 6 may be driven by the receiving side clock signal from the clock input terminal 11.

Next, a specific example of the configuration of the word sync extraction circuit 2 will be explained. In FIG. 4, input terminal 1 is supplied with a digital data signal as shown in FIG. 5A. In the digital data signal shown in FIG. 5A, the unit time T of the data bit is between time t _{1 and} t ₂ , and is inverted at time t ₂ and _{t 3 ,} respectively. The distance is 1.5T. At this time, the data of the 29th bit in one word is located between times t ₁ and t ₂ , and between times t ₂ and t ₃ and at time t _3.
Until time t ₄ , which is 1.5T after
has been inserted. Therefore, the next word starts from time t ₄ and after, and every unit time T starts from time t ₄ .
MSB, 2SB, ... data is allocated.

Next, a high-rate clock with a period of 1/n (n is an integer of 5 or more) of the unit time T is
Clock) signal is applied to the high speed clock input terminal 15. In this embodiment, as shown in FIG. 5B, a high-speed clock signal in which n is 6 (ie, T/6 period) is used. Of this high-speed clock signal B, the time at which the first clock pulse after the above-mentioned time _t1 occurs is defined as _t1 , and the time at which each clock pulse occurs up to the above-mentioned time _t2 is successively
Let t ₁₂ , t ₁₃ , .... There are normally six clock pulses, but if the interval △t between time t ₁ and t ₁₁ is 0
If it is close to , the number may be 5 or 7 depending on the error between the input data and the receiving clock. Furthermore, the clock pulse generation times from time t ₂ to time t ₃ are sequentially t ₂₁ , t ₂₂ , . . . , and the same applies from time t ₃ onwards. For the same reason as above, the number of clock pulses between times t ₂ and t ₃ is normally nine, taking into account an error of ±1.

A digital data signal A (see FIG. 5; the same applies hereinafter) supplied to the input terminal 1 in FIG. 4 is sent to a D-type flip-flop 21 driven by the high speed clock signal B. As is well known, this D-type flip-flop 21 sends a change in the state of the input terminal 1 to the Q output terminal in response to a clock signal from the clock terminal 15, and outputs a change in the state of the input terminal 1 to the Q output terminal in response to a clock signal from the clock terminal 15. The digital data signal A having a phase difference Δt becomes a digital data signal C synchronized with the high-speed clock signal B and having a phase difference of 0 (however, there is a slight delay time required for the circuit response), and the digital data signal C is synchronized with the high-speed clock signal B. Appears on the output terminal. This digital data signal C is sent to the next D-type flip-flop 22, and from the Q output terminal of this D-type flip-flop 22, a digital data signal D shifted by one cycle T/6 of the high-speed clock signal B is obtained. It will be done. The Q outputs of these two D-type flip-flops 21 and 22 are connected to an exclusive OR (hereinafter referred to as Ex.OR) circuit 23.
A signal E of the transient (whether "1" and "0" are inverted or not) of the digital data signal is obtained. Here, input digital data signal A
is always reversed at times t ₂ and t ₃ ,
The signal E has transient pulses P ₁ and P ₂ between times t ₂₁ and t ₂₂ and between t ₃₁ and t ₃₂ , respectively. Normally, nine high-speed clock pulses are included between these transient pulses P ₁ and P ₂ (between times t ₂₂ and tt ₂₃ ), and considering an error of ±1, 8, 9,
The WSD signal can be determined by counting and detecting 10 high-speed clock pulses.

That is, the above-mentioned WSD determination is performed by the counter 24 and logic matrix circuit 25 shown in FIG. This counter 24 is a preset type 16
It is a forward counter, and with a preset value of 5, performs a preset operation in response to the transient pulse _P1 of the signal E, and sequentially counts the high speed clock pulses as shown in FIG. 5G.
The numbers in FIG. 5G are the count values of the counter 24. Outputs of counter 24 Q _A , Q _B , Q _C , Q _D
correspond to decimal numbers 1, 2, 4, and 8, respectively, and in the logic matrix circuit 25, the NAND circuit 2
6, take NAND of Q _A and Q _B , and combine the output of this NAND circuit 26 with Q _C , Q _B , and the above signal E.
The NAND is processed by the next NAND circuit 27 to obtain an output signal H. Therefore, when the count value of the counter 24 is 12, 13, 1, _A 〓 _B , Q _C , Q _D
all become "H", and if a transient pulse _P2 occurs in the signal E during this time, the output signal H becomes
WSD detection pulse _P3 is generated. This output signal H
is sent via the OR circuit 30 to the preset load terminal of the next preset type hexadecimal counter 31.

In order to prevent the counter 24 from being preset by the transient pulse _P2 of the signal E, the signal E is sent to the load terminal for preset control of the counter 24 via the NAND circuit 28, and this NAND circuit is The above-mentioned WSD detection pulse _P3 is sent to 28, and the passage of the above-mentioned transient pulse _P2 is blocked. Therefore, NAND circuit 2
The output signal F from 8 includes only pulse ₁ , which is the inversion of the above transient pulse _P1 .

Furthermore, the counter 24 outputs the carry pulse generated when counting 15 to the inverter 2.
9 to the clock input inhibition control terminal (clock enable terminal), and the count value is held at 15 until the next transient pulse performs the preset operation.

Next, the counter 31 takes out a bit clock signal for reading the data of each bit in one word, and after inverting the carry pulse with an inverter 32, it is sent to a load terminal for preset control via the OR circuit 30. By sending this signal, a decimal value of 10 is preset, and the counter is used as a repeat counter that repeats every six high-speed clock pulses (the period is the above-mentioned unit time T). Further, as an output, Q _C out of Q _A , Q _B , Q _C , and Q _D similar to the above is taken out via an inverter 33 .

That is, when the WSD detection pulse _P3 of the output signal H from the logic matrix circuit 25 is sent to the load terminal of the counter 31 via the OR circuit 30, the preset value 10 is loaded, and the preset value 10 is loaded as shown in FIG. The pulses of the high-speed clock signal B are counted sequentially from 10 onwards. This number in Figure 5 I is the counter 31.
is the count value of When the count value changes from 11 to 12, the output J from the inverter 33 falls, and when the count value reaches 15, a carry occurs, and an inverted carry pulse P _C is generated in the output signal K from the inverter 32. This pulse P is sent to the load terminal of the counter 31 via the OR circuit 30, and then presets 10. Therefore,
After counting up to 15, counting starts from 10, and when the count reaches 10 from 15, the output J from the inverter 33 rises. Thereafter, the operation is repeated in a similar manner at a cycle of 6 counts from 10 to 15 (the unit time T of the data bits), and the time when the output J rises becomes the center position of each data of the digital data signal D. That is, if each data of the digital data signal D is read at the rising edge of the bit clock output J, erroneous reading will be minimized. This is for example a digital data signal D
The D-type flip-flop 34 is driven by the bit clock output J, and the Q output is sent to the data output terminal 5.

Next, JK type flip-flop 36 and D
A type flip-flop 37 is used to obtain a word sync signal synchronized with the bit clock output J. This converts the above WSD detection signal H to J-
The output (see FIG. 5L) is input to the K-type flip-flop 36, and the output is input to the D-type flip-flop 37.
send to If the bit clock output J is used as the clock for this D-type flip-flop 37, the Q output becomes a word sync signal synchronized with the bit clock output J as shown in FIG.
sent to. Note that the output of the D-type flip-flop 37 is the S output of the JK-type flip-flop 36.

According to the digital signal transmission method of this embodiment, since the word sync signal is built into the digital signal, there is no need for a signal transmission line dedicated to the clock, and the synchronization deviation of the clock signal due to transmission can be prevented. There is no need to consider it. In this case, on the receiving side, each data position (from MSB to LSB) within one word can be confirmed by extracting the word sync signal, so there is no misreading of data. Therefore, it becomes possible to accurately extract the word sync signal inserted into one word. Also, since it is serial transmission,
Unlike parallel transmission, there is no need to use a large number of signal transmission lines, simplifying wiring work and improving reliability.

As is clear from the above description, according to the signal transmission method according to the present invention, a block flag bit is provided for each word of a digital signal consisting of multiple bits per word (for example, 32 bits), and this block flag bit is It is characterized by serially transmitting a fixed number of words (for example, 256 words) as one block.

Therefore, the number of control bits can be greatly increased without increasing the number of bits in one word, the area that can be used freely by the user is expanded, and the amount of control information can also be increased.

It should be noted that the present invention is not limited to the above-mentioned embodiments; for example, the position (bit number) of the block flag bit, the number of bits in one word, and the number of words in one block are arbitrary. Also, above
Of course, the present invention can also be applied to digital signals that do not use WSD.

[Brief explanation of the drawing]

The figures are all for explaining the embodiments of the present invention, and FIG. 1 is a schematic diagram showing mapping of word blocks, and FIGS. 2 A to E are schematic diagrams showing the format of one word of a digital signal. 3 is a block circuit diagram showing the input circuit section on the receiving side, FIG. 4 is a block circuit diagram showing a specific example of the word sync extraction circuit 2 in FIG. 3, and FIGS. 5 A to M
are time charts showing operating waveforms at points A to M in FIG. 4, respectively. 1...Digital signal input terminal, 2...Word sync extraction circuit, 3...Word sync output terminal, 4...Bit clock output terminal, 5...Data output terminal.

Claims (1)

[Claims] 1. Each word containing a plurality of information bits is provided with at least one control bit and a flag bit, and a block is formed for each predetermined number of words. A digital signal transmission method characterized in that the signal form of the located word is different from the flag bit, and significant information consisting of a plurality of control bits included in the plurality of words of each block is transmitted.