JPS6251430B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic analyzer that measures logic timing relationships of input logic signals.

Digital techniques have recently become popular in the field of measuring digital and analog signals. Digital measuring instruments, such as logic analyzers, are suitable for adjusting and troubleshooting digital devices, such as computers, desk calculators, computer terminals, and digital control devices. Such a logic analyzer is suitable, for example, for measuring the logic level (high or low) and timing relationship of a plurality of logic signals at various circuit points or input/output terminals in a digital device. The reason for this is that the logic analyzer has a digital storage circuit and a preset counter, and can store and measure logic signals before or after the trigger signal, making it possible to analyze, for example, the state of digital equipment before and after an abnormality occurs. There are two types of logic analyzers, one is a logic timing analyzer and the other is a logic state analyzer.

A logic timing analyzer displays a timing diagram (waveform diagram) of an input logic signal on a display means such as a cathode ray tube.
This is suitable for hardware engineers. The logic state analyzer displays a state diagram of an input logic signal on a display means such as a cathode ray tube as a series of numbers "0" and "1", and is suitable for software engineers. The logic state analyzer is suitable for analyzing the bit states of words, ie, logical data, relative to clock signals.

In a logic timing analyzer, a vertical position control circuit selects a selected one of the multiple channels of logic signals displayed on the cathode ray tube in order to compare the timing relationships between the logic signals of the selected channel and the logic signals of other channels. It has been proposed to control the vertical position of the logic signals of the channels. However, such logic timing analyzers have not been able to simultaneously compare the timing relationships of many logic signals, such as 4, 8, or 16 channels. Other logic timing analyzers include a counter and a brightness modulation circuit that modulates the brightness of the input logic signal, and compare the timing of each signal using a vertical cursor formed by brightness modulating the same point in each channel. However, the bit relationship between the trigger point and the vertical cursor was not displayed. Additionally, conventional logic state analyzers have been unable to display timing relationships of input logic signals.

Accordingly, one of the objects of the present invention is to provide an improved logic analyzer that does not have the drawbacks of the prior art mentioned above.

Another object of the invention is to provide an improved logic analyzer that displays the bit relationship between a trigger point and a vertical cursor.

Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings. FIG. 1 is a block diagram of a preferred embodiment of the present invention. The input logic signals of channels CH-0 to CH-3 are applied to comparators 18 to 24 via input terminals 10 to 16, respectively. Comparator 18~
24 receives a reference voltage as a threshold level from the reference voltage sources 26 to 32, and applies the output to the memory circuit 34 and word identification circuit 37. The memory circuit 34 may be a random access memory element (RAM), and the word identification circuit 37 may be comprised of a phase inverter, a selection switch, and an AND gate. Four parallel outputs from the storage circuit 34 corresponding to the logic signals of channels CH-0 to CH-3 are sent to a multiplexer 36 to convert the parallel signals into serial signals.
is applied to The output of the multiplexer 36 is sent to the cathode ray tube 3 via a buffer amplifier 40 and a mixer 42.
8, that is, applied to the vertical deflection plate of the display means.

To generate a delayed word trigger signal,
The output of the word identification circuit 37 is sent to the digital delay circuit 4.
The delay bit number information from the digital delay circuit 44 is applied to the readout circuit 45. Trigger signal 48 is a delayed word trigger signal from digital delay circuit 44, channel CH-0.
or an external trigger signal applied to external trigger input terminal 50 according to the selection of switch 46. The output trigger signal of the trigger circuit 48 is applied to a first control circuit 52 including a preset counter and an address counter.
2 is generated by the clock signal generator 54 and sent to the frequency divider 5.
6 or an external clock signal applied to external clock input terminal 58 according to the selection of switch 60. switch 6
The 0 fixed contact is connected to a digital delay circuit 44 .

The sweep generator 62 receives a sweep command signal from the first control circuit 52 and generates a buffer amplifier 64 and a mixer 6.
A gradient wave signal is applied to the horizontal deflection plate of the cathode ray tube 38 via 6. The blanking signal from the sweep generator 62 is sent to the cathode ray tube 38 via a Z-axis amplifier 63.
applied to the grid. The first control circuit 52 is
A write/read command control signal and a write/read clock signal are applied to storage circuit 34, and a read clock signal is applied to multiplexer 36.

The addition/subtraction counter 68 receives an output pulse from the second control circuit 70 at its addition or subtraction terminal;
Preset counter 72 receives the output of addition/subtraction counter 68 at its preset terminal and receives the read clock signal of first control circuit 52 at its clock terminal. Shift register 74 is buffer amplifier 40
The detection data of channel CH-0 is sent to the flip-flop circuit 76, the detection data of channel CH-1 is sent to the flip-flop circuit 78, and the detection data of channel CH-2 is sent to the flip-flop circuit 78. The detected data is applied to a flip-flop circuit 80, and the detected data of channel CH-3 is applied to a flip-flop circuit 82. The outputs of flip-flop circuits 76-82 are applied to readout circuit 84, and the output of preset counter 72 is applied to Z-axis amplifier 63.

The cursor trigger interval counter 86 as a detection means receives the output of the preset counter 72 and the trigger information of the first control circuit 52, and
Trigger information is also applied to Z-axis amplifier 63. The output of the counter 86 corresponds to the bit difference information between the trigger point and the output of the counter 72, and the output of the readout circuit 8
8. Character generator 90 is readout circuit 4
5, 84 and 88 readout information and sweep generator 6
2 and the X, Y and Z signals from character generator 90 are sent to mixers 66 and 42, respectively.
and is applied to the Z-axis amplifier 63.

When the storage mode is selected, the input digital signal is stored in the storage circuit 34. The write speed, that is, the sampling speed is determined by the frequency of the write clock signal, and the write frequency signal is determined by the first control circuit 5.
It is controlled by a clock signal applied to 2. The word identification circuit 37 selects channels CH-0 to CH-3.
generates an output when the logic state of the input digital signal matches the predetermined logic state. When the event delay mode is selected, the digital delay circuit 44, including the preset counter, is connected to the word identification circuit 37.
and generates an output when a predetermined number determined by the settings of this counter is counted. Further, when the clock delay mode is selected, the digital delay circuit 44 counts the clock signal when the output of the word identification circuit 37 occurs, and similarly, when the scheduled number is counted, the circuit 44 counts the clock signal.
produces output. The expected number of delay bits of digital delay circuit 44 is displayed on cathode ray tube 38 by readout circuit 45 and character generator 90. Trigger circuit 48 receives the signal selected by switch 46 and applies a trigger signal to a preset counter within first control circuit 52. The preset counter can be set to a trigger mode such as "pre-trigger".
Used to select either ``center trigger'' or ``post trigger'', storage circuit 34 ceases storage operations when the preset counter produces an output.

When the read mode is selected, storage circuit 34 receives a read command control signal and a read clock signal from first control circuit 52. The parallel logic signals are sent to multiplexer 3 to be converted to serial logic signals.
6. Sweep generator 62 generates a ramp signal in synchronization with the read clock signal so that the serial logic signal from multiplexer 36 is displayed on cathode ray tube 38. The vertical position of the serial logic signal is automatically controlled, so the channel CH-0~CH
It should be noted that the -3 logic signals are displayed separately in the vertical direction of the tube surface of the cathode ray tube 38.

The second control circuit 70 includes an addition/subtraction counter 68
Apply a predetermined number of pulses to the addition or subtraction terminals. The output of counter 68 presets preset counter 72 which receives the read clock signal. Once counter 72 has counted the read clock signal to the preset state, counter 72 applies an output to Z-axis amplifier 63 and detection means 74. The Z-axis amplifier 63 brightness-modulates the point of the logic signal selected by the second control circuit 70. The modulated points are used as vertical cursors to measure the time relationship between each channel signal. Soft register 74 detects the state of the brightness modulated logic signal by the output of counter 72, and the detected logic state is stored in flip-flop circuits 76-82 and output to the cathode line by readout circuit 84 and character generator 90. displayed on tube 38. A counter 86 serving as a detection means receives the trigger information and the output of the counter 72, reads out the bit number relationship between the brightness-modulated point of the logic signal and the trigger point, and reads out the bit number relationship between the brightness-modulated point of the logic signal and the trigger point.
Displayed by 0. Z-axis amplifier 63 also receives the trigger information and intensity modulates the logic signal at the trigger point.

The above is an explanation for the case where the input signal is 4 channels, but in this case, first
The CH-0 signal is read out and displayed on the cathode ray tube, the vertical cursor point and the trigger point are intensity-modulated, and the logic state of the cursor point is detected.
Next, the signal of channel CH-1 is read out and processed in the same way, and then the signal of channel CH-2 and
The signal of CH-3 is read out and processed. That is, due to the alternate operation, the brightness modulation points of each channel are aligned in the vertical direction to display the same time for each channel. Note that the information from the readout circuits 45, 84, and 88 can be displayed during the retrace period of the electron beam of the cathode ray tube 38.

FIG. 2 shows the tube surface of the cathode ray tube 38. As shown in FIG. Waveform A
-D are logic signals of channels CH-0 to CH-3, respectively. The brightness-modulated point E indicates the trigger point in the pre-trigger mode, i.e. the point at which the trigger signal is supplied to the first control means 52;
The brightness-modulated point F indicates a vertical cursor controlled by the second control circuit 70. The letter G indicates the bit number relationship between the brightness modulation points E and F. The figure shows that point F leads point E by 208 bits of the read clock pulse. The letter H is F
Logical state of a point, e.g. channel CH-0 to CH-
2 indicates "level 1" and channel CH-3 indicates "level 0". The letters indicate the number of digital delay bits controlled by digital delay circuit 44.

As can be understood from the above description, the logic analyzer of the present invention displays the logic timing relationship by waveforms A to D, and also displays the trigger point E and the vertical cursor F, and shows the relationship between them. , timing analysis is extremely easy. Furthermore, since all information is displayed on the cathode ray tube 38, it is easy to record measurement results with photographs.

Although only the preferred embodiments of the present invention have been described above, it will be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. For example, the input signals may have 8, 16 or 32 channels and the outputs of readout circuits 45, 84 and 88 may be displayed on other display means such as LEDs or liquid crystals. A glitch removal circuit may be provided between the word identification circuit 37 and the digital delay circuit 44, and the storage circuit 34 may be a shift register. The cursor may also use any known technique, such as superimposing a marker signal or displaying a continuous vertical bright line without intensity modulation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a preferred embodiment of the present invention, and FIG. 2 is a diagram showing a display means according to the present invention, where 34 is a storage circuit, 38 is a display means, and 52 and 70 are first and second display means. Control means and 86 indicate detection means.

Claims (1)

[Claims] 1. A first control means that is supplied with a trigger signal and generates a control signal, a storage means that stores an input logic signal in response to the control signal from the first control means, and the logic signal stored in the storage means. display means for displaying the logic signal as a logic waveform, the trigger signal is supplied to the second control means for selecting a desired portion of the logic signal stored in the storage means, and the first control means. further comprising a detection means for detecting the number of bits between the part of the logic signal corresponding to the point in time when the logic signal is selected and the desired part of the logic signal selected by the second control means, and displaying the output of the detection means. A logic analyzer featuring: