JPS62500061A - MOS transistor with Schottky layer electrode - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] MOS transistor with Schottky N electrode area The present invention relates to a semiconductor device, more specifically a MOS (MOS) having a Schottky single-layer electrode region. (metal oxide semiconductor) field effect transistor.

Miyo Dan Tosami Layers composed of certain types of metals and metal-like materials (“Schottky layers”) layers'') form a Schottky barrier at the interface between these and the semiconductor body. These Schottky layers have some important characteristics.

For example, the source or source in a p-channel MOS transistor with low leakage current etc. It is known that it can be used as a drain electrode and/or as a drain electrode. However, this In a Schottky single-layer transistor, this source and/or &N are connected to the drain region and the gate. It is possible to align the edge of the ground electrode with the edge of the ground electrode.

light J1υL cold In one embodiment of the invention, a shot is formed on the main surface of the silicon semiconductor body. Key source and/or bqlt drain electrode layer and covered with insulating material layer A MO5FET device structure is provided having a gate electrode. This source and/or Alternatively, each drain electrode layer extends into a recess within this body. this hollow extends below the insulated gate electrode structure, thereby providing access to the source and/or Alignment between the drain region and the edge of the gate electrode is achieved. schottky electrode Whether it creates a Schottky barrier or a resistive contact will be explained later. In particular, it depends on the conductivity of the semiconductor material being contacted.

Brief description of the drawing FIGS. 1-10 illustrate exemplary p-channel channels in accordance with certain embodiments of the present invention. Cross-sections of this structure at various stages to fabricate parts of the MO8FET structure Show the diagram: FIG. 11 shows an exemplary P-channel MO according to another embodiment of the present invention. 3 shows a cross-sectional view of this structure at one stage in the fabrication of a portion of the FET structure; FIG. 2 shows an n-channel MO8FET structure according to yet another embodiment of the invention. A cross-sectional view of the structure is shown.

Figures 5 to 8 are shown in Figures 1 to 4 and Figures 9 and 10. The left side of the structure is shown in an enlarged view.

Kokuou Elephant Village The workpiece shown in Figure 1 was manufactured by a well-known process, and field surface layer 10, a thick oxide layer known as "field oxide" 11. a thin oxide layer 12 forming a gate dielectric layer and a polysilicon gate electrode layer Contains 13.

Next (FIG. 2), the exposed top and side surfaces of the polysilicon layer 12 are A conventional oxidation step is performed to produce a thin silicon oxide cover layer 14. will be carried out. Typically, this thin oxide layer 14 is about 300 Angstroms thick. As a result of this polysilicon oxidation, the thickness of the original thin oxide layer 12 (FIG. 1) As shown by the oxide layer 121 (FIG. 2), the polysilicon layer 13 somewhat increased except for the lower part (indicated by reference numeral 12 in Figure 2). Add.

Next, the exposed portions of the thin oxide layer 121 and the sidewall portions of the thin oxide layer 14 are h) The upper part is the well-known CHF.

Fluoride ions (F+) in the plasma generated by (Freon 23) Chemically reactive backing, anisotropic processes such as sputtering (reactive ion etching) completely removed by an etching step. What is “anisotropic” etching? Only the surfaces parallel to the top surface of the layer 10 are removed by the etching process. selective in that it is attacked and removed by Ru.

Next, as shown in FIG. 4, the n-type surface layer 10 is exposed at this time. An isotropic etch step of the top layer is performed, typically when the silicon is about 95 oz. ngstrom thickness is removed, and the lower part of the remaining sidewall oxide ff14 is removed. A cavity is formed between the bottom of this sidewall oxide layer and the top surface of the n-type surface layer 10. Here, "isotropic" etching means that the removal rate by etching is means that it is equal in all directions. however.

n-type silicon layer], the sloped walls of the exposed top portions 101 and 102 of 0 Some crystallographic selections as shown by sections 101.1 and 102.1 Optionality exists. This isotropic etching is typically performed using a liquid mixture of hydrofluoric acid and nitric acid. Wet etching with a compound, or usually with argon or other suitable etching. This is accomplished by dry etching using etching gas. This process is an isotropic sidewall acid at approximately 1 mm Hg, a pressure high enough to achieve tucking. The lower part of compound 14 is 95 angstroms accurate to within 10 angstroms. It is carried out only for a partial period to remove only a distance. Next, as shown in Figure 5, - Positively charged argon ions are directed toward the platinum cathode target 3 Platinum layers 32, 33 and 34 are anisotropically deposited on two sides of the structure to be fabricated. It will be done. More specifically, the structure fabricated here uses positively charged argon ions. platinum target where platinum atoms are removed by sputtering due to placed near the Kokura ion is located at platinum target 31. Reached by momentum. This momentum is the negative polarity DC applied to target 3] Through the ion accelerating DC electric field generated by voltage E1 and capacitor C2 of the ion accelerating AC electric field generated by the RF voltage E2 applied to the surface layer 10. given to ions under the influence. Normally, El is approximately 1,000 volts; E2 is approximately 500 volts peak to peak (AC amplitude) at a frequency of approximately 13 MHz. twice). Therefore, compared to Target 31, very few, if any, Less argon (with some momentum) hits this structure. For this reason, plastic China is not removed from layers 32, 33 and 34. This structure is made of deposited plastic. During this anisotropic platinum deposition, a preferable or maintained at about 200'C or lower.

The sputtering process is then repeated, which includes platinum layers 32,33 and and 34 are removed, deposits 35 and 34 are removed in the cavities below the oxides [11 and 14]. 36 (FIG. 6) for redistribution. This is more than the AC voltage E2 When the voltage is increased to a higher voltage, e.g. 1000 volts or more, argon ions are added to the platinum layer. 32.33 and 34 should be removed so that they hit the top surface of the workpiece. Therefore, let's do it. Platinum from these layers as well as some targets 31 is empty It is diffused in all directions, including towards the sinuses. However, once it is deposited inside the cavity, The edges of oxide layers 11 and 14 then inject argon into deposits 35 and 36. These deposits are removed through this sputtering process. Retained. Typically, this structure is also sputtered (compared to platinum). To avoid the formation of platinum silicides (which exhibit strong resistance to removal) The temperature is maintained at about 200°C or lower.

Normally, the presence of Jl: 32, 33 and 34 (Figure 5) indicates that the cavity is completely filled. It is not always necessary to form these layers in advance, although this is preferable. A single sputtering process to fill all the platinum into this cavity without It can also be obtained directly from the target 31.

As shown in FIG. 7, the AC voltage E2 is typically about 500 volts per minute. the platinum layers 41, 42 and 43 during manufacture. It is deposited anisotropically on the -L plane of the structure. Again, the temperature of this structure is 3. The temperature is kept below about 200°C to prevent the formation of chemical compounds. This structure is then suitable for sintering the platinum to produce platinum silicide. In an atmosphere 1 For example, in argon gas mixed with 15 percent oxygen, typical Generally, the heat treatment is performed at a temperature of about 625°C. The platinum in layers 42 and 43 is These cover the silicon with platinum silicide layers 15 and 1G (Figure 8). Become. However, the leftmost portion of layer 42 does not cover silicon and is essentially a plastic layer. Stay Chyna. Second, platinum rather than platinum silicide, e.g. It is removed by wet etching with water, typically at about 80°C, thereby Latina silicide layers 15 and 16 remain.

During the silicide formation process, layer 43(1,6) is expanded into the surrounding silicon. Ru. By appropriate selection of dimensions and processing parameters, the result of this expansion is As.

The right edge of layer 16 (source region) is approximately aligned with the left edge of gate electrode 13. I can do it. If necessary, for the drain region 17 (FIG. 9) of this device. can also obtain similar results. The ability to achieve such alignment is demonstrated by the present invention. This is an important feature of

After the formation of platinum silicide layers 15, 16 and 17, the top surface of the structure being manufactured selected areas have openings to expose the underlying platinum silicide layer 15. It is covered with an insulating layer 22 (FIG. 9), which is well known in the art. Next, as shown in Figure 10, Contours to the gate electrode and the source and drain regions, respectively, are cts 18, 19 and 20 are provided.

As an alternative to the above steps, as shown in FIG. directed the argon ions into the platinum cathode target 31, thereby causing the platinum cathode target 31 to The material is deposited on the workpiece in one step, and at the same time the part that will contact the silicone is plated. It can be converted into latina silicide. In this process, the workpiece is A temperature of about 625° C. is maintained to produce the ionide.

Another method of depositing platinum involves low pressure chemical vapor deposition of platinum followed by platinum deposited to produce platinum silicide in the area above the silicon. This is followed by wet etching, e.g. with aqua regia. Platinum on silicon dioxide (not on platinum silicide) is removed by be done.

FIG. 12 shows an n-channel MO8FET device according to another embodiment of the present invention. A cross section of a vice structure 100 is shown. Here we will discuss platinum silicide sources and and drain electrodes 86 and 87 essentially drain to n+ in the underlying p-type surface MBO. doped silicon regions 81 and 82 and a resistor (rather than a Schottky barrier). Make a contact. Platinum silicide edges of the gate electrode as in the previous structure. Instead of aligning the corresponding edges of the electrodes, each of the gate electrodes 18 in the structure 100 Each edge corresponds to the lower doped silicon region 81 or 82. edge (pn junction).

Structure 100 is fabricated as described above with the following exceptions. In other words, (1) p-ta The depth of the cavity formed in the n-type region 81 in the deep layer 8o is somewhat shallow (for the purpose of matching). and (3) correspondingly less platinum is deposited.

More specifically, during platinum sputtering, n+ regions 81 and 82 are The target 31 (FIG. 7 or FIG. 11) contains hydrogen, which is a donor impurity dopant. It is formed by adding element or antimony (or both). this Therefore, n+ regions 81 and 82 are formed simultaneously during platinum sputtering. (course battering). These n0 regions are therefore filled with impurity dopants. Formed by exclusion from latina into silicon (separation factor). Post-processing temperature is kept well below the temperature at which significant diffusion of impurities occurs within the silicon. Therefore, the thickness of the n-medium regions 81 and 82 is approximately 100 angstroms (or approximately 100 angstroms). (below). Alternatively, at an earlier stage of manufacturing, For example, the gate electrode layer 13 and sidewall acid (t22M (FIG. 4)) are coated with these impurities. A conventional method for importing and diffusing donor impurities using The n-middle regions 81 and 82 can also be formed using conventional techniques.

In either case, pn Junctions 91 and 92 are formed. Preferably, the right end of the pn junction 91 is connected to the gate. substantially aligned with the left edge. This alignment can be achieved, for example, at the initial depth of the cavity (Fig. 4). is about 63 angstroms, and the thickness of the n+ region is about 100 angstroms. obtained by doing. Here, the platinum is 100 angstroms thick. The thickness of the platinum silicide layer 81 after being deposited is approximately 200 angstroms. Become.

As is well known in the art, platinum silicides are compatible with n-type silicon and This is a barrier formed by p-type silicon. The barrier height is 0.85 volts while the barrier height is 0.25 volts. (For example, 1M, P, Lepselter (M, P, Lepselter) and J.M. Andrews, B.S. Edited by B. and S. Chvartz, Electrochemical Society of Japan (Electro Chemical Society), published in 1969, “Resistance to Conduct” Ohmic Contacts to Sem1 conductors J Paper published on pages 159 to 186 of [Resistive Contacts to Silicon (Otusic Contacts to 5i1icon) and see Table 1 on page 173. ). The height of the barrier formed with n-type silicon is thus relatively high; Since this greatly disturbs the mutual conductance of the MOSFET structure, the n middle region 8 1 and 82 are formed within n-channel structure 100. Effective barrier in this way can be tolerated by quantum mechanical tunneling of charge carriers through the barrier. level, the MO8FET transconductance is reduced by the Schottky barrier. This will ensure that there is no major interference.

In this way, P-channel MOSFET structures 20 and 20 are placed on the same silicon body 9. and n-channel MOSFET structure 100, which Using the terminology of 0MO8 technology, 'n-type surface [10 is "n-tab"] Thus, the p-type surface layer 8o becomes the lp-tab 1'.

Alternative to platinum to form metal silicide source and drain electrodes Titanium or zirconium can also be used. In addition, Chita Nium silicide and zirconium silicide are both p-type and n - approximately the same barrier height for both types of silicon, i.e. 0.55 volts; symmetric structures can be used for these silicides. wife P-channel and n-channel with zirconium or titanium silicide electrodes - channel preferably interposed between respective silicide electrodes in the transistor; Highly doped P+ and n+ impurity regions and n-type and P-type surface layers 10 and 80 are provided. Typically, these p and The thickness of both n+ regions is approximately 100 angstroms (or less). It will be done. Impurities per square centimeter within these P+ and n+ impurity regions Doping concentration expressed in atoms (or ions) (i.e. "surface concentration") is made low enough to avoid the latch-up problem from occurring again. Noriyoshi Typical, this is on the order of 1013 or more per square centimeter. 1013 per square centimeter to 1000 ml for tabs with doping levels of - Rui is considered to be of lower order. On the one hand, the volume concentration is the resulting The transconductance of the transistor structure is not significantly disturbed. It is made high enough to reduce the effective barrier (by tunneling effect). typical is on the order of 5 x 10" per cubic centimeter. Separately, the effective bar In order to lower the rear, the surface concentration of impurities in the n+ and p+ impurity regions is increased somewhat, Therefore, increasing this thickness allows operation within the current limits of typical power supplies. It is also possible to avoid latch-up problems.

Other modifications are also possible. For example, to form a metal silicide electrode, Other transition metals that produce metal silicides suitable for Schottky barriers with recon, For example, cobalt, hafnium or tantalum can also be used. Ma Alternatives to producing platinum or other metal silicides by sputtering This metal is first deposited over the entire top surface of the structure to be fabricated and then 400°C to 650°C for about 2 to 6 minutes. Pike) treatment to convert the gold into ρt silicide, and then this Metals remaining on the oxide can also be removed by etching with hot aqua regia. can.

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Claims (8)

[Claims] 1. Schottky layer source electrode (16) formed on the semiconductor body 10; a gate electrode layer (13) separated from the semiconductor body by an insulating layer (12); and a MOS transistor having a sidewall insulating layer (14) covering the sidewall of the gate electrode. In structure, A source electrode (16) of the transistor is hollowed out under the sidewall insulating layer and connected to the gate electrode. extending into and filling a cavity within the semiconductor body terminating in a predetermined relationship with an edge of a layer; A transistor characterized by: 2. A transistor according to claim 1, wherein the semiconductor body is made of silicon. , the gate insulating layer is silicon dioxide, and the gate electrode layer is polycrystalline silicon. and the source electrode layer is a metal silicide. Njista. 3. The transistor according to claim 2, wherein the sidewall insulating layer is made of silicon dioxide. A transistor characterized by being a reconductor. 4. The circuit according to claim 1, wherein the source electrode is below the sidewall insulating layer. extending to a position substantially aligned with the overlying edge of the gate electrode layer. Featured circuit. 5. Polysilicon gate with a pair of facing sidewalls each coated with an oxide layer forming an electrode, the gate electrode being a main body of a single crystal silicon semiconductor body; MOSFET within the semiconductor body separated from the surface by a silicon dioxide layer In a method of manufacturing a transistor; a major surface of the silicon body adjacent the now exposed edge of the sidewall oxide layer; The silicon book is removed by etching the now exposed portion of the surface. forming a cavity under one of the sidewall oxide layers in the body; and The main surface is bombarded with metal, and the silicone is heated so as to fill the cavity with a metal silicide layer. a metal silicide layer on the now exposed silicon portion of the main surface of the main body; A method comprising the step of forming. 6. In the method according to claim 5, during the process of colliding the metal, substantially no metal or metal silicide builds up on the oxide; It is characterized by the formation and accumulation of metal silicides on exposed parts of the con body. How to make it a sign. 7. In the method according to claim 6, during the process of colliding the metals, The upper major surface of the polysilicon gate electrode is exposed, thereby allowing the process to metal silicide is also generated and accumulated on the main surface of the gate electrode during How to characterize it. 8. The method according to claim 7, characterized in that the metal is platinum. How to make it a sign.