JPS624729B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stored program type step-by-step sequence controller, and in particular, it is possible to return to the original process after power outage recovery by simply changing the connection method of the interrupt signal input terminal. The present invention relates to a sequence controller that allows selection and setting of executing an interrupt program in an emergency.

As is well known, this type of controller is applied to various control objects and must meet a wide range of demands. Therefore, there are a wide variety of commands related to the transition between processes, that is, commands that specify what conditions are met to proceed to the next process, and in that case, which process to proceed to. The dolphin is one of the big selling points.

On the other hand, it is preferable that the hardware structure of this type of sequence controller be as simple as possible. The basic purpose of this invention is to enable the sequencer to exhibit as many functions as possible by using predetermined command words through simple hardware changes.

That is, an object of the present invention is to restore a specific storage area in the user's memory to the state before the power outage by either connecting the interrupt input terminal to an interrupt signal source or disabling the input terminal from interrupts. The purpose is to enable it to be selectively used for writing a return command "RET" to a process number or for writing a jump command "JMP" for an emergency interrupt program.

An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram for explaining the electrical configuration of a sequence controller (hereinafter referred to as sequencer) according to the present invention, and FIGS. 2 and 3 are diagrams showing an example of the structure of an interrupt input terminal. , FIG. 4 is a flowchart showing the operation of the sequencer according to the present invention.

As shown in FIG. 1, the sequencer 1 includes an input interface circuit 2 having a plurality of input terminals into which signals indicating the operating status of the controlled object are input, and an output terminal through which operation command signals etc. to the controlled object are output. A plurality of output interface circuits 3, a user memory 4 for storing a control program that determines how to control a controlled object, and a user memory 4 for writing a control program into the user memory 4, or for operating the sequencer 1, An operating device 5 for performing operations such as stopping, a CPU 6 for controlling program writing, controlling sequencer operation, stopping, etc., and controlling program execution, etc., when an emergency situation such as a power outage or an interrupt occurs. It consists of a process number save memory 7 for saving the process number being executed.

As shown in FIG. 1, the user memory 4 is provided with a series of storage areas with consecutive addresses corresponding to process numbers, and each storage area is designated as "OP", "DATA-1", "DATA-1", and "DATA-1". 2”, “OUT”
It is divided into four columns called . and,
In the “OP” column, the instruction code described later is “DATA−”.
1" and "DATA-2" columns contain data for modifying the instruction code written in the "OP" column, and the "OUT" column contains the "ON" information for each output terminal that should be set when executing the process. ”, “OFF” data is written. In addition, the desired instruction code, modification data, and output terminal ON/OFF are stored in each column in the user memory 4.
To write data, turn on the power switch 51 and program console switch 52 of the controller 5.
Thereafter, the keyboard switch 5a is operated in the following manner.

Next, the instruction code provided in this sequencer 1 and the execution contents of the instruction code will be briefly explained.

(1) "NOP"; Non-operation command This is used to proceed to the next process without doing anything, and is useful for processes that are no longer needed due to process changes.

(2) “END”; End command Indicates that all processes in one cycle have been completed.

(3) “JMP”; Jump command Jumps to the process written in the “DATA-1” column and continues execution from there.

(4) "AND"; AND command When all signals are input to the input terminals corresponding to the numerical values written in the "DATA-1" and "DATA-2" columns, proceed to the next step.

(5) "OR"; OR command When a signal is input to at least one of the input terminals corresponding to the numerical values written in the "DATA-1" and "DATA-2" columns, proceed to the next step.

(6) "CNT"; Count command Counts the signals input to the input terminal corresponding to the value written in the "DATA-2" field up to the value written in the "DATA-1" field, and when the count is up, the next Proceed to the process.

(7) “CJP”; Conditional jump command Also referred to as conditional jump command.
The process jumps to the process corresponding to the numerical value specified in the ``1'' column, and if no signal is input to the input terminal of ``DATA-2'', the process proceeds to the next process.

(8) “RPT”; Repeat command Repeats the current process from the process written in the “DATA-2” column until the number of times written in the “DATA-1” column.

(9) “TIM”; Timer instruction “Minutes” written in the “DATA-1” column,
When the "seconds" written in the "DATA-2" column have elapsed, the process proceeds to the next step.

(10) “2TM・AND”; Timer and instruction When the time specified in the first step and the input specified in the second step are matched, proceed to the next step.

(11) “2TM・OR”; Timer OR instruction Time-up of the time specified in the first step,
Alternatively, the process proceeds to the next process upon receiving a signal again before the input specified for the second process.

(12) "2LG・AND"; 4-input AND instruction When the inputs (4 inputs) specified for the first and second steps are complete, proceed to the next step.

(13) "2LG・OR"; 4-input OR instruction Receive the signal that comes first among the inputs (4 inputs) specified for the 1st and 2nd steps and proceed to the next step.

(14) "RET"; Process return command Jumps to the process stored in the process number save memory 7 and continues execution from there.

As mentioned above, the predetermined process step operation is executed in response to each instruction code due to the action of the CPU 6. Specifically, this action is performed as follows, for example. That is, the CPU 6 includes a process counter that outputs the process number corresponding to the program to be executed, various register groups, numerical values, and logical operation circuits, and the above register groups, logical and numerical values that perform the process step operation corresponding to each instruction code. It has a built-in system memory in which programs to be executed using arithmetic circuits and the like are stored in advance. Then, when the sequencer 1 is operated, a predetermined process number is output from the process counter according to the program in the system memory, and the contents stored at the address in the user memory 4 corresponding to that process number are
It is captured in a specified register in CPU6 and becomes “OUT”.
The signal state of the output terminal is set according to the ON/OFF data in the column. Next, in the “OP” column, “DATA−
Arithmetic execution programs corresponding to the codes written in the "1" column and the "DATA-2" column are called from the system memory, and it is repeatedly checked whether the process step condition is met. For example, "AND""01"
If it is "02", it is repeatedly checked whether the logical product of the signals input to input terminals 1 and 2 is "1", and if it is "CNT", "06", or "07", input terminal "7" is checked. The number of signals input to `` is counted, and it is repeatedly checked whether it has reached 6 or not.
Then, the code in the "OP" column has the meaning of executing the program corresponding to the next process number on the condition that the operation is satisfied, "AND", "OR",
In the case of "CNT", "TIM", etc., the count value of the process counter is incremented by one as soon as the relevant calculation is completed, while on the other hand, it is specified as "JMP", "RPT", "RET", etc. as a condition that the calculation is completed. If the process has the meaning of executing a program corresponding to the specified process number, the content of the process counter is forcibly preset to the specified process number when the calculation is completed. Thereafter, the contents of the address specified by the new process number output from the process counter are taken from the user memory 4 into a predetermined register, and the same operations as described above are performed.

Next, a newly added hardware configuration and system program related to the present invention will be explained.

First, as shown in FIG. 1, the input interface circuit 2 is provided with an interrupt input terminal INT for inputting an interrupt signal. FIGS. 2 and 3 show an example of a specific structure of this interrupt input terminal INT. Among the screw terminals constituting the base 8, the terminal 9 located at the endmost end is used as a common terminal, and the terminal 10 adjacent to this is used as an interrupt terminal. and,
As will be described later, in order to set this interrupt input terminal to an "interrupt prohibited" specification, it is sufficient to short-circuit the terminals 9 and 10 with a jumper wire 11 as shown in FIG. 2, and to set the interrupt input terminal to an "interrupt enabled" specification. In this case, the terminals 9 and 10 may be connected to the interrupt signal source 12 as shown in FIG. 3, and an α contact forming the interrupt signal source 12 may be interposed between the terminals 9 and 10. .

On the other hand, the system memory in CPU6 has a fourth
A system program having contents as shown in the flowchart of the figure is stored.

As described above, after installing the interrupt input terminal INT and storing the system program, write either "RET" or "JMP" to address 0 of the user memory 4 and start the sequencer 1.
Power outage processing or interruption processing is performed through the steps shown in the flowchart of FIG. 4.

That is, write the instruction code "RET" in the "OP" field at address 0 of the user memory 4, and short-circuit the terminals 9 and 10 with a jumper wire 11 as shown in FIG. 2 to set the "interrupt disabled" specification. After that, when the sequencer 1 is activated, routine _R1 is executed to determine the input state of the interrupt input terminal INT. And in this case interrupt input terminal INT
Since the input state of is "ON", that is, terminals 9 and 10 are short-circuited as shown in Figure 2, the routine
The determination result of R ₁ is "YES", and routines R ₂ and R ₃ are subsequently executed, and the user memory 4 is cleared to 0.
The contents of the address will be read to the CPU 6. Then, put “ON” in the “OUT” column of address 0.
If "OFF" data is written, the signal state of the output terminal is set based on the "ON" and "OFF" data when routine _R4 is executed.
Next, routine _R5 is executed to determine that the instruction code in the "OP" column is "RET", and then routine _R6 is executed to preset the process counter with the contents stored in the process number save memory 7. be done. That is, upon execution of routine _R6 , the contents of the process counter are preset to the process number that was interrupted at the time of power outage. And routines R ₃ , R ₄
is executed, the contents of the storage area specified by the process counter are read from the user memory 4, the output setting operation is executed, and then a routine is executed to determine the instruction code written in the "OP" column.
R ₅ , R ₇ , and R ₈ are executed, and a predetermined operation is executed according to the corresponding instruction code. Then, each time the execution of each operation is completed, the routines R ₉ and R ₁₀ are executed.
is executed, and it is determined whether an interrupt signal has been input to the interrupt input terminal INT, that is, whether or not the voltage between terminals 9 and 10 has changed from "OFF" to "ON", and the power supply voltage has fallen below the allowable limit. In other words, it is determined whether or not there has been a power outage. and,
When a "power outage" occurs, the determination result of routine _R10 becomes "YES" and routine _R11 is executed.
The process number being executed at that time is saved and held in the process number saving memory 7. Next, when the "power outage" is restored, the routine goes through the process described above.
R ₁ , R ₂ , R ₃ , R ₄ , R ₅ , and R ₆ are executed in order, and the program is executed again by returning to the process that was interrupted at the time of power outage.

On the other hand, write the instruction code "JMP" in the "OP" field at address 0 of the user memory 4, and
As shown in the figure, after connecting the terminals 9 and 10 to the interrupt signal source 12 to make them "interrupt enabled", when the sequencer 1 is started, the routine starts to determine the input state of the interrupt input terminal INT. R ₁ is executed. If the input state of the interrupt input terminal INT at that time is "OFF", that is, terminals 9 and 1
If there is no conduction between 0 and 0, the determination result of routine R ₁ is "NO", and subsequently routines R ₁₂ and
R ₁₃ and R ₃ are executed in sequence, and the contents of the process counter are preset to the first process number "1" of the normal program, and from then on, the contents of the first position of the user memory 4 are
It will be read out to the CPU 6. In other words, execution of the program at address 0 in user memory 4 will be omitted, and even if "JMP" is written in the "OP" field at address 0, its execution will be omitted only when sequencer 1 starts. It turns out. Thereafter, the corresponding operation is executed according to the instruction code, and each time the operation is completed, routine _R13 is executed and the process counter is incremented by 1. After that, the operation is specified by the contents of the new process counter. The programs are sequentially read out from the user memory 4 and executed. During this time, if an interrupt signal is input to the interrupt input terminal INT, that is, if the voltage between terminals 9 and 10 changes from "OFF" to "ON", the determination result of routine _R9 is "YES".
Then, routine R ₁₁ is executed, and the process number being executed at that time is saved and held in the process number saving memory 7, and then routines R ₂ and R ₃ are executed, and 0 in the user memory 4 is saved. The contents of the address
It will be read out to CPU6. and,
Since "JMP" is written in the "OP" column of this address 0, the judgment result of routine R ₇ is "YES", and then routine R ₁₄ is executed, and the process counter is set to the "JMP" instruction. It will be preset to the process number specified by . Therefore,
User memory 4 specified by this "JMP" command
If you write the program you want to execute in an emergency in the internal storage area and write the "RET" command in the final step, the emergency program will be executed at the same time as the interrupt signal is input, and the interrupt will be triggered when the interrupt signal is input. This makes it possible to return to the original process that was interrupted.

As described above, according to the sequencer 1 shown in this embodiment, the jumper wire 1 is connected between the interrupt input terminals 9 and 10.
1 or by simply connecting an α contact that closes with an interrupt signal between terminals 9 and 10, the program at address "0" in the user memory 4 can be executed constantly, or when an interrupt signal is input. If you use this option, you can simply write the "RET" or "JMP" command to the "0" address above to return to the original process when the power is restored. or execution of an interrupt program in an emergency.

As is clear from the above description, the present invention provides a step-by-step sequence controller that sequentially executes storage commands for process areas sequentially designated by a process counter, provided adjacent to a common terminal on a terminal block. Check the signal status of the interrupt input terminal and the interrupt input terminal during operation.
In response to the change from OFF to ON, interrupt control means saves the contents of the process counter to process number save memory, and then presets the process counter with a specific process number, and controls the power supply status during operation. A power outage control means that saves the contents of the process counter to the process number saving memory in response to the time when a power outage is detected, and a power outage control means that checks the signal state of the interrupt input terminal in response to power on. However, if this is in the ON state, the specific process number is preset in the process count, while it is in the OFF state.
In this case, the system is equipped with a power-on control means that presets the first process number of the normal program in the process counter, so the specifications for handling the interrupt signal terminal have been changed and it has been made compatible with the above-mentioned specific process number. "RET" or "JMP" in the storage area to
By simply writing , it is possible to enable power outage processing or interrupt processing.

That is, according to the present invention, if the interrupt input terminal and the common terminal are short-circuited and "RET" is written in the specific process number area, it is possible to return to the process before the power outage as soon as the power is turned on. If the other two are opened, the normal program can always be executed from the first step when the power is turned on.Furthermore, an external a contact, which is an interrupt signal source, can be connected between the common terminal and the interrupt input terminal. , and write "JNP" in the specific process number area, the original interrupt processing can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the electrical configuration of a sequence controller (hereinafter referred to as sequencer) according to the present invention, and FIGS. 2 and 3 are diagrams showing an example of the structure of an interrupt input terminal. , FIG. 4 is a flowchart showing the operation of the sequencer according to the present invention. 1...Process step-type sequence controller, 4
...Memory for user, 6...CPU, 7...Memory for saving process number, INT, 9, 10...Interrupt input terminal.

Claims (1)

[Scope of Claims] 1. In a step-by-step sequence controller configured to sequentially execute storage commands for process areas sequentially designated by a process counter, an interrupt input is arranged adjacent to a common terminal on a terminal block. The signal status of the terminal and interrupt input terminal is checked during operation, and in response to the moment when this changes from OFF to ON, the contents of the process counter are saved to the process number save memory, and then the specific process is saved to the process counter. An interrupt control means that presets the number, and a power outage control that checks the power supply status during operation and saves the contents of the process counter to the process number save memory in response to the detected occurrence of a power outage. In response to turning on the power, the signal state of the interrupt input terminal is checked, and if it is in the ON state, the specific process number is preset in the process counter, while if it is in the OFF state, the process counter is set to the normal value. A step-by-step sequence controller comprising: power-on control means for presetting the first step number of a program.