JPS6245583B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for performing pattern recognition using a photosensitive device and a network of a number of modules connected thereto. Regarding pattern recognition problems, for example, 1968
“Recognizing Patterns-Studies in Living and
Today's devices suffer from the disadvantage of requiring a central computer to analyze the scanned data, as described in Chapter 6 of ``Pattern Recognition - A Study of Living Automatic Systems''. However, it also requires a complex matching of the scanned data and the stored data. On the contrary, the pattern recognition method according to the invention does not have any of these drawbacks. A transmission network or device that has been developed and used during the There are countless variations of transmission networks or devices for producing a particular response from a device. Examples of such transmission devices include ordinary computers, e.g.
There are models such as M7094, and in these, calls are made to reproduce stored information as needed. Also, telephones or related devices that classify dialed information and transmit it to specific locations along predetermined routes, or to check for the presence or absence of predetermined patterns of numbers or other information. There are pattern recognition devices used. The various forms of network and transmission technology that have been developed over the past several decades to solve problems associated with transmission applications include a myriad of methods for network equipment. However, many machines, particularly of the type described above, required a device for addressing the core memory and an interrogation mechanism for locating a module or word or other information, regardless of its contents. This requires identifying each location in memory of the information, including special numbers, reference characters, etc., and providing direct access (call) to each location from the central processing unit. To overcome some of these complexities, computers are equipped with so-called systems that include, for example, distributed storage and logic to enable data reproduction without knowledge of the data's location. It has been designed to have an associative memory device. However, techniques for implementing this have the disadvantage of requiring the use of a central processing unit that must be wired to every module or cell of the storage device. If the central processing unit were to fail, all associative memory playback devices would also fail. Accordingly, the present invention provides a method for performing pattern recognition using a network device that does not suffer from the above-mentioned disadvantages. In summary, the present invention allows transmission between storage logic modules without the need for an addressing mechanism, i.e., without knowledge of the location of all other modules, and without the need for a central processing unit connected to every module. In this method, pattern recognition is performed using a photosensitive device connected to a circuit network that enables this. Further, according to the present invention, it is possible to cause any module to send a request message for certain information and to propagate that message to all remaining modules, and a module that responds to the message (that module is searched) from the module containing the information to be sent along an efficient path to the module that requested the information (and without cycling in the response path).
And each module is completely "ignorant" or uninformed about the positions of other modules than the few adjacent modules to which it is directly coupled. Still another object is to provide a new and improved device that makes it possible to study neural networks, etc. in living organisms from the viewpoints of (1), (2) and (3) below. (1) Great adaptability of the modular arrangement of the present invention; (2) Utilization of one-way connections found in the nervous system; and (3) Absence of a central unit, which also does not exist in the nervous system. The brain, for example, seems to lack such a unit, but it can still function even if it is divided into several parts. Yet another object is to provide a new and improved circuitry for use in more general applications as well. Another feature of the invention resides in the novel method of transmission response based on the invention, which, once again, is applicable to many different types of equipment and devices for which the advantages of the invention are sought. It is widely applicable to problems. Although the invention is described below for purposes of illustration in a preferred embodiment in connection with an electrical or electronic network device, the principles underlying the device of the invention are not limited by such technology; It may be performed by many different types of equipment and even by different types of operators. However, furthermore, although the present invention is described in connection with a two-dimensional network, it could easily be extended to a three-dimensional network using well-known techniques, if desired. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the accompanying drawings, the circuit network used in the present invention will be explained first, and then the pattern recognition of the present invention using this network will be explained. In FIG. 1A, a preferred storage-logic module is shown as, for example, the number 1,
It has six bidirectional channels or connections labeled 2, 3, 4, 5, and 6. This constitutes a six-sided or hexagonal module. The invention relates both to networks consisting of modules with bidirectional channels and to networks consisting of modules with unidirectional channels either in the direction out of the module or in the direction toward the module. 6
Various arrangements of unidirectional channels in the corner module can be used, several of which are shown in Figures 1B, 1C, and 1D. FIG. 1E shows a rectangular module with bidirectional channels 1, 2, 3 and 4. Figures 1F and 1G also illustrate the arrangement of unidirectional channels in a rectangular module. In the example of FIG. 1D, channels 1, 3 and 5 carry messages to the module, while channels 2, 4
and 6 are adapted to take out messages from the module. This is arbitrarily referred to as "Class K" operation. FIG. 1B, on the other hand, shows "Class D" operation, where channels 1, 2 and 6 bring messages to the module, while channels 3, 4 and 5 carry messages out. 1st C
The figure also shows another arrangement of "classes" in which the input channels are 1, 2 and 4 and the output channels are 3, 5 and 6. Obviously, other arrangements and combinations of these classes of operation may also be used. Similarly, in the square module embodiment of Figure 1F, channels 1 and 2 carry messages;
Channels 3 and 4 then transmit messages, while in the module of FIG. 1G, channels 1 and 3 are input channels and channels 2 and 4 are output channels. Each module has parts called a logic unit and a storage unit, regardless of its geometrical shape. These are operated according to the decision principles explained below. Briefly, each module receives two forms of messages. That is, a general message, which is also referred to as a "message" in the description of the present invention, and a response message, which is also referred to as a "response." For each module, the general message arrives first,
It stores in its memory unit the identification names of the channels that send the message to all of its output channels. And later, if a response arrives, it is sent out to one output channel determined by a decision principle based on the identification of the channel on which the general message first arrived, as will be explained later. The storage unit of each module can be columnar or circular, with a capacity according to the intended application, but large enough to hold information about the channel on which the general message first arrives. Must have. If one or more other generalization messages are expected to be sent before the response arrives, the storage unit stores the identification name of each generalization message and the first arrival of each generalization message. It must be possible to maintain the channel's identification name. Assuming that several general messages arrive between responses, the logic unit of each module determines whether the incoming message is a general message or a response message. This is done by using the first pulse to indicate the nature of the message if the message is sent as a train of pulses, such as a "0" indicating a general message and a "1" indicating a response message. This can be easily done by FIG. 2 shows a typical circuit network using "K class" and "D class" hexagonal modules. The module, indicated by the dot in the center of the drawing, may have the structural shape shown in FIG. Many such modules are distributed throughout the network,
It is observed that each is represented by a small dot. The central module is “K class” (first
The channels 2, 4 and 6 are shown as unidirectional channels in the form of FIG. Channels 1, 3, and 5 also have arrowheads pointing toward the center of the module, indicating that they receive information supplied to the module. Similar conventions are used for channel connections in all other modules of the network arrangement of FIG. In this example, module ¹ has a channel connection with its right neighbor (connected to module channel 4) of "Class D" (Figure 1B).
is shown as having a connection of 2'
and 6′ channel connections have inward arrows;
The 3', 4' and 5' channel connections have outward pointing arrows. Thus, this network is “K
1. Some of the modules, such as ^I2 , have their channels shown in FIG. Although some are shown rotated from the position shown, the class remains the same and will be treated in the same way from now on.Also, some channels are missing around the perimeter of this network.These The output channel is simply connected to one of the existing output channels. Otherwise, the end module operates exactly like the other modules. According to the invention, FIG. The network includes a plurality of storage-logic modules, each of which accepts an input message and, depending on the format of the message, delivers an output message. They are connected to a rectangular collection and circumscribe each other at least partially.For example, modules ¹ , ² , ³ , ⁴ , ^I5 , and ^I6 are connected to a hexagonal group that circumscribes the central module. This hexagonal aggregate constitutes a group of aggregates, and then this hexagonal aggregate has modules ¹ ,
² , ³ , ⁴ , ⁵ , ⁶ , ⁷ , ⁸ ,
It is circumscribed by the next group of peripheral hexagonal clusters formed by ⁹ , ¹⁰ , ¹¹ , ¹² , and this connection is continued in sequence to complete the complete network arrangement. Furthermore, according to the invention, each module of one collection is connected only to adjacent modules of other collections. For example module ¹
is shown connected to the adjacent module ¹² by a conductive unidirectional channel 3 ^' ;
¹ means module ¹ by channel 4'.
The adjacent modules ² are connected by channels 5', which in turn connect them to other parts of the network. These connections, as described above, consist of unidirectional connections between the output of one module and the input of its adjacent module (unidirectional outward connections 3', 4' and 5' are Corresponding modules ¹² , ¹ and
² ). Furthermore, the arrangement of channels is such that between any two modules,
Passages are now provided to allow transmission between them; for example, 6 and ⁶ .
² , transmission is allowed on channels 2' and 5'. With this type of connection, for example, in a network configured as shown in Figure 2, any module can signal a request message requesting information (a general message); Signals can be transmitted to all other modules in the network. Also, the other module or modules that contain the requested response (information) do not have "information" about where the request message came from, as far as multiple modules in the network are concerned. If not, it automatically routes its response through the collection of modules to which it is adjacent and the collection of modules that follow them, and causes this response to be sent to the first module that issued the request message. That is, according to the present invention,
It turned out that these completely new results could be obtained. How this happens is explained below. For example, request message (general message)
is issued by the logic-memory module shown in the center of FIG. The filled arrowhead (▼) in FIG. 2 shows how this message first reaches another module. The same message will appear on other channels of the module after some time delay, but such later arriving messages will be rejected as discussed below. For the sake of explanation, the response message to the request message is “K class”.
(but the message that is the source of the requesting message does not "know" this fact in advance). When the request message (summary message) reaches module V, module V sends a response message. And a series of modules between modules,
Each is completely independent of and has no information about the other modules, but so that the response message from module V reaches the module through a reasonable shortcut without circulation.
operate collectively. This is accomplished in that each module receiving a response sends this response according to a decision principle based on the identification of the channel on which the request message first arrived. The rules and design philosophy of this determination for "K line" and "D class" modules are as follows.

[Table] The rules for sending response messages are as follows:
It depends solely on the channel and does not depend on the spatial configuration of the modules. The channel identification number is independent of the direction of the channel in the diagram.
Continue to show channels related to it. For example, D
Input channel 2' of module ¹ , which is
Specified as 1', 6'. Also, the input channels of module ¹² , which is also class D ^, are 2″, 1″,
6". By this method, the first
The channel relationships in diagram B are saved. In applying the response orientation rule or decision principle,
Numerical primes, etc., may be omitted when designating channels, such as in the case of modules. In Figure 2, module V is class K (1D
), which accepts a general message along its input channel 3 and transmits its response message to its output channel 2 according to the decision principle. Similarly, the modules are of class D (1B
), and since the general message was received on channel 6, a response message is passed along channel 5. The module receives the general message on channel 2 and sends out a reply message on channel 3, which is continued to module ⁶ and _I4 .
The response thus passes through the path marked by the dotted arrow. In this way, it will be seen that a response issued from any module will reach the module that issued the general message via a reasonably short path with no loops. It is clear that any module, not just the central module, can act as a general message source. FIG. 3 shows a network constructed from the rectangular class C modules of FIG. 1F. Again, each module is connected to its adjacent module of the same type by a unidirectional channel, and a transmission path exists between any pair of elements. The same conventions as in FIG. 2 are used for the direction of the channel and the channel on which the general message first arrived and the response path. For purposes of explanation, let module S ¹ , which is the most central, be the starting point for the general message. The table shows rules for direction of responses.

[Table] Assume that module S ² has a response to the general message issued by S ¹ . Since S ² receives the general message on input channel 1, the response is directed to output channel 4 of S ² . Since ^S3 receives the general message on channels 1 and 2, the response message is sent out on channel 3 and thus passes through ^S4 to ^S10 before reaching the general message source. Figure 4 shows a circuit network composed of six K-class modules. Now assume that module H is selected as the general message source. Again, assume that the filled arrows (▼) indicate the pattern of the general message that first reached each module. The rules for directing responses are shown in the table. Now assume that module H ¹¹ at the top of the diagram contains the response. Since the general message will arrive on input channels 1 and 5, the response will be directed to output channel 6. H ¹⁰ , which also receives the general message on channels 1 and 5, directs the response to 6. Since ^H1 will receive the general message to 5, the response will go out from 4. And in this way, the response reaches the module H, which is the source. Directing the response after the general message has propagated can also be accomplished by a network constructed of modules having bidirectional channels as shown in FIGS. 1A and 1E. For example, when a circuit network is appropriately configured with modules having unidirectional channels as shown in FIGS. 2 and 3, and when a circuit network with a similar configuration is configured using modules with bidirectional channels. , the propagation time of the general message and the return time of the response are almost the same. However, the need for logic and storage capacity is much lower for networks consisting of unidirectional channels. This is because a bidirectional channel is equivalent to two unidirectional channels with opposite directions. Thus, for example, in a hexagonal bidirectional channel network, each module appears to have six input channels and six output channels that do the same job. The method of input and output to the network, whether response messages or summary messages, depends on the particular application. For example, to briefly describe the pattern recognition case of the present invention described below, a general message is ejected into the network at the end, and a response message is generated by the module and collected from the end. Furthermore, in very general transmission operations between computers located far apart, it is desirable to input a general message from the outside and extract response messages from each module of the circuit network. To do so, an extra input channel from an external device (eg, a computer) and an extra output channel to the external device would be added to each module. These extra channels will be made clear in the detailed discussion of module construction in conjunction with FIG. By using such a circuit network, the pattern recognition method of the present invention is implemented. This makes it possible, for example, to easily identify the direction of angles and the length of straight lines, to detect curvature, and to recognize the alphabetic characters of certain typefaces. To illustrate this feature of the invention, assume that there is a closely packed bank of photovoltaic cells or other light sensitive devices on top of the network, each triangular in shape with equal sides, and a hexagonal circuit. It is assumed that it is located above the triangle formed by the mesh channel.
Let the positions of two such photovoltaic cells be P ₁ and P ₂ ,
It is shown in the lower right corner of FIG. Each photovoltaic cell is connected to three modules at its three vertices. And when the photocell is blocked by a certain image,
All three modules connected to it will be "activated" or "on". Each module has 6 triangular areas and therefore 6 photovoltaic cells.
Since it is surrounded by six vertices, one module can be turned "on" by any of these six photocells. A bank of photovoltaic cells operated in this manner converts the normally continuous projected image into a discrete representation on the network. This is a common process for many approaches to pattern recognition. In FIG. 5 the discontinuities in the image of the thin line LL ¹ are illustrated. As mentioned later, this is the fourth
The figure is shown in a modified form. When an image enters or traverses the triangular area formed by the channels of the network, the three modules at the vertices are activated via the photocells in that area. Thus modules C ¹ -C ¹⁹ will be activated by image LL ¹ . Returning to Figure 4 to make some observations about the propagation of the general message. Axes (always defined in relation to the general message source) H-A, H-
Except along C, H-B, the total live message reaches two channels of the module simultaneously. Furthermore, there are three regions where the pattern of arrival is uniform. That is, in the area of HBA'C, the general message reaches input channels 1 and 5. In the area of HCB'A, input channels 1 and 3 are simultaneously reached, while in HAC'B channels 3 and 5 are reached. Then, if module H ¹² in corner A sends a general message, the entire hexagonal network behaves like area HBA'C. That is, all modules except those along the H ¹² axis (A-B' and A-C') receive general messages on channels 1 and 5 simultaneously. This can be understood by visually moving module H to corner A. Similarly, the transmission from H ¹⁴ in corner C arrives on channels 3 and 5 simultaneously, and the transmission from H ¹³ in corner B arrives on channels 1 and 3. These three corners A, B and C, whose transmission of the general message will produce a uniform arrival pattern as described above, are referred to as the primary corner ( We will call them ``PRIMARY corners''. Here, it is assumed that the unit time is the time required for one message to go from one module to the next module. When propagating from a signal source, a general message will go to a module along the shortest path present. Therefore, the arrival time of the general message can be easily determined by learning the modules that exist between the signal source module and a particular module along the shortest possible path. Thus, in Figure 4,
Modules H <sup>1</sup> , H <sup>2</sup> and H <sup>3</sup> will receive the general message first, ie starting from H, in one unit time. Elements H <sup>4</sup> to <sup>H 9</sup> receive the summary message in 2 time units. It is immediately obvious that the "cotemporal" lines of propagation are concentric triangles, and that in any region such as HBA'C the lines are parallel. The network AC'BA'CB' of FIG. 4 appears transformed in FIG. 5 to form a star network. Associated with each primary corner are two star points (star vertices). The star point on the right side when looking at the circuit network from one primary corner is called the right star point, and here
It is called RSP. The one on the left is called the left star point and is referred to here as LSP. Thus, for the first corner C, RSP <sub>C</sub>
and LSP <sub>C</sub> , and the same holds true for even A and B of the first order. When a general message is sent from an RSP or an LSP, the network receives the same uniform arrival pattern as would be obtained by sending from the relevant primary corner of the star point.
Formed on AC′BA′CB′. For example, the transmissions from RSP <sub>C</sub> and LSP <sub>C</sub> arrive simultaneously on input channels 3 and 5, as do the transmissions from corner C. For example, module C <sup>21</sup> in Figure 5 is
Receive the general message from RSP <sub>C</sub> on channels 3 and 5. This is indicated by a solid arrowhead (▼). C <sup>25</sup> receives a summary message from corner C in the primary corner on channels 3 and 5, which is indicated by a solid arrowhead with a bar (▼). Similarly, module C <sup>5</sup> in the center of the network of FIG. 5 will receive general messages from RSP <sub>C</sub> , LSP <sub>C</sub> or C on channels 3 and 5. RSP and LSP form the same arrival pattern to each module in the network, but the time path from the generation of the general message to the arrival of the module's response message is different for RSP and LSP. This will be explained below. A method for determining this elapsed time is also described, which may also be used in pattern recognition applications discussed below. The terms used below are defined as follows. Tracks: lines formed by alignment of channels, e.g. lines n <sub>1</sub> −n <sub>1</sub> ′, n <sub>2</sub> −n <sub>2</sub> ′ and n <sub>3</sub> −n <sub>3</sub> ′ near LSP <sub>C</sub> or line n <sub>4</sub> −n near RSPc <sub>4</sub> ′ and
<sub>n5</sub> − <sub>n5</sub> ′. Related tracks of star point: Tracks that face the star point, such as n <sub>1</sub> −n <sub>1</sub> ′, n <sub>2</sub> −n <sub>2</sub> ′, etc., face LSP <sub>C</sub> , so these are related tracks of star point LSP <sub>C.</sub> The associated track of star point RSP <sub>C</sub> is n <sub>4</sub> −
n <sub>4</sub> ′, n <sub>5</sub> −n <sub>5</sub> ′, etc. RESPONSE RETURN TIME−
(abbreviated as RRT): The time lapse from the start of a general message in a module until a specific response arrives in the same module. for example
The RRT of the response from C <sup>21</sup> to the general message from RSPc is 6. This is because the shortest time for a summary message to reach C <sup>21</sup> is 3 time units. Also, by applying the response orientation rules in the table, the response is
It is found that it takes 3 time units to reach RSP <sub>C</sub> , thus giving an RRT of 6. With the configuration of the circuit network shown in Figure 5,
For a given star point, the responses from modules that exist along the track associated with that star point are
All RRTs are equal. For example, one track associated with RSP <sub>C</sub> is n <sub>4</sub> -n <sub>4</sub> '. Thus, the RRTs for C <sup>23</sup> and C <sup>24</sup> are all 3 units of time, as can be easily seen from FIG. The other related track of RSP <sub>C</sub> is n <sub>5</sub> − n <sub>5</sub> ′, and the C <sup>20</sup> , C <sup>21</sup> and C <sup>22</sup> existing on this track
RRT is 6. Further, the RRT for the module existing along n <sub>6</sub> −n <sub>6</sub> ′ is 9. To obtain the RRT for each of the further related tracks,
It is obvious that all that is required is to add the three unit hours. Therefore, if we have 3 units of time, 1
If we redefine the unit time so that , we can obtain the RRT by adding 1 to each passing related track. According to the terminology according to this new convention, the RRT for RSP <sub>C</sub> is 1 for modules along n <sub>4</sub> −n <sub>4</sub> ′, 2 for modules along n <sub>5</sub> −n <sub>5</sub> ′, and so on. Become. Thus, the RRT from a particular module in a network can be easily determined by simply counting the number of associated tracks lying between a given star point and a given module. According to this method, the response from C <sup>6</sup> to RSP <sub>a</sub> is
It is readily apparent that the RRT is 7, while the RRT from C <sup>6</sup> to LSP <sub>a</sub> is 8 units of time (new units). Three facts have been established for the network in FIG. (1)Left or right star point (LSP or RSP) of one primary corner (A, B or C)
is the circuit network as well as these primary corners.
That will produce the same general message arrival pattern on the channels of modules in AC′BA′CB′. (2) When a general message is sent from one primary corner or either of the star points to the left or right of it, the arrival pattern of the general message to all modules of the network without ends is It's the same. (3) The response return time (RRT) of a response from a particular module to a star can be determined by counting the number of associated tracks from that star to the responding module. As previously defined, the associated track of a star point is the track facing that star point. Next, we present the rules by which the network performs the type of recognition described above. 1. Each of the six star points sequentially sends out an uncoded general message in the form called UNCODED. 2. When a general message arrives at a module (as shown earlier, it will arrive at the same time on two channels of the internal module): (a) If the module that received it is connected to the associated photocell If the module is already in the "activated state" or "on state" by Sends one CODED general message.
"CODED" simply indicates that the module that sends it is in the "active" state. A code can be indicated by a prefix or by the state of a single prefix bit, where a "0" is an uncoded state and a "1" is a non-coded state.
will indicate the coded state. (b) If the module is ``inactive'' or ``off,'' then the module will send messages to all of its output channels, whether or not the input general message is
Sends a general message of UNCODED. 3 (Response rule) If the module is in the activated state and the UNCODED general message arrives on both input channels at the same time, then the module is coded on all output channels. After sending the general message, a response message is sent along the channel determined according to the rules in the table. Recognition of angles, lengths, curvatures, etc. is accomplished by analyzing the response messages received by the star point thus generated and from which the general message was generated. Let us apply the basic side of this response to the image produced by the straight line LL' in FIG. As shown above, this image shows that only modules C ¹ -C ¹⁹ are in the "activated" state. The general message may be sent from RSP _C or
Even though it originates from LSP _C , it simultaneously reaches channels 3 and 5 of module C ¹ in uncoded form. This is because both star points produce the same arrival pattern (as explained earlier), and C ²⁶ and
This is because both ^C27s are in the "off state" (thus emitting an uncoded general message). Therefore, C ¹ sends a response message to RSP _C or LSP _C. Similarly modules C ⁴ , C ⁶ and
^C9 also sends out a response message. All of these modules are shown surrounded by a circle. On the other hand, C ² , C ³ , C ⁵ , etc. accept general messages in encoded form along at least one channel and therefore do not send response messages. As previously discussed, the response return time (RRT) at a star point can be easily determined by counting the number of associated tracks between that star point and the responding module. Thus, C ¹ ,
The RRTs with RPS _C for C ⁴ , C ⁶ and C ⁹ are 5, 7, 8 and 10 respectively, while for LSP _C we get 9, 8, 7 and 6. Here, the minimum
Assume RRT is 0. Methods based on this assumption only need to count related tracks between responding modules. Then, the RRT for C ¹ , C ⁴ , C ⁶ and C ⁹ is 0, 2, 3, 5 in RSP _C.
In LSP _C , it becomes 3, 2, 1, 0. The average RRT calculated in this way, that is, the average response feedback time, is defined as follows. = maximum value of RRT/number of responses received - 1 or 1.0, whichever is greater.Thus, for line LL' in FIG.
In RSP _C is 5/3 or 1.66, and in LSP _C
In this case, it becomes 3/3 or 1.0. The procedure described here is one that converts a portion of an image seen from a star point into a series of responses (hereinafter referred to as a sequence). The average response return time is a summary representation of this sequence. Thus, when projecting an image onto the network, the average response return time marked by all star points becomes a modified representation of the image, which can be used to identify the image. Figure 6 is a reproduction of the circuit network in Figure 5 rotated by 60 degrees. Corner A appears on the left. The direction of the channel is not shown because it is easy to see. Projected onto the circuit network is the image of the letter B. Large black dots indicate activated modules. Module-X is responsive to LSP _A and RSP _A and is shown encircled.
Those responding to RSP _B and LSP _B are shown enclosed in rectangles. The modules shown surrounded by triangles are those responsive to LSP _C and RSP _C. Considering LSP _A , it receives 10 response messages. First comes the response message from the module. This RRT
That is, the response return time is set to 0. The last response message to arrive is from X. this is
It will be reached in RRT15. This is because there are 15 related tracks of LSP _A between I and X. Therefore, the average response feedback time in LSP _A is 15/(10-1), or 1.7. The others are as follows. At RSP _A = 12/9 = 1.3 At RSP _B = 9/2 = 4.5 At LSP _B = 3/2 = 1.5 At RSP _C = 1 At LSP _C = 1 The appearance of this series of average response return times is as follows: This is a representation of the letter B as observed by the net. Recognizing B at the later stage is achieved by matching the series of time aspects described above with the series of time aspects actually obtained at the later stage. Therefore, if you obtain the appearance of such a series of average response feedback times for other characters and figures in advance, you can later compare the appearance obtained when other characters and figures are actually applied. According to
The characters and figures can be recognized. The network of FIG. 5 is reproduced in FIG. 7 without any rotation. Straight line segment L1,L
2, L3, L4 and line segments C1, C with curvature
2, C3 are shown together with the network representation of these line segments indicated by black circles. RPP _C or
Modules that respond to general messages from either LSP _C are circled. Although all line segments are shown condensed here for comparison purposes, the following description will be made for the case where only one line segment appears at a time. As is clear from the response rules and Figures 5, 6 and 7, a response message to a star point in a corner will originate from the edge of the image facing that corner. Therefore, the responses from the module to the three corner star points A-C indicate the edges or boundaries of some image projected onto the network. The network of the invention can therefore be used as an image edge detector. Furthermore, by examining the temporal continuity of a series of response messages received at a star point, the shape of the edge of the image can be detected. In particular, the following is true. That is, when the edges of the image are formed by straight lines, the time intervals between a series of response messages received at one star point are kept approximately equal.
If the edge is a convex image, the time interval at the left and right star points of the corner facing the edge starts to increase after a constant value. If the edge is a concave image, the time interval at the star points on the left and right of the corner facing the edge starts from a large state, gradually decreases, and then a time interval of a constant value continues. . These conditions become more pronounced as the density (number of elements per unit area) of the network increases. Consider the line segment C3 in FIG. 7 as a convex end of a certain image. RSP _C will first receive Z ¹ . This is because the module is in the closest related track of RSP _C. Counting the related tracks, the intervals between response messages are ^Z2 to ^Z9 , which arrive at a time interval of one unit time,
It turns out that Z ¹⁰ will arrive following Z ⁹ with a time interval of 2 time units, Z ¹² will follow after a further time interval of 3 time units, and so on. In LSP _C , Z ¹³ to ^{Z 5} will arrive in time intervals of one unit time, and Z ⁴ to Z ¹ will arrive in increasing time intervals. This time, consider the line segment C1 as the end of a concave image. X ¹ will reach RSP _C first. This is followed by X ₂ after 4 units of time, and then X ³ for another 2 units.
will continue after a unit of time. The same time interval is maintained between X ³ and X ⁴ . However, X ₅ ~ X ¹² is 1
They will arrive at time intervals of unit time. Also
In LSP _C , the same behavior is maintained, with large time intervals decreasing and later becoming time intervals of one unit time. On the other hand, when the straight line segment L4 is taken as the end of the image, all of the responses Y ¹ to ^{Y 5} reach RSP _C at a time interval of approximately 2 unit times. These are received by LSP _C at time intervals of one unit time. Therefore, according to the present invention, it is possible to know whether the edges of an image are convex, concave, or straight. The network can also be used to determine the direction of the angle and the length of the straight image edges by the method of the invention. That is, in FIG. 7, L1 is corner C.
It is observed that L2 gives only one response to the star point, L2 gives 4 responses, L3 gives 7,
And it is observed that L4 gives 5 responses. Here all line segments have the same length. Therefore, it is clear that the difference in the number of responses received for each line segment at the left and right star points of even C is due to the angular direction. Also, in the case of corner C,
It is clear that the maximum number of responses is obtained when the line segment is vertical (up and down in the figure). As the angle approaches ±30° to the vertical, the number of responses approaches 1. Another important thing is that the average response return time also changes as the line segment angle changes. Since the average response return time is not length-based, it represents the average response return time of line segments L2, L3 and L4, which can be used to estimate the angle, independent of the length of the line segment. It is shown in L1 will be discussed later.

[Table] The vertical is defined as 0°, and the angle in the time direction is positive. It can be seen that at 0° both star points record an average response return time of 1.0. As the angle increases towards 30°,
in RSP _C increases, while in LSP _C remains at 1.0. For angles less than 0° and more than 30°, reactions occur. In this way, RSP _C
is sensitive to angles between 0° and 30°, while
LSP _C is sensitive to angles between 0° and -30°. Since corner B is rotated by 60° with respect to corner C and is otherwise identical, RSP _B and LSP _B are sensitive to angles between 30° and 90°. Dew. Corner A is B or C
It is the same except that it is rotated by 60 degrees. Therefore, RSP _A and LSP _A will be sensitive to angles between 150° and 90°. Since we started at -30°, the range of all three sets of star points will cover all angles, from 0° to 180°. Line segment L1 gives only one response ^W1 , even though it has the same length as the other straight line segments. All other activated modules along L1 do not emit response messages in order to receive the general message coded along at least one channel. The angle of L1 is -30°. Even if it were 30 degrees,
Again, only one response message will be emitted, regardless of length. However, slightly rotating the network will cause multiple responses and move L1 to one sensitive region of the star point. The range over which the line segment angle lies can be determined by identifying the star points that have the largest average response return time. For L2,
This is LSP _C as shown in the table.
Thus L2 must be between -30° and 0°, which is the overreaction range of LSP _C. In this way, when the 30° interval between line segment angles is determined,
The exact value within this range is given by: where θ is an angle between 0° and 30°, and is the maximum value of the average response return time received at the two corner star points facing the line segment. The actual angles of L2, L3 and L4 are -16.6°, 0° and 11.3°, respectively. The values calculated by the above formula are -16.2°, 0° and 11.0°. By considering lines L2-L4 in Figure 7, increase the length of the edge when the edge of the image lies in the sensitive area of the two star points in opposite corners of the edge. and the number of responses is also shown to increase.
The increase in response obtained for a given increase in length then depends on the angle of the line segment forming the end. Therefore, given the number and angle of responses, the length of the channel can be used to determine the length of the end. Since the angle itself can be determined from the larger average response return time at the star point, the length can be determined from the number n of received responses according to the formula shown below. Length=(n-1) ^√2 ++1 All line segments L1 to L4 have a length of 11 channels. When the above formula is applied to L1 to L4, 0,
10.2, 10.4 and 10.6 are obtained. “0” of L1
The length reflects the fact that L1 is not actually present in the sensitive region of RPS _C and LSP _C. These star points simply “see” the edge of L1
It is. The values for L2-L4 are all in good agreement, especially from the point of view of the individualization of the images to obtain the representation on the network. From the fact that after a series of responses at time intervals of constant unit time, the time intervals tend to increase, we determine that the edges of the image are convex,
The average curvature can be calculated. Now, N is 1
Let T be the number of responses that occurred after the first response that comes in a time interval greater than , and let T denote the time at which these responses were received. The curvature (radius) is then given by the following equation using the length of the channel. The values of T and N at RSP _C and LSP _C for curves C1 and C3 are shown in the table.

[Table] The actual radius of C2 and C3 is 30 each.
and 41. The average radius calculated at the two star points is 30 for C2 and 42 for C3. A good match is also obtained here. The design of the logic-storage module will first be discussed in connection with the transmission methods embodied in the networks of FIGS. 2, 3, and 4, and then in
Consider the relevance of pattern recognition embodied in the networks of Figures 6 and 7. The module contains relatively basic and well-known logic and memory circuitry, and is susceptible to a wide variety of variations. In Figure 8,
The example rectangular module of FIGS. 1F and 3 is shown as a functional block diagram. However, it should be understood that other well-known circuit arrangements may be readily substituted, and thus the other modules of FIG. 1 may be suitably constructed in a similar manner. Referring to FIG. 8 for explaining the broad principles of operation, input channels 1 and 2 are shown providing input messages to element 1A. If it is determined that the input message is a general message, the identification information of the channel through which the general message first arrived is stored and stored in memory along with the message's identification name. The message shall not be rejected. The total activity message is conveyed to all output channels by block 2B. However, whenever a general message reaches one channel of a module, the same message also arrives, with a slight delay, on the other channels of that module. Arrivals after this should be rejected and should not be propagated. The comparator 2A compares the identification name of the incoming general message with the identification name stored in memory.
Performs this rejection function. If there is a match, subsequent summary messages are discarded. If it is determined by 1A that the input message is a response message, the code or identification of the incoming channel of the corresponding general message is recovered from memory via comparator 3A, and this code Accordingly, according to the rules set forth in the table and FIG. 3, the response message is directed to the appropriate output channel through 4A. 9 and 10 illustrate complete block diagrams for the implementation of the module shown in FIG. 1F, including typical connections for receiving and transmitting messages. Functional block diagrams 2A and 3A of FIG. 8 appear in detail in FIGS. 9 and 10. In FIG. 9, a signal to any input channel can be applied to the following seven parallel conductors on that channel's seven parallel conductors.
(The appended letter at the bottom right indicates the channel number in Figure 1F). That is, enable bit E, response/summary message bit R, 5.
The number of identifying name bits M ₀ -M ₄₀ can be determined arbitrarily and can be chosen according to suitable variations in design. Channels for input from a device (eg a computer) and output to the same device may also be provided; all such output and input channels are marked with a D suffix. The input lines are routed through inverters and groups of NOR gates 13-18 such that whenever a signal appears on any input channel 1, 2 or D, a signal is provided at the output of the NOR gate. The signals from the NOR gates, together with the enabling signals E ₁ and E ₂ of channels 1 and 2, are temporarily given to the memory 19 for later use (the output signals from here have their stored (The subscript S is added to indicate this.) E _io from Noah Gate 1
The signal is for triggering a series of one-shot multivibrators 2, 3 and 4 for clocking the memory 19 to enable the memory and providing a time delay for entering the memory and delivering the output signal. used for. The identifier bits SM ₀ -SM ₄ of the memory 19 are immediately sent to the match comparator 0' for comparison with the identifier that will be stored in the memory of the compare-storage block.
~3'. Four such blocks are shown, but any number of blocks can be used (a typical comparison-memory block is the 10th block).
(detailed in the figure). 2A in Figure 8
and 3A are both comparators and their functions are substantially similar, so they both use the same elements in FIGS. 9 and 10. Elements corresponding to the blocks of FIG. 8 are shown surrounded by a dotted border. For example, I and J in FIG. 10 belong to block 3A in FIG. Elements 20, 2 in FIG.
3, 24 and 25 constitute a continuation of 2A in FIG. A comparison between the identification bits SM ₀ -SM ₄ of the input message and such bits previously stored in memory blocks 0'-3' is shown in FIG. When completed with E, F and G, the output of gate H is “X true” (the subscript X indicates blocks 0' to 3'
) indicates that there is a match in this memory block. This match signal serves two functions. First of all, it allows the signal from the NOR gate 20 to generate a true signal, indicating that the identifier in question is available in memory. Secondly, it is
enable the E ₁ and E ₂ output signals (by providing signals from I and J to the NOR gates 21 and 22) and the corresponding input channel number of the previously stored general message, i.e. the general message arrival code. instruct. The signals for these channels and their inverses are connected to NAND gates 27 and 28 which orient correctly according to the table orientation rules. These directing gates allow output gating for the appropriate response channel unless a signal is generated from 25 or 26. If the SR bit at 19 is "off" (indicating input of a general message) and no true signal is generated at 25 (indicating that this message has not been previously stored in memory) ) when
A store and send all signal is generated at 26.
This signal is connected to a series of three NOR gates 29-3 used by this signal and the orientation control signal.
1 to enable all output channels. This signal also applies to gate A in FIG.
The memory load signal is used in conjunction with the counter signals 0'-3' in gates 9-12 to store the incoming distinguished name bits SM in the memory block next to block 0'-3'. ₀ − Load SM ₄ . After the memory load is completed, the one-shot multivibrator 6 moves from block 0' to
Counters 7 and 8 are advanced by one to the next position in preparation for the next memory load signal for loading the next memory of 3'. On the other hand, if the accumulated response bit SR is "off" and the general message is accumulated in memory, or if the accumulated response bit SR is
If SR is "on" indicating a response message and no corresponding general message in memory, the E send signal is inhibited by 23-25 and any output signal is prevented from being sent. Ru. NAND gates 32-52 and inverter drivers on the output lines perform the send or inhibit function for each output line. The subscript indicates the channel number. Element 1A of FIG. 8 is not shown in FIG. 9, but this takes advantage of the fact that there is no need to separate the response message from the summary message until the memory is examined to find the identifier. This is because the. As can be seen from Figure 9, element 1
The functions of A are accomplished in a different order. If the identifier is not stored or in memory (true) and the response bit is "off" (general message condition), then NAND gate 29, 26 sends the message to all output channels. 30 and 3
1 is possible. Otherwise, the message is directed by 4A according to the arrival pattern of the associated general message. The grouping of elements in FIGS. 9 and 10 is designated for design considerations and ease of connection, and is not necessarily in the order of function shown in FIG. 8. Continuous data manipulation may also be used. The logic of Figure 1D in implementing pattern recognition -
The storage elements basically follow the outline in FIG. However, specific requirements require some additions and allow some simplifications. In particular, since the star points sequentially emit general messages, no memory block is required to store identifiers. The module, on the other hand, will have to perform the following additional functions: (1) Recognize whether the general message is coded or not. (2) Recognize whether the photovoltaic cell is “on” or “off.” (3) Code or uncode the output summary message depending on whether the module is activated. (4) When the module is in an activated state and two uncoded general messages arrive at the same time, one response is sent. FIG. 11 shows a block diagram of a hexagonal K class module for pattern recognition. Each of the three input channels can contain 5 bits of information. That is, the enable bit E indicates the presence of a message, the response bit R indicates a response message or a general message, the uncoded bit U indicates whether the general message is already coded, and the two bit counts C0 and C1 indicates how many response messages there are in the input response. This means that if there are two responding modules on the same related track, their response return times (RRTs) will be the same, and as a result, the responses will converge on one module at the same time somewhere along the path to the star point. It is necessary to become. The module that collects the responses sends out only one response, so
It must be shown that the response it sends is representative of two responses. Do this with count bits. Two count bits are used to allow double responses, single responses, etc. to arrive simultaneously. Thus one response can represent up to four responses. If more is required, it can be achieved simply by adding additional count bits. All input signals, with the exception of the enable signal, are introduced through NOR gates P13-P17 so as to generate a signal whenever the corresponding input signal is present. The enable signals are routed in pairs to the NAND gates P1-P3 so that they generate a signal whenever two arrive at the same time.
If this happens, a signal of "2" will be produced at NAND P4, which will lead to directing gates P26-P
28 and is also used for counting. Direction gates P26-P28 implement the rules given in Table I for K-class modules. The outputs of gates P29-P31 pointing to the appropriate path are used for storage in latch P32. At gate P7 and flip-flop P8,
The inversion of the appropriate bit, ie the general message state, is coupled to the input phase of the clock (discussed a little later) and provides a signal at gate P9 that inhibits the generation of an alternative general message, thus accepting it following the first general message. Reject the general message sent. This output (all labeled send "SAL") is sent to P36-P38 to be stored as enable bits in latches P51 and P52.
Pass through the gate. SAL is also gated with the photovoltaic signal PC at P10, and the output of P10 is gated together to generate the uncoded signal bit _Uput . Thus, depending on whether the PC is on or off, or whether its module is activated or not, an appropriate general message is sent. U _put is P4
Latch P51, P via 0, P44 and P48
52. The last function of SAL is P2
9-activating latch P32 which stores the orientation (route) information created by P31. PC is related to one module6
It turns on when any one of the photocells is on. If the message is a response message, gate P14 generates R _put (R output);
R _put activates P33-P35 to load the response message into latches P51 and P52. At the same time, gates P18-P25 move the count bit to the appropriate latched position, or add up the number of responses if two responses arrive at the same time;
Send this as CO _put (CO output) to an appropriate latch position. Latches P51-P54 use two-phase clocks (designated ICLOCK and OCLOCK) to generate and enable signals to be sent out. On the first phase of the clock (ICLOCK), latches P51 and P52 are loaded by the input signal as described above. At the end of this phase, the signal is transferred to latch P5.
1 and P52 output terminals. The output phase (OCLOCK) begins immediately after the input phase. During this phase, the signal is loaded into output latches P53 and P54, and the signal is held in this latch for use in the adjacent module during the next power phase. The delayed response signal from gate P12 also passes through this path, causing a WAIT signal to be generated during the following input cycle. This wait signal is generated when the response condition is satisfied. That is, it is used to generate a response in the next cycle via the gate P14 and R output when the module is activated and two uncoded general messages arrive simultaneously. The invention is best utilized in conjunction with a small calculator that initiates a summary message from the six stars in sequence. The number of responses can be determined, and the average response return time can also be calculated.Then the circuit starts sending a summary message when the star point (corner) follows the signal from the computer, counts the responses, Determining the time taken for the response to arrive and passing the result through a small computer is shown. Again, this is for illustrative purposes only and other shapes are of course possible. Figure 12 shows a block diagram of such a circuit.The tip of the start pulse from the computer is
It must be synchronized to OCLOCK and is accepted by block 7A to generate the reset (Clear) signal. This signal is sent to counters 7C, 7
C' and adder 7D, and the general messages E', R', I', CI', and
OCLOCK in 7B to generate CO′
(These bits were previously discussed in connection with FIG. 11). In this way, the signal from the computer causes the transmission of a general message at the star point. Counters 7C and 7C' start with an OCLOCK pulse and begin counting clock (time) pulses. This provides a way to maintain continuity in time. The first response is input lines E, R, U, CI and CO
, the enable E, response R and uncoded U signals combine to cause adder 7D to add +1 to latches 7E' and 7E'' whose starting value is -1. The count is set to 0. This gating signal of E, R and U also stores the current clock count of 7C and 7C' in both latches 7E and 7E. As other messages arrive, the E, R and U bits are examined, and if they are response messages, they latch their counts CO and CI. ' and 7E'' and causes the current value of the clock (ie, time of arrival) to be stored in 7E. Latch 7E remains at its original time count since its clock signal has been disabled after the first response. Thus, when the arrival of responses is finished, the computer obtains the number of responses from 7E'', the arrival time of the first response message from 7E〓, and the time of the last response message from 7E.

[Brief explanation of the drawing]

FIGS. 1A-1G show block diagrams illustrating preferred types of storage-logic modules, cells or units that may be used in connection with the present invention. FIG. 2 shows a schematic diagram of a network arrangement using a number of modules, for example of the type shown in FIGS. 1B and D, interconnected and operative in accordance with the invention. Figure 3 shows the second type of module except that it is composed of modules of the type shown in Figure 1F.
Shows something similar to the figure. FIG. 4 shows something similar to FIG. 2, except that it is constructed of modules of the type indicated by D in FIG. Figures 5, 6 and 7 show network diagrams displaying the pattern recognition characteristics of the network. 8, 9 and 10 show block diagrams illustrating the logic and storage arrangement of the module of FIG. 1F used in FIG. FIG. 11 shows a schematic diagram of the logic and storage arrangement of the module of FIG. 1D used in the pattern recognition mode of FIGS. 5-7. 1st
FIG. 2 is a diagram of a module, such as that used in FIGS. 5-7, for injecting messages into the network and collecting responses therefrom.

Claims (1)

Claims: 1. A plurality of storage logic module units interconnected by cooperating input and output channels, and a light sensitive device connected to each of the module units, each of said module units has a logic unit that recognizes a general message and a response message received on its input channel, a memory that stores the identification name of the general message and the identification name of the input channel that first received the general message, and a memory that stores the identification name of the general message and the identification name of the input channel that first received the general message. a logic unit for transmitting the general message to all output channels when the general message is received; and said memory for storing a response message received on its input channel and in which of its input channels the corresponding general message was first received. a logic unit that transmits on a particular output channel according to the content of a pattern in a circuit network, the method comprising: applying a geometric pattern to a network to activate a photosensitive device; transmitting a plurality of general messages into the network from each of a plurality of modular units disposed around the network; transmitting, returning response messages to the general message from the module units connected to said actuated light sensitive device in the network, the number of those returned response messages for each general message, the response; A pattern recognition method comprising outputting the time interval between messages, the temporal order of response messages, and the average response return time.