JPS6240754A - Pin mounting structure of pin grid array - Google Patents

Pin mounting structure of pin grid array

Info

Publication number
JPS6240754A
JPS6240754A JP18090285A JP18090285A JPS6240754A JP S6240754 A JPS6240754 A JP S6240754A JP 18090285 A JP18090285 A JP 18090285A JP 18090285 A JP18090285 A JP 18090285A JP S6240754 A JPS6240754 A JP S6240754A
Authority
JP
Japan
Prior art keywords
pin
film substrate
wiring pattern
grid array
head
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18090285A
Other languages
Japanese (ja)
Other versions
JPH0553067B2 (en
Inventor
Akira Konishi
小西 昭
Teruo Wakano
輝男 若野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
I Pex Inc
Original Assignee
Dai Ichi Seiko Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Ichi Seiko Co Ltd filed Critical Dai Ichi Seiko Co Ltd
Priority to JP18090285A priority Critical patent/JPS6240754A/en
Priority to EP86108770A priority patent/EP0218796B1/en
Priority to DE8686108770T priority patent/DE3675321D1/en
Priority to US06/880,832 priority patent/US4823234A/en
Priority to KR1019860006161A priority patent/KR870002647A/en
Priority to CN198686105249A priority patent/CN86105249A/en
Publication of JPS6240754A publication Critical patent/JPS6240754A/en
Publication of JPH0553067B2 publication Critical patent/JPH0553067B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE:To reduce the thickness and cost of a pin grid array by interposing a film substrate and a wiring pattern between the step and the head the head of the stepped pin engaged within a through hole of the substrate. CONSTITUTION:A stepped pin 2 has a large-diameter portion 2a for forming a step near one end side, the one end side is engaged with a through hole 7 of a film substrate 1, and the one end side is then calked to form a head 2b. A metal ring 8, the substrate 1 and a wiring pattern 6 are interposed between the head 2b and the portion 2a to be secured to the substrate 1, and electrically connected with the pattern 6. Thus, a pin grid array of the substrate made of plastic film can be manufactured.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、ピングリッドアレイのピン取り付け構造、特
に薄肉のプラスチック製フィルム基板へのピンの取り付
け構造に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a structure for attaching pins to a pin grid array, and particularly to a structure for attaching pins to a thin plastic film substrate.

(従来の技術) 従来、半導体装置のパッケージとして、デュアルインラ
インパッケージ(以下、DIPという。)が大部分を占
めていたが、最近のLSIチップの高集積化や電子装置
の小型化、高性能化に対する要求の増大により装置のピ
ン数が増大するようになり、DTPではピン数の増加に
限界があるため、最近では、セラミック基板にピンを複
数列立設したピングIJツドアレイが開発され、実用に
供されてきている。
(Prior art) Traditionally, dual in-line packages (hereinafter referred to as DIPs) have been the most popular semiconductor device package, but recently, LSI chips have become more highly integrated, and electronic devices have become smaller and more sophisticated. The number of pins in devices has increased due to the increasing demand for devices, and since there is a limit to the increase in the number of pins in DTP, recently, a pin IJ array, which has multiple rows of pins on a ceramic substrate, has been developed and put into practical use. It has been provided.

(発明が解決しようとする問題点) しかしながら、従来のピングリッドアレイパッケージは
、セラミック製基板を採用しているため、コストが高く
、しかも基板を大きくすると共に、回路を微細化するこ
とは困難であるという問題がある。このため、プリント
配線基板技術を応用した比較的安価なプラスチック製の
ピングリッドアレイが開発されているが、製造工程での
管理を厳しくしなければ高精度のものが得られず、また
熱伝導を高めるため金属製放熱板を組み込むと、接合工
程や接合部の封止工程など製造工程が増加するなどの問
題がある他、セラミック基板を用いたものと同様、ピン
グリッドアレイの薄型化が困難であった。
(Problems to be solved by the invention) However, since conventional pin grid array packages use ceramic substrates, they are expensive, and it is difficult to increase the size of the substrate and miniaturize the circuits. There is a problem. For this reason, relatively inexpensive plastic pin grid arrays have been developed using printed wiring board technology, but high precision cannot be obtained without strict control during the manufacturing process. Incorporating a metal heat sink to increase the heat dissipation rate increases the number of manufacturing steps such as bonding and sealing of joints, and, like those using ceramic substrates, it is difficult to make the pin grid array thinner. there were.

本発明者は、前記問題を解決する手段として、開口部を
有し表面に配線パターンを形成されたフィルム基板と、
該フィルム基板に立設され前記配線パターンに接続され
た複数のピンと、前記フィルム基板の開口部を覆うよう
にフィルム基板上に配置された金属製放熱板とからなり
、前記フィルム基板を放熱板の周縁部及びピンと耐熱性
樹脂で封入成形して一体化してなることを特徴とするピ
ングリッドアレイを提案した。しかしなから、基板がグ
ラスチック製フィルムで形成されているため、フィルム
基板と配線パターンの接合強度が低い。それ故、パター
ンとピンをハンダ付してもその強度は向上しない。ハン
ダ付による面接合方法の場合はハンダ付加工が繁雑にな
り、又、加工後、洗浄工程ら必要となる。
As a means to solve the above problem, the present inventor has proposed a film substrate having an opening and having a wiring pattern formed on its surface;
It consists of a plurality of pins erected on the film substrate and connected to the wiring pattern, and a metal heat sink arranged on the film substrate so as to cover the opening of the film substrate, and the film substrate is connected to the heat sink. We proposed a pin grid array characterized by integrally molding the peripheral edge and pins with a heat-resistant resin. However, since the board is made of a glass film, the bonding strength between the film board and the wiring pattern is low. Therefore, soldering the pattern and pin does not improve its strength. In the case of surface bonding method using soldering, the soldering process is complicated and a cleaning process is required after the process.

(問題点を解決するための手段) 本発明は、前記問題を解決する手段として、表面に配線
パターンを形成されたフィルム基板と、該フィルム基板
及び配線パターンを貫通する各貫通孔にピンを嵌入固定
してなるピングリッドアレイにおいて、前記フィルム基
板の貫通孔に嵌入された段付きピンの段部と頭部とてフ
ィルム基板と配線パターンとを挾持させてなることを特
徴とするピングリッドアレイのピン取り付け構造を提供
するものである。
(Means for Solving the Problem) As a means for solving the problem, the present invention provides a film substrate having a wiring pattern formed on its surface, and a pin inserted into each through hole passing through the film substrate and the wiring pattern. In the fixed pin grid array, the stepped pin fitted into the through hole of the film substrate has a stepped portion and a head that sandwich the film substrate and the wiring pattern. This provides a pin attachment structure.

好ましい実施態様においては、フィルム基板の配線パタ
ーンと反対側の表面上に11通孔と同軸に金属リングを
形成し、該金属リングとフィルム基板及び配線パターン
とを前記貫通孔に嵌入された段付きピンの段部と頭部と
で挟持させることが行なイっれる。
In a preferred embodiment, a metal ring is formed coaxially with the 11 through holes on the surface of the film substrate opposite to the wiring pattern, and the metal ring, the film substrate, and the wiring pattern are connected to each other with a stepped ring fitted into the through hole. It is possible to clamp the pin between the stepped portion and the head.

(作用) 本発明は、フィルム基板と配線パターンとをフィルム基
板の貫通孔に嵌入された段付きピンの段部と頭部とで挾
持するようにピンの頭部をかしめることによりピンのフ
ィルム基板への取り付けとピンの配線パターンへの接続
を行うようにしたものである。また、フィルム基板の片
側表面に形成された配線パターンの反対側表面に貫通孔
と同軸に金属リングを形成することにより、該金属リン
グとフィルム基板および配線パターンとをピンで挾持さ
せた際の挟持力を向上さけるようにしたものである。ま
た、これによってプラスチック製フィルムを基板とする
ピングリッドアレイの製造を可能にするものである。
(Function) The present invention makes it possible to swage the film of the pin by caulking the head of the pin so that the film substrate and the wiring pattern are held between the step and the head of the stepped pin fitted into the through hole of the film substrate. It is designed to be attached to the board and connected to the pin wiring pattern. In addition, by forming a metal ring coaxially with the through hole on the opposite surface of the wiring pattern formed on one surface of the film substrate, the metal ring, the film substrate, and the wiring pattern can be held together with pins. It was designed to improve strength. Moreover, this makes it possible to manufacture a pin grid array using a plastic film as a substrate.

(実施例) 以下、本発明の実施例について添付の図面を参照して説
明する。
(Example) Hereinafter, an example of the present invention will be described with reference to the accompanying drawings.

本発明に係るピングリッドアレイの一実施例を示す図に
おいて、Iはポリイミド樹脂、エポキシ樹脂などのプラ
スデック材料からなるフィルム基板、2は良導電性金属
材料からなる段付きピン、3は銅又はアルミニウムなど
良熱伝導性金属材料からなる放熱板、4はフィルム基板
と、ピンと放熱板とを一体に封じ込める封止部で、ポリ
フェニレンザルファイド、エポキシ樹脂などの耐熱性樹
脂から形成されている。
In the diagram showing an embodiment of the pin grid array according to the present invention, I is a film substrate made of a plus deck material such as polyimide resin or epoxy resin, 2 is a stepped pin made of a highly conductive metal material, and 3 is a copper or The heat sink is made of a metal material with good thermal conductivity such as aluminum, and 4 is a sealing part that integrally seals the film substrate, the pins, and the heat sink, and is made of a heat-resistant resin such as polyphenylene sulfide or epoxy resin.

フィルム基板1は、その中央部に開口部5を有し、その
表面には、第3図に示すように、開口部5の近傍から放
射状に伸張した配線パターン6が形成され、該配線パタ
ーン6及びフィルム基板1を貫通して複数の貫通孔7が
形成されている。フィルム基板I上の配線パターン6は
、貫通孔7と同軸にリング部6aが形成されていて、フ
ィルム基板lの配線パターン6と反対側の表面上には、
貫通孔7と同軸に、かつ配線パターン6のリング部6a
と同形状の金属リング8が形成されている。
The film substrate 1 has an opening 5 in its center, and a wiring pattern 6 extending radially from the vicinity of the opening 5 is formed on its surface, as shown in FIG. A plurality of through holes 7 are formed through the film substrate 1 . The wiring pattern 6 on the film substrate I has a ring portion 6a formed coaxially with the through hole 7, and on the surface of the film substrate I opposite to the wiring pattern 6,
Ring portion 6a of wiring pattern 6 coaxially with through hole 7
A metal ring 8 having the same shape is formed.

段付きピン2は、一端側近傍に段部を形成する大径部2
aを有し、一端側をフィルム基板1の貫通孔7に嵌入し
た後、その一端側をかしめて頭部2bを形成させ、その
頭部2bと大径部2aとの間に金属リング8、フィルム
基板!及び配線パターン6を挟持させることによりフィ
ルム基板lに固定されると共に、配線パターン6に電気
的に接続されている。
The stepped pin 2 has a large diameter portion 2 that forms a stepped portion near one end.
a, and after fitting one end side into the through hole 7 of the film substrate 1, the one end side is caulked to form a head 2b, and between the head 2b and the large diameter part 2a, a metal ring 8, Film substrate! By sandwiching the wiring pattern 6, it is fixed to the film substrate l and is electrically connected to the wiring pattern 6.

放熱板3はフィルム基板lの開口部5に面する側に該開
口N5とほぼ同面積の凹所9が形成されろ一方、周縁部
3aに突起IOが形成され、周縁部3aをフィルム基板
l及びピン2と耐熱性樹脂で封入成彩することによりフ
ィルム基板■及びピン2と一体化されている。なお、1
1はスタンドオフで、ピングリッドアレイをピンソケッ
トやマザー基板等に装着した際、マザー基板等との間に
一定の間隔をあけるためのもので、ピングリッドアレイ
の4つの角部にそれぞれ封止部4と一体成形されている
。なお、スタンドオフ11はフィルム基板の角部に限ら
ず任意の位置に形成することができる。また、封止部4
にはピン2の頭部2bに達する穴12が形成されている
が、この穴12は封入成形時にピン2を抑圧固定する可
動ピン19により形成される。20は放熱板3と封止部
4との接合部から水分が侵入するのを防止するための防
湿用保護皮膜である。
The heat dissipation plate 3 has a recess 9 having approximately the same area as the opening N5 on the side facing the opening 5 of the film substrate l, and a protrusion IO formed on the peripheral edge 3a, so that the peripheral edge 3a is connected to the film substrate l. The pin 2 is sealed with a heat-resistant resin and is integrated with the film substrate (2) and the pin 2. In addition, 1
1 is a standoff, which is used to leave a certain distance between the pin grid array and the mother board when it is attached to a pin socket, mother board, etc., and is sealed at each of the four corners of the pin grid array. It is integrally molded with part 4. Note that the standoffs 11 can be formed not only at the corners of the film substrate but also at any arbitrary position. In addition, the sealing part 4
A hole 12 reaching the head 2b of the pin 2 is formed in the hole 12, and this hole 12 is formed by a movable pin 19 that presses and fixes the pin 2 during encapsulation molding. Reference numeral 20 denotes a moisture-proof protective film for preventing moisture from entering through the joint between the heat sink 3 and the sealing portion 4.

前記構造のピングリッドアレイは次のようにして製造で
きる。即ち、フィルム基板lのベースフィルムの両面に
銅箔を積層し、該銅箔の表面上にフォトレジストを塗布
して乾燥させ、一方の表面に配線パターンを、反対側の
表面に貫通孔7を形成すべき位置に対応する金属リング
のパターンをそれぞれ露光した後、公知方法によりエツ
チングして配線パターン6と金属リング8とを形成ずろ
The pin grid array having the above structure can be manufactured as follows. That is, copper foil is laminated on both sides of the base film of the film substrate l, a photoresist is applied on the surface of the copper foil and dried, and a wiring pattern is formed on one surface and a through hole 7 is formed on the opposite surface. After each metal ring pattern corresponding to the position to be formed is exposed, etching is performed by a known method to form the wiring pattern 6 and the metal ring 8.

次いで、フォトレノストを溶解、除去した後、電気メツ
キ法により配線パターン6北にニッケルメッキを下地と
して金メッキを積層し、さらに貫通孔の形成及び所定寸
法への穿設切断加工を施すことにより製造できる。
Next, after dissolving and removing the photorenost, gold plating is laminated on the north side of the wiring pattern 6 using nickel plating as a base by electroplating, and through-holes are formed and punched and cut to a predetermined size.

なお、この実施例では、銅箔をエツチングして形成され
た配線パターンの上にニッケルメッキ及び金メッキを積
層しているが、必ずしもその必要は無く、配線パターン
を銀メッキその池の耐食性、良導電性金属メッキで形成
してら良い。
In this example, nickel plating and gold plating are laminated on the wiring pattern formed by etching the copper foil, but it is not necessary to do so. It would be better if it was formed with metallic metal plating.

また、フィルム基板lの製造方法として次の方法を採用
してム良い。即ち、ベースフィルムにスリット加工を施
し、脱脂、乾燥後、化学銅メッキの付着を容易にするた
めベースフィルムの両表面に触媒ペーストを塗布し、乾
燥させた後、スタンピング加工し、配線パターン6及び
金属リング8を形成すべき部位以外の部位にレジストイ
ンキをスクリーン印刷してマスキングし、次いで化学銅
メッキ法により銅メッキを施すことにより金属リング8
と配線パターン6の下地を形成し、配線パターン6の下
地となる銅メッキーヒに電気銅メッキ、電気銀メッキを
積層して配線パターンを完成させる方法である。この場
合、配線パターン6の表面トレシストインキ層の表面と
を同一レベルに形成できるので、表面に凹凸の無い平滑
なフィルム基板とすることができ、封入成形時にパリが
形成されることが無い。
Further, the following method may be adopted as a method for manufacturing the film substrate 1. That is, the base film is slitted, degreased, and dried. Catalyst paste is applied to both surfaces of the base film to facilitate attachment of chemical copper plating. After drying, stamping is performed to form wiring patterns 6 and The metal ring 8 is formed by masking the areas other than the area where the metal ring 8 is to be formed by screen printing resist ink, and then applying copper plating using a chemical copper plating method.
In this method, the base of the wiring pattern 6 is formed, and the copper plating serving as the base of the wiring pattern 6 is laminated with electrolytic copper plating and electrolytic silver plating to complete the wiring pattern. In this case, since the surface of the wiring pattern 6 can be formed on the same level as the surface of the trace resist ink layer, a smooth film substrate with no irregularities on the surface can be obtained, and no flakes are formed during encapsulation molding.

前記フィルム基板1にピンを取り付けるには、予め用意
した段付きのピン2をフィルム基板1の貫通孔7にピン
2が嵌入し、ピン2の頭部2bとなる端部を振動あるい
はハンマーリングによりかしめれば良い。これにより、
ピン2の頭部2bと大径部2aとの間に金属リング8、
フィルム基板!及び配線パターン6が挟持させ、ピン2
がフィルム基板lに固定されると共に、配線パターン6
に電気的に接続される。
To attach a pin to the film substrate 1, a stepped pin 2 prepared in advance is inserted into the through hole 7 of the film substrate 1, and the end of the pin 2, which will become the head 2b, is vibrated or hammered. Just caulk it. This results in
A metal ring 8 is provided between the head 2b of the pin 2 and the large diameter portion 2a.
Film substrate! and the wiring pattern 6 is sandwiched, and the pin 2
is fixed to the film substrate l, and the wiring pattern 6
electrically connected to.

その後、第4図に示すように、下型15のキャビティI
7内に配置し、フィルム基板!の開口部を覆うように放
熱板3をセットし、上型18を降下させて型閉めし、耐
熱性樹脂をキャビティ17に射出して封入成形し、次い
で、放熱板3が露出している側の表面にエポキシ系ある
いはポリイミド系樹脂をコーティングすることにより、
第1図に示す構造のピングリッドアレイを製造できる。
After that, as shown in FIG. 4, the cavity I of the lower mold 15 is
Placed in 7, film substrate! The heat dissipation plate 3 is set so as to cover the opening of the heat dissipation plate 3, the upper mold 18 is lowered and the mold is closed, a heat-resistant resin is injected into the cavity 17 and sealed, and then the side where the heat dissipation plate 3 is exposed is closed. By coating the surface with epoxy or polyimide resin,
A pin grid array having the structure shown in FIG. 1 can be manufactured.

なお、ピンの形状としては、必ずしも段を一重とする必
要はなく、第5図に示すように、段を二重以上設け、二
つの段部間の空間に耐熱性樹脂がまわり込むようにし、
ピンの引抜力を向上させるようにしてもよい。
Note that the shape of the pin does not necessarily have to be one step, but as shown in Figure 5, two or more steps are provided so that the heat-resistant resin wraps around the space between the two steps.
The pulling force of the pin may be improved.

(発明の効果) 以上の説明から明らかなように、本発明によれば、基板
の配線パターンと反対側の表面に金属すングを形成し、
ピンをかしめる際に貫通孔を形成するベースフィルムの
変形が防止され、挟持不能となる事態が発生ずることが
ないので、薄肉のフィルム基板を使用し、該フィルム基
板をピン及び放熱板と一体に封入成形でき、ピングリッ
ドアレイの薄型化及び低コスト化を図ることができ、し
かも50μm程度の高寸法精度で信頼性の高いピングリ
ッドアレイを製造できる。
(Effects of the Invention) As is clear from the above description, according to the present invention, a metal ring is formed on the surface of the substrate opposite to the wiring pattern,
When the pin is caulked, the base film that forms the through hole is prevented from deforming, and a situation where the pin cannot be held is prevented. Therefore, a thin film substrate is used, and the film substrate is integrated with the pin and the heat sink. The pin grid array can be encapsulated and molded, the pin grid array can be made thinner and lower in cost, and moreover, the pin grid array can be manufactured with high dimensional accuracy of about 50 μm and high reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係るピングリッドアレイの断面図、第
2図はその部分拡大断面図、第3図は第1図のピングリ
ッドアレイの製造に使用するフィルム基板の平面図、第
4図は第1図のピングリッドアレイの製造過程における
封入成形時の金型の要部断面図、第5図は本発明の変形
例を示すピングリッドアレイの要部断面図である。 1〜フイルム基板、2〜ピン、3〜放熱板、3a〜放熱
板の周縁部、4〜耐熱性樹脂、5〜開口部、6〜配線パ
ターン、7〜貫通孔、8〜金属リング、lO〜突起。 wstai) 第2図 第4図 第5図
FIG. 1 is a sectional view of a pin grid array according to the present invention, FIG. 2 is a partially enlarged sectional view thereof, FIG. 3 is a plan view of a film substrate used for manufacturing the pin grid array of FIG. 1, and FIG. 1 is a sectional view of a main part of a mold during encapsulation molding in the manufacturing process of the pin grid array shown in FIG. 1, and FIG. 5 is a sectional view of a main part of a pin grid array showing a modification of the present invention. 1-film substrate, 2-pin, 3-heat sink, 3a-periphery of heat sink, 4-heat-resistant resin, 5-opening, 6-wiring pattern, 7-through hole, 8-metal ring, lO- protrusion. wstai) Figure 2 Figure 4 Figure 5

Claims (2)

【特許請求の範囲】[Claims] (1)表面に配線パターンを形成されたフィルム基板と
、該フィルム基板及び配線パターンを貫通する各貫通孔
にピンを嵌入固定してなるピングリッドアレイにおいて
、前記フイルム基板の貫通孔に嵌入された段付きピンの
段部と頭部とでフィルム基板と配線パターンとを挾持さ
せてなることを特徴とするピングリッドアレイのピン取
り付け構造。
(1) In a pin grid array consisting of a film substrate with a wiring pattern formed on its surface, and pins inserted and fixed in through holes penetrating the film substrate and the wiring pattern, the pins are inserted into the through holes of the film substrate. A pin mounting structure for a pin grid array, characterized in that a film substrate and a wiring pattern are held between a step portion and a head of a stepped pin.
(2)フィルム基板の配線パターンと反対側の表面上に
貫通孔と同軸に金属リングを形成し、該金属リングとフ
ィルム基板及び配線パターンとを前記貫通孔に嵌入され
た段付きピンの段部と頭部とで挾持させてなる特許請求
の範囲第1項記載のピングリッドアレイのピン取り付け
構造。
(2) A metal ring is formed coaxially with the through hole on the surface of the film substrate opposite to the wiring pattern, and the metal ring, the film substrate, and the wiring pattern are connected to the stepped portion of the stepped pin fitted into the through hole. A pin mounting structure for a pin grid array according to claim 1, wherein the pin grid array is held between a head and a head.
JP18090285A 1985-08-16 1985-08-16 Pin mounting structure of pin grid array Granted JPS6240754A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP18090285A JPS6240754A (en) 1985-08-16 1985-08-16 Pin mounting structure of pin grid array
EP86108770A EP0218796B1 (en) 1985-08-16 1986-06-27 Semiconductor device comprising a plug-in-type package
DE8686108770T DE3675321D1 (en) 1985-08-16 1986-06-27 SEMICONDUCTOR ARRANGEMENT WITH PACK OF PIN PLUG TYPE.
US06/880,832 US4823234A (en) 1985-08-16 1986-07-01 Semiconductor device and its manufacture
KR1019860006161A KR870002647A (en) 1985-08-16 1986-07-28 Semiconductor device and manufacturing method
CN198686105249A CN86105249A (en) 1985-08-16 1986-08-16 Semiconductor device and manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18090285A JPS6240754A (en) 1985-08-16 1985-08-16 Pin mounting structure of pin grid array

Publications (2)

Publication Number Publication Date
JPS6240754A true JPS6240754A (en) 1987-02-21
JPH0553067B2 JPH0553067B2 (en) 1993-08-09

Family

ID=16091304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18090285A Granted JPS6240754A (en) 1985-08-16 1985-08-16 Pin mounting structure of pin grid array

Country Status (1)

Country Link
JP (1) JPS6240754A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63213364A (en) * 1987-02-27 1988-09-06 Ibiden Co Ltd Semiconductor mounting board
US5485039A (en) * 1991-12-27 1996-01-16 Hitachi, Ltd. Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a second main surface
JP2008130344A (en) * 2006-11-20 2008-06-05 Matsushita Electric Ind Co Ltd Fluorescent lamp

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63213364A (en) * 1987-02-27 1988-09-06 Ibiden Co Ltd Semiconductor mounting board
US5485039A (en) * 1991-12-27 1996-01-16 Hitachi, Ltd. Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a second main surface
JP2008130344A (en) * 2006-11-20 2008-06-05 Matsushita Electric Ind Co Ltd Fluorescent lamp

Also Published As

Publication number Publication date
JPH0553067B2 (en) 1993-08-09

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