JPS6240458Y2 - - Google Patents
Info
- Publication number
- JPS6240458Y2 JPS6240458Y2 JP1980157604U JP15760480U JPS6240458Y2 JP S6240458 Y2 JPS6240458 Y2 JP S6240458Y2 JP 1980157604 U JP1980157604 U JP 1980157604U JP 15760480 U JP15760480 U JP 15760480U JP S6240458 Y2 JPS6240458 Y2 JP S6240458Y2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- etching
- conductor
- check
- check mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 claims description 24
- 239000004020 conductor Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 230000001154 acute effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- BFNBIHQBYMNNAN-UHFFFAOYSA-N ammonium sulfate Chemical compound N.N.OS(O)(=O)=O BFNBIHQBYMNNAN-UHFFFAOYSA-N 0.000 description 1
- 229910052921 ammonium sulfate Inorganic materials 0.000 description 1
- 235000011130 ammonium sulphate Nutrition 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Landscapes
- ing And Chemical Polishing (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
【考案の詳細な説明】
本考案はプリント板に関し、特に導体パターン
のエツチング状態を容易にチエツクできるプリン
ト板を提案するものである。[Detailed Description of the Invention] The present invention relates to a printed board, and in particular, proposes a printed board in which the etched state of a conductive pattern can be easily checked.
一般にプリント板を使用して回路を構成する場
合、例えば高周波回路の印刷コイルの電源或いは
高圧回路を構成する導体パターンは、パターン幅
やパターン間隔に充分な精度が要求されるため、
導体パターンのエツチングが正確に行なわれてい
るか否かをチエツクする必要がある。特に機器の
小型化、集積化等によつて小さい基板上に多数の
回路が形成されるようになつて来ると、治具等を
使用してエツチングの仕上り状態を入念にチエツ
クしなければならず、その作業は非常に能率の悪
いものであつた。 Generally, when configuring a circuit using a printed board, for example, the conductor patterns configuring the power supply of a printed coil of a high frequency circuit or a high voltage circuit require sufficient precision in pattern width and pattern spacing.
It is necessary to check whether the conductor pattern is etched accurately. In particular, as a large number of circuits are formed on small substrates due to the miniaturization and integration of equipment, it is necessary to carefully check the finished state of etching using jigs, etc. The work was extremely inefficient.
そこで、本考案は斯かる点を改善すべくなされ
たものであり、以下、その詳細を図面を参照して
説明する。 Therefore, the present invention has been devised to improve these points, and the details thereof will be explained below with reference to the drawings.
第1図は本考案によるプリント板の一実施例を
示しており、1は基板、2はその基板上に形成さ
れた導体パターン、3はこのパターンのエツチン
グ状態をチエツクするために設けられたチエツク
マークである。 FIG. 1 shows an embodiment of a printed board according to the present invention, where 1 is a substrate, 2 is a conductor pattern formed on the substrate, and 3 is a checker provided to check the etching condition of this pattern. It's a mark.
前記チエツクマーク3は、エツチング状態をチ
エツクすべきパターンの適当な個所にパターンの
形成時と同時に設けられるものであり、第2図a
のようにパターン2の外側に同一の導体材料で形
成されるか、或いは第2図bのようにパターン2
内部の導体欠除部として形成される。即ち、プリ
ント板の母材である銅張積層板上に前記導体パタ
ーン2及びチエツクマーク3に相当する形状をエ
ポキシアクリレート系のエツチングレジストを印
刷して形成し、そのレジストを紫外線により硬化
させたのち硫酸アンモニウム等の溶液に浸漬する
ことによつて上記レジストが施されていない部分
の銅をエツチングして除去し、その後、アルカリ
性溶液に浸漬して上記パターン2等の上のエチン
グレジストを除去することによつて形成される訳
である。その際、上記チエツクマーク3はエツチ
ングが正確に行なわれた場合にその三角マークの
先端が導体パターン2の縁部に接するように、前
記エツチングレジストによるパターン及びチエツ
クマークの印刷が正確に行なわれる。 The check mark 3 is provided at an appropriate location of the pattern whose etching condition is to be checked at the same time as the pattern is formed, as shown in FIG. 2a.
It is formed of the same conductive material on the outside of pattern 2, as shown in FIG.
Formed as an internal conductor cutout. That is, shapes corresponding to the conductor patterns 2 and check marks 3 are formed by printing an epoxy acrylate-based etching resist on a copper-clad laminate, which is the base material of the printed board, and after curing the resist with ultraviolet rays. Etching and removing the copper in the areas where the resist is not applied by immersing it in a solution such as ammonium sulfate, and then removing the etching resist on the pattern 2, etc. by immersing it in an alkaline solution. It is formed by At this time, the pattern and check mark are printed accurately using the etching resist so that the tip of the triangular mark comes into contact with the edge of the conductor pattern 2 when etching is performed accurately.
したがつて、第1図の基板1上に導体パターン
2を形成する際にパターン以外の導体部分を除去
するエツチング工程に於いて、エツチング時間の
不足等によりエツチングが充分に行なわれなかつ
た場合は、チエツクマーク3の形状が大きくなつ
て導体パターン2への連接部分が増大(第3図a
の場合)するか、或いは、チエツクマーク3の形
状が小さくなつて導体パターン2の縁部から離れ
る(第3図bの場合)ことになる。また、エツチ
ング過多の場合には、第4図a,bに示すように
上記と全く逆の状態になる。このため、エツチン
グ後或いはプリント板の完成状態に於いて、上記
チエツクマーク3をチエツクすれば、エツチング
の仕上がり状態即ち導体パターン2が所定の幅に
エツチングされているか否かを容易に確認できる
ことになる。 Therefore, in the etching process for removing conductor parts other than the pattern when forming the conductor pattern 2 on the substrate 1 shown in FIG. 1, if etching is not performed sufficiently due to insufficient etching time, etc. , the shape of the check mark 3 becomes larger and the connecting part to the conductor pattern 2 increases (Fig. 3a).
(in the case of FIG. 3b), or the shape of the check mark 3 becomes smaller and moves away from the edge of the conductor pattern 2 (in the case of FIG. 3b). Furthermore, in the case of excessive etching, the situation is completely opposite to that described above, as shown in FIGS. 4a and 4b. Therefore, by checking the check mark 3 after etching or when the printed board is completed, it is possible to easily check the finished state of the etching, that is, whether the conductor pattern 2 has been etched to a predetermined width. .
ところで、上記チエツクマーク3は導体パター
ン2の幅またはパターン間隔をチエツクすべき個
所に設ければよい訳であるが、エツチングの進み
具合は方向によつて異なるので、第5図a,bに
示すように1個所について縦横二方向にチエツク
マークを設ければよい。また、プリント板上の導
体パターン全体をチエツクする必要がある場合に
は、上記二方向のチエツクマークを一組として複
数組設ければよい。 The above check marks 3 may be provided at locations where the width or spacing of the conductor patterns 2 should be checked, but since the progress of etching differs depending on the direction, it is sufficient to provide check marks in two directions, vertical and horizontal, at one location, as shown in Figures 5a and 5b. Also, when it is necessary to check the entire conductor patterns on the printed board, it is sufficient to provide multiple sets of check marks in the two directions.
本考案のプリント板は以上の如く構成されたも
のであるから、プリント板製造時のエツチング工
程後或いはプリント板完成後に於いて、導体パタ
ーンが所定の幅又は間隔になつているが否かをチ
エツクマークの目視によつて非常に簡単にチエツ
クできるので、検査能率が大幅に向上することに
なる。また、上記チエツクマークは導体パターン
と同時に形成されるものであるから、チエツクマ
ークを施すために別個の工程を必要とせず、従つ
て、製造コストが増大することもない。しかも、
チエツクマークはその先端と導体パターン縁部と
の接離状態によつてエツチング状態を検査するも
のであるから、チエツクマークを設けるために大
きなスペースを必要とせず、従つて、エツチング
状態を厳しく管理しなければならないパターン幅
やパターン間隔の狭い部分にも設けることができ
る。 Since the printed board of the present invention is constructed as described above, it is possible to check whether the conductor patterns have a predetermined width or spacing after the etching process during printed board manufacturing or after the printed board is completed. Since the marks can be checked very easily by visual inspection, inspection efficiency is greatly improved. Furthermore, since the check mark is formed simultaneously with the conductor pattern, no separate process is required to form the check mark, and therefore, manufacturing costs do not increase. Moreover,
Since the check mark is used to inspect the etching state by checking the contact and separation between the tip and the edge of the conductor pattern, it does not require a large space to provide the check mark, and therefore the etching state can be strictly controlled. It can also be provided in areas where the pattern width or pattern spacing is narrow.
第1図は本考案を実施したプリント板を一部省
略して示す平面図、第2図a,bは上記プリント
板のエツチング状態が正常な場合を、第3図a,
bはエツチング不足の場合を、第4図a,bはエ
ツチング過多の場合をそれぞれ示す部分拡大図、
第5図a,bはチエツクマークの具体的な実施態
様を示す部分拡大図である。
2……導体パターン、3……チエツクマーク。
FIG. 1 is a partially omitted plan view of a printed board embodying the present invention, FIGS. 2 a and b show the printed board in a normal etched state, and FIGS.
b is a partial enlarged view showing the case of insufficient etching, and FIGS. 4a and b are partially enlarged views showing the case of excessive etching,
FIGS. 5a and 5b are partially enlarged views showing a specific embodiment of the check mark. 2...Conductor pattern, 3...Check mark.
Claims (1)
先端を有するチエツクマークのその先端が正規の
エツチング状態の場合に上記パターンの縁部に実
質的に点接触するように、上記チエツクマークを
導体パターンと同一材料で該パターンの外側に形
成するか、導体パターン内部に導体欠除部として
形成し、このチエツクマークと上記パターンの接
離度合によつてエツチング状態をチエツクできる
ようにしたプリント板。 The check mark is made of the same material as the conductor pattern, such that the tip of the check mark having an acute tip indicating the etching condition of the conductor pattern is in substantial point contact with the edge of the pattern in the normal etching condition. A printed board in which the etching condition is formed on the outside of the pattern or as a conductor cutout inside the conductor pattern, and the etching condition can be checked by the degree of contact and separation between the check mark and the pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1980157604U JPS6240458Y2 (en) | 1980-11-04 | 1980-11-04 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1980157604U JPS6240458Y2 (en) | 1980-11-04 | 1980-11-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5780865U JPS5780865U (en) | 1982-05-19 |
JPS6240458Y2 true JPS6240458Y2 (en) | 1987-10-16 |
Family
ID=29516711
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1980157604U Expired JPS6240458Y2 (en) | 1980-11-04 | 1980-11-04 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6240458Y2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0694393B2 (en) * | 1985-11-25 | 1994-11-24 | 株式会社東芝 | Ceramic body |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS519684A (en) * | 1974-07-15 | 1976-01-26 | Nippon Electric Co | Handotai sochi no seizo hoho |
-
1980
- 1980-11-04 JP JP1980157604U patent/JPS6240458Y2/ja not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS519684A (en) * | 1974-07-15 | 1976-01-26 | Nippon Electric Co | Handotai sochi no seizo hoho |
Also Published As
Publication number | Publication date |
---|---|
JPS5780865U (en) | 1982-05-19 |
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