JPS6234195A - Automatic phase detection circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a video signal necessary for connecting a video signal outputted from a personal computer or a word processor to a digital peripheral output device for operating a display CRT'i. This invention relates to an automatic phase detection circuit between video data and a dot clock in a video signal interface.

[Summary of the invention]

The present invention connects to a digital peripheral output device such as a flood panel display or a video fist printer, which has a different display drive method from the video signal 'IcRT output from OA equipment such as a personal Φ computer or word processor for a display CRT. The video signal interface required for this purpose has a 5% delay relationship and uses a delay circuit E'x that has multiple tap outputs.

When video data is input, the phase relationship between the video data and the dot clock is automatically determined, and the video data is input to the serial/parallel conversion circuit with an optimal timing relationship.

[Prior art]

Conventional National Technical Repo
rt Vo131No2 Apr 1985 p6
As described in Section 2, when adjusting the phase of video data and dot clock, the user connects the host system and peripheral system and determines whether the dot clock is rising or falling, whichever works better. It has been known to select the polarity of the resulting clock phase.

[Problems to be solved by the present invention]

Since the video signals sent out from host systems such as Shikashi and Burnal Computers are based on devices that operate analogously, such as CRTs, they are formatted in a standardized format down to the details required by digital devices. However, there were the following problems. For this reason, users of digital peripheral systems have to read the manual and select the polarity and adjust the phase of the dot clock every time they change the host system or peripheral system in use. had.

a) There is no dot clock in the composite video signal. Therefore, as shown in FIG. 6, the horizontal synchronization component of the video signal is input.

It is necessary to modify the video signal interface 1020 PLL (phase lock loop) circuit to fully regenerate the dot clock. However, even if the frequency of the dot clock can be reproduced electronically.

Even the phase relation with the video data could not be reproduced, and flicker sometimes appeared in the image.

b) In the separate video signal, the dot clock is supplied, but due to the polarity of the dot clock, the difference is c9".The phase relationship between the video data and the dot clock is different on the host system side. Furthermore, on the video signal interface side, the 1-phase relationship tends to deteriorate due to the effects of connection couples and input buffers, and even products of the same model may not be able to adjust the phase uniformly. .

Therefore, in order to solve these conventional problems, the present invention automatically adjusts the phase of video data and dot clock to the optimum phase, regardless of the phase relationship, and eliminates flicker and distortion in a single image. No money is aimed at getting a video signal interface.

[Means for solving problems]

In order to solve the above problems, the automatic phase detection circuit of the present invention is characterized by having the following configuration.

a) Delay means for converting video data input into a plurality of signals with the same pulse width and phase differences; b) a first latch circuit that simultaneously latches the plurality of phase signals using a dot clock; and C) the first latch circuit. d) A second latch circuit that holds the output of the dot clock for a time period much longer than the dot clock cycle; Means for selecting from among the phase difference signals [Operation] The automatic phase detection circuit configured as described above has video data that is digitally processed and has a regularity of nine Hals width, and a dot clock. When you type.

Since the phase relationship of video data and video data with respect to the dot clock is measured digitally with an accuracy determined by the resolution of the delay circuit, it is possible to easily select video data that has the optimal phase relationship with the dot clock based on this digital information. .

〔Example〕

Embodiments of the present invention will be described below based on the drawings. FIG. 3 is a diagram showing where the self-m phase detection circuit of the present invention is located in the entire system. In the figure, host system 101j-7,.

This is an information processing device that uses a display CRT 105 such as a burner computer or a word processor as a display device. Host system IQ1, C! RT10
In order to operate 5i, a CRT controller is used to generate commonly known synchronization signals (H-8YNC, V-8YNC
It then sends out video data (video signal) 101A. When performing gradation display, a luminance signal is added. On the other hand, the dot clock is 1 dot 1 of all video data displayed.
The dot clock is used as a basic clock in the Honuto system to correspond to the CRT10.
No fL is supplied to 5. Thus at video signal interface 102.

It is necessary to reproduce the dot clock 102A'ii by a PLL circuit which inputs the synchronization signal H-E+YNO. In addition, the synchronization signal is generated by a synchronization separation circuit.

Separated into TTI and level signals, interface 1
02 must be entered.

On the other hand, if 0RT105 has a color display.

Generally the video signal 101Al'! - A dot clock for preventing color shift is supplied from the host system 101, so the interface 10
There is no need to reproduce the dot clock in 2.

Now, the video signal interface 102 [.

Signals for analog processing systems such as CRTs.

Frame buffer using MO8 type semiconductor memory
A device that converts the memo 9103 and the microcomputer into a ratio signal suitable for a digital processing system such as a peripheral circuit such as a DMA (direct memory access) controller or a line-sequential drive type flat panel display. It is. For this reason, the inside of the video signal interface is broadly divided into an input system and an output system. The input system is a CR that raster scans using sawtooth p waves when a video signal is input.
A circuit is required to solve a problem that did not arise in the T. One of them is the automatic phase detection circuit of the present invention. Digital processing system.

Since all parallel data processing is generally performed, the phase relationship between the video data and the dot clock in the circuit that converts all serial video data into parallel φ data is important. In other words, if the change timing of the dot clock, which is the basic operating clock of the interface 102, and the change timing of video data are close to each other, power fluctuations and noise may occur.

A phenomenon occurs in which video data that should be converted at a predetermined timing is shifted to the previous or next timing. Although this phenomenon does not pose a problem in a CRT that performs analog processing, in the one peripheral system 104, it is clearly recognized as a one-dot shift. This phenomenon can be digitally prevented by adding an automatic phase detection circuit of the present invention between all video data and the serial/parallel converter 7 shown in FIG.

Now, in FIG. 1, a waveform shaping circuit 1 composed of an inverter and an AND circuit removes spike-like noise caused by ringing and external noise from video data VDATA, and outputs a signal vo.

Delay circuits 2, 3, 4Vi, the signal V+ which has the same polarity but one phase difference from the signal '7o shown in FIG.
+Vs +Vs 't'' occurs.Delay circuit 2
, 3°4 are shown as using inverters in the first example, but any circuit that can obtain a constant delay time of 1% may be used. Signal ■O+ ■I TV t
+ vs is 10 flip-flops equivalent to 1,874
It is connected to the input of a 4-bit latch 9 consisting of. The waveform shaping circuit 11 shapes the waveform of the dot clock DCLOOK and outputs a clock 9A, which is inputted to the clock input cKKfifi of the latch 9. Launch 9 is a signal 2 at the rising edge timing of clock 9A.

,V,,V,.

The digital state of vS is held at the output Q until the rising edge of the secondary clock 9A. Lunch 904 Pit output Qil
'1. The signal is input to a 4-bit latch 16 made up of a flip-flop 10 equivalent to LS74. Since the clock input to the latch 16 is the signal V3k, which is inverted by the inverter 5, the input signal is output to the output Q at a timing that is slightly delayed by nine edges from the rise of the signal v3.

The latch 13 is a circuit for updating only when the video data VDATA falls. That is, this is because the phase with the dot clock is determined only when there is video data. Lunch 1304 bit output is
This corresponds to phase mk encoding of video data and dot clock. In the timing example in Figure 2, vO+V at the timing indicated by the arrow of dot clock 9A.
l *■2. The state of v3 becomes the output of latch 16.

Signal 6A is video data determined to have optimal timing. For example, in timing example (A), latch 13
The output is:

(v31 v21 Vl + VO) = (1+ 0
+010), and signal 6A is Vo.

In FIG. 2, one period of the dot clock 9A corresponds to one dot of the peripheral device.

In FIG. 2, as an example, there is a case where the dot clock 9A rises in the middle of the video data sequence (81!). Pictured as the ideal timing, p-(A) is the ideal state.

CB) shows the case when the dot clock is fast, and (C) shows the case when the dot clock is slow. Also, in order to distinguish between the timing side (A) and (0) as shown in the figure, the signal ■
. The phase difference between the dot clock 9 and v3 is required to be at least half a period relative to the dot clock 9. Also, the signal vo I Vl + ■2 H
The number of bits of Vl (it should be determined by comparing the switching speed of the transistors that make up the video interface and the frequency of the dot clock, and is selected from a value of 2 dots or more. By the way, the dot clock frequency is 640 x 200 dots) For.

For an image of 14.3 MJ (Z, 640×4 [10 dots), 21 Ml1z is a commonly used value.

Now, block 14!・This is a statistical processing circuit for i-phase determination results. The encoded output Q of latch 16 is connected to the input of latch 21. The latch 21 has an output Q)
The reason for this is that noise that cannot be removed by the waveform shaping circuits 1 and 11 is processed. So, latch 1
This is to prevent an abnormal condition such as flicker from occurring in the peripheral output device by immediately feeding it back when the output of No. 3 is changed. The decoder 26 decodes the output Qt of the latch 21 to generate an optimal phase video data selection signal 23B and a second order video data selection signal 23.
0 and a non-existing code detection signal 23Ai is output. signal 23
B controls the selector 6 and selects the video data VO, Vl.
, Vz.

■ Output all selections from 3. Output 6 of selector 6
A is connected to data input A of a serial-to-parallel converter 7 equivalent to LS164. -Kadot clock 9A [
, is provided with a delay equivalent to that of the selector 6 by means of a delay circuit 12, and is connected to the clock input C of the S/P converter 7.

With the above circuit, the clock C in the 57p converter 7 is
The setup time and hold time for data A are ensured, and stable operation is guaranteed.

The output of the s7p converter 7 is synchronized with a latch 8.

It is connected to data bus 102B shown in FIG.

The selector 24 uses the control signals 230 and 23B to convert the 4-bit signal emitted by the AND circuit 22 when the input and output Q of the latch 21 are both 11'' to f!, the appropriate phase pit 24A, and the second rank. Bit 24B is selected and output.

Signals 24A and 24B are.

The AND circuits 26 and 27 and the inverter 25 generate a signal with a polarity opposite to that of the latch 13 clock.

The clock input to the binary counters 28 and 29 is now OK. The counters 28 and 29 are circuits that count the number of times the outputs of the latch 15 and the latch 21 are the same at the rising timing of video data, and have a frequency division ratio equal to 1. If the judgment result of the decoder 23 is correct, the counter 2
The carry output OA of the counter 29 should be outputted earlier than the carry output CA of the counter 29. in this case.

Simultaneously with the carry output of the counter 28, the NOR circuit 32 resets and starts the counters 28 and 29fl, and there is no change in the phase determination results. On the other hand, the second ranking counter 29
If the carry is early (1° counters 2B and 29 are reset and started, the output 31A of the uOR circuit 51 becomes 0", and the outputs of the decoders 23B and 230 are switched.

In other words, the video data that was ranked second is selected as the optimal phase data. This process is intended to fully compensate for the judgment error caused by the coarse phase difference time used for one phase judgment.

Frame counter 17 receives vertical synchronization signal VSYNC!
? This is a binary counter that uses a clock whose waveform has been shaped by a Schmitt inverter 15 as the clock CK.

When the frame counter 17 reaches full count, it stops counting until it is reset by the inhibit gate 16. ) The frequency division ratio of the V-mu counter 17 is designed to be several times or more the counting time of the counters 2B and 29. The AND circuit 18 activates the reset signal generation circuit 19 when the frame counter is in a full count state and the carry of the % second rank counter 29 is output.

The reset signal generation circuit 19 generates a signal VSYN C! It generates an output in synchronization with , resets the frame counter, and updates the output Q of the latch 21 at the same time. To update the output of the mataratch 21, the latch 21 updates (vZ + vt
! The output 23AK of the decoder 23 is manipulated even when a code such as v, IVo)=('+0+1+o,1), which is impossible during normal operation, is held.

As mentioned above, the statistical processing circuit 14 needs to perform several judgment processes, so if it is entirely microprocessorized and equipped with a highly flexible feedback processing function, it will be possible to perform appropriate judgment processing. It is.

As a variation of this embodiment, in the actual rA example, video data having a pulse width twice as wide as that of the dot clock is input to the total delay circuits 2 and 5.4, but a faster circuit may be used. If used, this embodiment can operate even if the relationship between the video data and the dot clock is reversed.

Also, it is possible to integrate the launches 13 and 21 by devising the latch clock, so the latches 16 and 21 do not necessarily have to exist independently! There isn't.

Furthermore, in applications where the video data has a low noise level and is supplied with a stable video signal,
It goes without saying that the frame e counter 17 and the counters 28 and 29i are not necessarily necessary.

In the above description, although no mention has been made of the apparatus to which the present invention is applied, the present invention applies to information equipment using a CRT as a display device, such as an LCD or an FDP.

CR using flat panels and displays such as EL
The present invention is not only applicable to the T replacement field, but also to video printers and receiving devices for transmitting image information using communication lines.

[Effects of the Invention] As explained above, the present invention encodes phase information with respect to the dot clock from a plurality of video data having a constant 0% delay relationship, and automatically selects video data with an optimal phase based on this. So.

The present invention has the effect of realizing a video signal digital signal converting circuit with high operational reliability and easily applying it to a larger digital output device with a high dot frequency. (9) Since the circuit of the present invention can be integrated into a semiconductor, there is no need for an external adjustment circuit for the video signal interface, and accordingly, there is no need for adjustment steps before shipping the product, resulting in a cost reduction effect.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the automatic phase detection circuit of the present invention, FIG. 2 is a diagram showing main parts of phase detection timing,
FIG. 6 is a diagram showing an overview of a system to which the embodiment is applied. 2.3, 4.12...Delay circuit 9.15.22...4-bit latch 6.24...
selector

Claims (1)

Claims: An automatic phase detection circuit in a video signal interface for converting a video signal into a digital signal, characterized by having the following configuration. a) Delay means for converting video data input into a plurality of signals with the same pulse width and phase differences; b) a first latch circuit that simultaneously latches the plurality of phase difference signals using a dot clock; c) the first latch. d) A second latch circuit that holds the output of the circuit for a time period much longer than the dot clock period; A means of selecting among signals.