JPS6232535A - Information processor - Google Patents

Abstract

PURPOSE:To curtail hardware quantity by integrating an approximate inverse number table for storing a divisor whose use frequency is low, and a memory decoder for storing a control signal to an operating circuit, in the same storage means, and switching and using a read-out address and an output data. CONSTITUTION:In an approximate inverse number table/memory decoder 30, an approximate inverse number data of a divisor, and a part of plural groups of control signals to an operating circuit 25 are stored by plural words each in mutually different addresses. Switching of an approximate inverse number table function or a memory decoder function of the approximate inverse number table/memory decoder 30 is executed by an address selector 40 in accordance with an indication of a micro-instruction which is sent out onto a signal line 78 from a micro-instruction register 20.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an information processing device that uses both an approximate reciprocal table and a memory decoder, and in particular, an information processing device that uses an approximate reciprocal table and a memory decoder, and in particular, an information processing device that is equipped with a reciprocal table/mesori decoder that integrates both of the above functions. It relates to a processing device.

(Prior Art) Figure 3 is a block diagram showing an example of such an information processing device according to the prior art. In FIG. 2, 10 is a control storage device, 20 is a microinstruction register, 25 is an arithmetic circuit, 31 is a memory decoder, and 32 is an approximate reciprocal table.

In FIG. 2, the control signal to the arithmetic circuit 25 is read out from the control storage device 10, which stores a plurality of words of microinstructions, into the microinstruction register 20 for each machine cycle of the arithmetic instruction. A portion of the read microinstructions is directly sent to the arithmetic circuit 25 as a control signal via the signal line 79. On the other hand, among the set of multiple word control signals stored in the memory decoder 31, the - word control signal is sent to the arithmetic circuit 25 via the signal line 75. The memory decoder 31 receives an address signal sent from the address field of the microinstruction stored in the microinstruction register 20 via the signal line 72.
control signals are selected and read out. Memory decoder 31
The output of is supplied to the arithmetic circuit 25 via the signal line 75 as described above.

On the other hand, the approximate reciprocal data of the divisor is sent to the arithmetic circuit 25 via the signal line 77 from the approximate reciprocal table 32 in which multiple words of approximate reciprocal data are stored. The approximate reciprocal table 32 uses the divisor data on the signal line 71 as a read address.

In the above configuration, the approximate reciprocal table 32 for storing the approximate reciprocal of the divisor used in the divisor instruction is independent of the memory decoder 31 for storing a part of the control signal for the arithmetic circuit 25. It is prepared as dedicated hardware. However, among the many types of instructions executed by this type of information processing device, only the division instruction actually reads approximate reciprocal data from the approximate reciprocal table 32 via the signal line 77. Therefore, the approximate reciprocal data is used by the information processing device only once in each division instruction.

Further, the accuracy required for the approximate reciprocal data, that is, the data width and the number of words, is determined by the arithmetic processing capacity of the arithmetic circuit 25.

(Problems to be Solved by the Invention) In the conventional information processing device described above, the approximate reciprocal table and the memory decoder are realized by independent hardware, so the semiconductor Due to the remarkable increase in the capacity of memory elements, there is a disadvantage that when the above semiconductor memory element is used for an approximate reciprocal table, there may be a vacant area. Exclusive use of the reciprocal table has the disadvantage of increasing hardware waste.

An object of the present invention is to incorporate an approximate reciprocal table for storing rarely used divisors and a memory decoder for storing control signals to an arithmetic circuit into the same storage means, and to store read addresses and output data. It is an object of the present invention to provide an information processing apparatus in which the above-mentioned drawbacks are eliminated by switching and using the apparatus, and the hardware is configured without waste.

(Means for Solving the Problems) An information processing device according to the present invention is configured to include storage means, address selector means, gate circuit means, data selector means, and an arithmetic circuit.

The storage means is for storing approximate reciprocal data of the divisor for executing the deletion instruction and control signals for controlling the execution of the division instruction, each of which spans a plurality of words.

The address selector means selects predetermined address data for each machine cycle in order to read out the read address of the storage means as a divisor of a division instruction or a control signal.

The gate circuit means is for outputting approximate reciprocal data read from the storage means.

The data selector means selects the data when the data read from the storage means is a control signal, and selects predetermined approximate reciprocal data when the data read from the storage means is approximate reciprocal data. The arithmetic circuit uses the output of the data selector means as a control signal and executes processing using approximate reciprocal data output from the gate circuit.

(Embodiment) Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. In FIG. 1, 10 is a control storage device, 20 is a microinstruction register, 25 is an arithmetic circuit, and 3
0 is an approximate reciprocal table/memory decoder, 40 is an address selector, 50 is a data selector, and 60 is a gate circuit. It is similar to In the approximate coefficient table/memory decoder 30, approximate reciprocal data of the divisor and part of a plurality of sets of control signals for the arithmetic circuit 25 are stored in plural words at mutually different addresses.

Approximate reciprocal table/memory decoder 30's approximate reciprocal table function or memory decoder function is switched by the address selector 40 in response to a microinstruction instruction sent from the microinstruction register 20 onto the signal line 78.
This is done by Therefore, the address selector 40 selects the divisor data sent from the arithmetic circuit 25 onto the signal line 71, or selects the divisor data sent from the microinstruction register 25
The address signal of the memory decoder function sent on signal line 72 is selected from the address field of the microinstruction set to 0. The selected address signal is sent onto the address signal line 73 and added to the approximate reciprocal table/memory decoder 30 as address information.

If the switching instruction sent from the microinstruction register 20 onto the signal line 78 instructs the approximate reciprocal table function, the output data read from the approximate reciprocal table/memory decoder 30 onto the signal line 76 is circuit 60
as approximate reciprocal data of the arithmetic circuit 25 via the signal line 7.
7.

A control signal 74 having a predetermined content is supplied to a signal line 75 by the data selector 50 . This control signal is sent to the arithmetic circuit 25 via the signal line 75.

On the other hand, when the switching instruction on the signal line 78 instructs the memory decoder function, the output data on the signal line 76 is supplied from the data selector 50 via the signal line 75 as a control signal to the arithmetic circuit 25. .

FIG. 2 is a time chart showing an example of the operation of the embodiment shown in FIG. In FIG. 2, among the five machine cycles t0 to t4, at t, the approximate reciprocal table function is instructed by a switching instruction signal (signal line 78) in the microinstruction. At this time,
The address selector 40 selects the divisor data on the signal line 71, and the approximate reciprocal data stored at the corresponding address is read out from the approximate reciprocal table 30, and the gate circuit 6
0 to the arithmetic circuit 25 as approximate reciprocal data (signal line 77). On the other hand, since the switching instruction (signal line 78) instructs the memory decoder function at tOs and t to t4, the control signal (signal line 75) performs the control specified by the address signal flash included in the microinstruction. The data (A) is sent to the memory decoder 30 by the signal.
The data is read out from and supplied to the arithmetic circuit 25. At time t, read data (A) cannot be used as a control signal, and instead, data (B) with predetermined contents is supplied as a control signal. As a result, a control signal is continuously supplied from the arithmetic circuit 25 for each machine cycle.

(Effects of the Invention) As explained above, in the present invention, an approximate reciprocal table for storing a divisor that is used infrequently and a memory decoder for storing a control signal to an arithmetic circuit are stored in the same storage means. By switching between embedded and read addresses and output data, two different functions can be realized with the same hardware, which has the effect of preventing performance degradation and reducing the amount of hardware required. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the actual road side of an information processing apparatus according to the present invention. FIG. 2 is a time chart showing an example of the operation of the information processing apparatus shown in FIG. FIG. 3 is a block diagram showing an example of an information processing device according to the prior art. 10... Control storage device 20... Micro instruction register 25... Arithmetic circuit 30... Approximate reciprocal table/memory decoder 31...
・Memory decoder 32...Approximate reciprocal table 40.50...Selector 60...Gate circuit patent applicant NEC Corporation representative Patent attorney Hisashi Inoro 5den77) 口==koA'l#e
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Claims (1)

[Claims] a storage means for storing approximate reciprocal data of a divisor for executing a division instruction and a control signal for controlling the execution of the division instruction in a plurality of words, and a read address of the storage means for the divisor of the division instruction; Alternatively, address selector means for selecting address data determined for each machine cycle in order to read the control signal, gate circuit means for outputting the approximate reciprocal data read from the storage means; Data for selecting the data when the data read from the storage means is the control signal, and selecting the predetermined approximate reciprocal data when the data read from the storage means is the approximate reciprocal data. It is characterized by comprising a selector means and an arithmetic circuit for using the output of the data selector means as a control signal and executing processing using the approximate reciprocal data output from the gate circuit. Information processing device.