JPS6231447A - Bus analyzer - Google Patents

Abstract

PURPOSE:To attain an effective monitor and the recording of a data bus independently of a computer to be monitored by monitoring a bus data to compare it with the recording and stop conditions that can freely be set and controlling a recording action. CONSTITUTION:The data on a bus 10 to be monitored is monitored by a bus analyzer 20. When this data is coincident with the recording conditions set freely by a teletypewriter 30, the data is written to a memory 21 via a recording control circuit 22. While the memory 21 and the circuit 22 are controlled via a stop control circuit 23 to prohibit the writing action of the data to the memory 21 if said data is coincident with the stopping conditions set freely in the same way. Then the data written to the memory 21 in response to the setting action is recorded by the typewriter 30. Thus the bus 10 is monitored and recorded effectively and independently of a computer to be monitored. This can reduce the capacity of the memory 21 with no undesired recording action.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention relates to a bus analyzer for monitoring the operating status of various computer devices.

B. Summary of the Invention The bus analyzer of the present invention is connected to the bus of a computer device to be monitored, records bus data that meets arbitrarily set recording conditions in memory, and records bus data that meets arbitrarily set stop conditions. When a match is found, the recording operation is stopped, and the operation of the target device is analyzed by reading and analyzing the contents recorded in the memory.

C1 Prior Art] In order to investigate the cause of abnormal operation of a computer device, it is effective to monitor the operating state of the device from signals on the bus (bus data).

For this purpose, conventionally, a CPU is used as part of a computer device.
Some devices are equipped with a recorder that is controlled by a central processing unit (central processing unit) and can record all bus data for a certain period.

When some abnormality occurs in the device, the operation of the recorder is stopped by CPU processing. Thereafter, the CPU reads out the recorded contents of the recorder and performs analysis processing.

D1 Problems to be Solved by the Invention In the conventional method described above, all the bus data is recorded from the start of recording, so the time that can be monitored by a recorder with a limited capacity is short. There is not much bus data that is a key point required for operation analysis, and it is unreasonable to shorten the monitoring time by recording all bus data that includes a lot of unnecessary data. Also, if there is a lot of unnecessary data, analysis becomes troublesome.

In addition, in the conventional method, the recorder is stopped when a certain specific state is detected by the CPU of the monitored device, but since this processing is performed by software, the time difference between the above detection point and the stop point is big. As a result, bus data important for analysis may not be recorded. Furthermore, in order to change the conditions for stopping the operation of the recorder, it is necessary to change the program of the monitored device, which is extremely troublesome.

Furthermore, if the CPU program goes out of control, the bus data monitoring and analysis functions performed by the CPU will also be lost.

In addition, since the operation of outputting the contents recorded in the recorder to an external device is performed using the monitored bus through processing by the CPU of the monitored device, abnormalities in the monitored device (both hardware and software) are detected. ), it may be impossible to output recorded data to the outside.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to efficiently and effectively monitor and record bus data using a device that is functionally completely independent of the device to be monitored. Another object of the present invention is to provide a bus analyzer that is highly flexible and allows recording conditions and stop conditions to be easily and freely changed.

Means for Solving Problem E8 The bus analyzer according to the present invention includes a memory for recording bus data of a computer device to be monitored, and a memory for monitoring the bus data to determine whether or not it meets a predetermined recording condition. recording control means for determining whether or not a predetermined stop condition is met by monitoring the bus data and recording the bus data in the memory when the condition is met; A stop control means for stopping the data recording operation in the memory by the recording control means; a setting input means for arbitrarily setting the recording condition and the stop condition; and a means for reading and outputting the recorded contents of the memory. It is equipped with an output means.

20 Effects The bus analyzer described above is functionally completely independent of the computer equipment to be monitored, and operates as expected regardless of the hardware and software of the equipment to be monitored. The recording control means selects the bus data that meets the conditions from among the bus data that is being converted every moment, and records it in the memory. When the stop control means detects bus data that meets the conditions, it stops the data recording operation in the memory almost without any time delay. The output means reads the recorded contents of the memory via a signal line different from the monitored bus.

G. Embodiment Figure shows the configuration of a bus analyzer according to an embodiment of the present invention. In the figure, 10 is a bus of a computer to be monitored, 20 is a bus analyzer connected to this bus 10, and 30 is a TTY (TTY) as a man-machine interface connecting this bus analyzer 20 and an operator.
teletypewriter).

The bus analyzer 20 has a memory 21 for recording signals on the bus 10 (hereinafter referred to as bus data), and monitors the bus data to determine whether predetermined recording conditions are met, and when the conditions are met. Time to memory 21.

A recording control circuit 22 that sends a signal and records (writes) the current bus data in the memory 21, and a recording control circuit 22 that monitors the bus data to determine whether it meets a predetermined stop condition, and when the condition is met, writes the bus data to the memory 21. 12, a stop control circuit 23 that sends a signal to the control circuit 22 and prohibits data writing to the memory 21, a TTY controller 24, and a switch 25 that switches and connects the TTY controller 24, the TTY 30, and the remote terminal. The main controller 26 is a microcomputer that performs overall control of each part of the bus analyzer 20 (initial setting one hour management, one person output processing, etc.).

By operating the TTY 30 according to a predetermined procedure, the recording conditions in the recording control circuit 22 and the stop control circuit 23 can be changed.
The stopping conditions can be set arbitrarily. For example, an arbitrary address is set as the recording condition or stop condition.

By setting an address as a recording condition, you can record bus data in the memory 21 when the monitored computer device is running a program from a certain address to a certain address, or immediately after referring to data at a specific address. It can be used to record bus data in the memory 21.

Similarly, by setting an address as a stop condition, it is possible to prohibit writing to the memory 21 when the monitored computer device jumps to, for example, an abnormality processing program at a specific address.

When the stop control circuit 23 detects that the stop condition is met,
At the same time that writing to the memory 21 is prohibited, a detection signal is transmitted to the main controller 26 and outputted to the TTY 3G via the TTY controller 24.

Therefore, when a predetermined command is given from the TTY controller 30, the contents recorded in the memory 21 are read out, the main controller disassembles it, and the processed recorded data is sent to the TTY controller via the TTY controller 24. TY
30. The data generated at TTY 30 is separately processed to analyze the operation of the computer device to be monitored.

H1 Effects of the Invention As explained in detail above, the noise analyzer according to the present invention is completely independent of the computer device to be monitored, so it does not depend on the hardware of the computer device to be monitored.

The desired bus data monitoring operation can be reliably realized without depending on software. Furthermore, since only the bus data that meets the recording conditions is recorded in the memory, the limited memory capacity can be effectively utilized and the actual monitoring time can be lengthened. Furthermore, since recording conditions and stopping conditions can be easily and freely set and changed, the operating mode can be easily changed to suit the purpose, providing great flexibility.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a bus analyzer according to an embodiment of the present invention. 10... Bus to be monitored, 20... Bus analyzer,
21... Memory, 22... Recording control circuit, 23...
・Stop control circuit, 24...TTY controller, 25.
...Switch, 26...Main controller, 3o...T
TY (teletypewriter).

Claims (1)

[Claims] (1) A memory for recording bus data of a computer device to be monitored, and monitoring the above bus data to determine whether it meets a predetermined recording condition, and when the condition is met, the bus data is recorded as above. Recording control means for recording data in the memory; and monitoring the bus data to determine whether a predetermined stop condition is met, and when the condition is met, stopping the data recording operation by the recording control means in the memory. A bus analyzer comprising: a stop control means for controlling the recording condition; a setting input means for arbitrarily setting the recording condition and the stop condition; and an output means for reading and outputting the recorded contents of the memory.