JPS62292085A - Scramble system - Google Patents

Abstract

PURPOSE:To simplify a circuit on the decoder side by using a tip level of an inverted horizontal synchronizing signal as a reference level for inverting a video signal. CONSTITUTION:A horizontal signal for a video signal is inverted about a reference level set up by an inversional level setting circuit 24. A video signal is inverted by a video inverting circuit 27 at the tip level of the inverted synchronizing signal. Since the tip level of the horizontal synchronizing signal whose polarity is inverted and scrambled is used as the reference level for inverting a video signal, the circuit constitution on the decoder 200 side can be simplified.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Object of the Invention] (Field of Industrial Application) This invention relates to a scrambling method for video signals in paid broadcasting, etc. This invention relates to a scrambling method that reduces

(Prior Art) Generally, as a method for scrambling pay program signals in pay broadcasting such as CATV, video inversion processing is performed to invert the video signal at a predetermined level, synchronization offset processing is performed to offset the synchronization signal, etc. A method is known in which timing data related to these scrambling processes is transmitted while being superimposed on the vertical retrace period. According to this method, on the receiving contract terminal side, the data superimposed on the vertical retrace period is reproduced, and the video is inverted from the pedestal level of the offset-processed video signal and the pedestal level of the first word of the video signal that has not been offset-processed. The level is determined and the 1-inverted video signal is descrambled.

FIG. 4 is a circuit diagram showing an example of the above-mentioned conventional scrambling method. In the figure, 1 indicates an encoding section that performs scrambling processing, and 2 indicates a decoding section 2 that performs descrambling processing to obtain an owner image signal. .

A video signal to be scrambled is applied to an input terminal of the encoder 1, and a synchronization signal in this video signal is separated by a synchronization separation circuit 3. The separated synchronization signal is applied to a data timing generation circuit 4, which generates a timing signal for scrambling processing of synchronization offset and video inversion, and data indicating this timing. The data generated by the data timing generation circuit 4 is superimposed on the vertical retrace period by the data insertion circuit 5. Also, the synchronous offset circuit 6. The video inversion circuit 7 performs synchronization offset processing and video inversion processing on the video signal at the timing determined by the data timing generation circuit 4.

The video signal scrambled in this way is
The signal is applied to an adder 8, where the audio signal is superimposed, and after being tuned to a predetermined pitch by an RF modulator 9, it is sent to the decoder 2 via a transmission path.

The scrambled video signal input to the decoder 2 is tuned by the tuner 10 and then detected by the detector 11. At this time, the data extraction circuit 12 extracts the data superimposed on the vertical retrace period in the video signal, and based on this data, the synchronization separation circuit 13 extracts the unoffset synchronization signal and reproduces the data. - The timing generation circuit 14 generates a timing signal for descrambling. This data generation/timing generation circuit 14 descrambles the scrambled video signal by performing synchronous offset processing and video inversion processing, so the synchronous offset circuit 15. Timing control of the descrambling operation for the video inverting circuit 16 is performed.

(Problems to be Solved by the Invention) The scrambling waveform in the conventional scrambling method described above is shown in FIG. In this conventional scrambling method, the video inversion level is 1, for example.

It is determined from the pedestal level of the offset-processed horizontal synchronizing signal (OF) and the normal horizontal synchronizing signal. in this case,
An offset-processed synchronization signal, and.

A plurality of sample-and-hold circuits that sample and hold the respective pedestal levels of normal horizontal synchronizing signals and an arithmetic circuit that receives the hold voltages of these sample-and-hold circuits as input and calculates the video inversion level are required. If there is an offset amount in the sample/hold circuit and the arithmetic circuit, or if there is a fluctuation in the output level due to temperature characteristics, etc., the DC level of the descrambled signal or the Video inversion level fluctuates. This causes problems such as flicker or striped patterns due to changes in the DC level between horizontal lines on the descrambled screen, deteriorating the reproduced image.

This invention was made in view of the above points.

It is an object of the present invention to provide a scrambling method that can simplify the configuration of a descrambling circuit without preventing deterioration of a reproduced image that has been simplified by a disc.

[Structure of the invention]

(Means for solving the problem) In the present invention, the horizontal synchronizing signal of a video signal is inverted with respect to the reference level set by the inversion level setting circuit 24, and the horizontal synchronizing signal subjected to the inversion processing is The video inversion circuit 27 performs inversion processing on the video signal at the leading edge level.

With this configuration, the circuit configuration on the decoder side can be simplified by using the leading edge level of the polarity-inverted and scrambled horizontal synchronizing signal as a reference level for inverting the video signal.

(Embodiment) A pay program signal is scrambled in the code section 100, and decoded and descrambled in the decode section 200.

The encoder 100 performs synchronous offset processing, video inversion processing, and scrambling processing on the video signal input to the video signal input terminal IN. these,
The timing information for offset processing and video inversion processing is 2.
For example, it is inserted in a specific scanning period of the vertical retrace period.

The scrambling process in the encoder 100 will be explained using the waveform diagram shown in FIG. 2. The original video signal input to the video signal input terminal IN (Fig. 2 (Min)
) is determined by the pedestal level setting circuit 20.
It is clamped by the pedestal clamp circuit 21 to the reference potential set in . The clamp operation is performed using the above timing pulse a.
The output of the pedestal clamp circuit 21 is compared with the reference potential at the timing K. The timing of this pedestal clamp operation is
The timing pulse generated by the timing generation circuit ρ (FIG. 2(a)) is followed by K. It should be noted that the data timing generation circuit 2 operates in synchronization with the horizontal synchronization signal and vertical synchronization signal separated by the synchronization separation circuit n.

Then, in the video signal, the horizontal synchronization period (Fig. 2(b)) randomly specified by the data timing generation circuit n is
)) is inverted based on a predetermined level. The video inversion process for this horizontal synchronization signal is performed by an inversion level setting circuit based on the horizontal synchronization signal tip level sampled at the timing of the timing pulse (Fig. 2 (C)).
A feedback operation is performed so that the inversion level for inverting the horizontal synchronization signal becomes a predetermined value, and the inversion level is stabilized and carried out in the synchronous inversion circuit.

Further, data indicating the timing for inverting the horizontal 1A signal and a series of information for controlling subscriber terminals are generated in the data timing generation circuit n, and the information is transmitted to the data insertion circuit 26, for example, for vertical return. It is transmitted while being superimposed on a predetermined horizontal scanning period of the line period.

Next, the video reversal process for the picture period will be described. In this embodiment, the horizontal scanning period during which this video reversal process is performed and the video reversal process are made to coincide (see FIG. 2(b),
(d) ). That is, video inversion for a video signal is
The video inversion circuit 27 follows the pulse A generated by the data timing generation circuit B. At this time, the 1 inversion level detection circuit a, the video inversion circuit n
Both the level (Q IRE) of the normal horizontal synchronizing signal SN at the output end of the signal and the leading level (9 II) of the synchronizing signal SA inverted at a predetermined level, for example, 45 IRE by the synchronous inverting circuit δ are detected. Then, the difference between the video inversion level (90IRE) obtained by calculation from the average level (45 IRE) of both detected levels and the tip level of the inversion synchronization signal obtained by the synchronization inversion circuit 5 is eliminated. 1 inversion level control circuit 17 performs control so that the inversion level in video inversion circuit n becomes constant by feedback operation.

In this way, the output terminal OUT of the encoder section 100 is supplied with the horizontal synchronizing signal at a predetermined level (for example, 45 IRE) in accordance with the timing specified by the data timing generation circuit n.

A video signal is obtained by inverting the picture signal at a predetermined level (for example, 9QIRE) and scrambling the original signal.

In this case, the leading edge level of the synchronization signal inverted by the encoder section 100 is a stable level.

It can be used as an inversion reference level for inverting a video signal.

Next, the decoder section 200 will be explained.

The video signal scrambled by the encoder section 100 is sent to the input terminal IN of the degider section 200 via a transmission path.
added to. Synchronous separation circuit (9) of decoder section 200
separates the vertical synchronization signal and the horizontal synchronization signal that has not been subjected to video inversion processing.

Further, the transmission data superimposed on a predetermined period of the vertical synchronization signal is extracted by a data extraction circuit 32, and the data reproduction is performed by the data reproduction scaling generation circuit 31. This playback data is processed by the encoder section 100 to reproduce timing pulses related to video scrambling processing.
It is used for generation by the timing generation circuit 31.

The pulses obtained by the timing generation circuit 31 (FIG. 2(e)) are sent to the pedestal clamp circuit 33.

Pedestal clamping is performed only on normal horizontal synchronizing signals that have not been scrambled.

Further, a video inversion level for a picture signal for descrambling a scrambled signal subjected to video inversion processing is set by an inversion level setting circuit. At this time, the video inversion level for the picture signal is set based on the leading level (for example, 50I) of the horizontal synchronization signal, which is scrambled by inverting the horizontal synchronization signal at a predetermined level. Then, at the timing shown in FIG. 2(f), the horizontal synchronization signal that has been inverted by the synchronization inversion circuit A is inverted and returned to the normal polarity of the synchronization signal.

The video inversion level in the video inversion operation during the picture period is set by sampling the inversion level circuit at the timing shown in FIG. 2(y). The video inversion level set by the inversion level circuit N is derived to the video inversion circuit A, and at this level, the picture Gt is inverted according to the timing shown in FIG. Rumbled signal (Fig. 2 Vs
).

Next, details of the decoder section 200 will be explained using FIG. 3. Note that parts having functions corresponding to those in FIG. 1 above are designated by the same reference numerals.

First, in the decoder section 200, a scramble signal to be descrambled is applied to the input terminal IN.

A DC clamp operation is performed at the pedestal clamp circuit. The clamp level at this time is a divided voltage level Pv obtained by dividing the power supply voltage VOC by a series circuit of resistors.The capacitor C1 is charged with this voltage, and the clamp pulse ( Figure 2(e)
), the clamp voltage is applied to the pace of the transistor Q2 by switching the switch 8W according to the voltage. For this reason, the scrambled video signal applied to the pace of transistor Q1 (Fig. 2 v2)
The pedestal level of is clamped on the pace side of transistor Q2 during the normal horizontal sync signal period.

And 1. The signal subjected to the DC clamp processing in this manner is applied to the synchronous inversion circuit 35, where the polarity of the horizontal synchronous signal subjected to the inversion processing is inverted. What is the polarity reversal process for the horizontal synchronization signal?

In accordance with the timing shown in FIG. 2 (0), the switch SW2 switches to the emitter output of the transistor Q.

This is done by selectively deriving the collector output of transistor Q. That is, the polarity of the horizontal synchronizing signal is restored according to the timing shown in FIG. 5(f).

Next, the video inversion operation during the picture period in the video signal will be described. The polarity of the video signal is controlled according to the timing pulse (FIG. 2(h)) applied to the switch SW. The video signal inversion level at this time is set by using the voltage sampled at the capacitor C7 according to the timing pulse ((9) in FIG. 2) at the tip level (90 E) of the horizontal synchronizing signal whose polarity has been inverted. That is, the voltage sampled by the capacitor C1 is applied to the collector side of the transistor Q4.

Define the inversion level when performing inversion processing on the picture signal. Switch SWs is set at a predetermined timing (Figure 2)
The descrambled signal which inverts the image by switching is outputted via the emitter follower transistor Q.

Note that the resonant circuits (Lto, C1o), (Lto, Ct) provided in the switches sw, , sw, respectively,
o) has a resonance frequency of approximately 3.58 MHz, and traps one color subcarrier to prevent the color signal from affecting the video signal.

The emitter of the transistor Q obtains a descrambled signal, and the differential transistor pair of transistors Q, , Q detects the synchronization signal leading edge level of the descrambled signal with the pace voltage level of the transistor Q6. , the diskla/pull signal obtained by slicing the horizontal synchronization signal tip level at a predetermined level is amplified by transistor QB, and emitter follower transistor Q,
is led out to the output terminal OUT. The differential pair transistors Q, , Q.

Transistor Q+ during the synchronization signal period detected from K.

conducts, the tip of the horizontal synchronizing signal is expanded to a predetermined level, and the horizontal synchronizing signal with the expanded tip is output to the above output terminal.
It is clamped to a predetermined level by IIK.

As a result, a horizontal synchronizing signal and a signal descrambled for the picture are obtained at the output terminal OUT.

〔Effect of the invention〕

As described above, according to the scrambling method according to the present invention, when both the horizontal synchronization signal and the picture signal are scrambled by the video inversion process, the top level of the horizontal synchronization signal subjected to the video inversion process is used as the picture signal. Since it is used as an inversion reference level when inverting, the scrambling effect can be enhanced. Further, in the descrambling process, since the video inversion process for disc simplification is performed on the picture signal based on the leading level of the inverted horizontal synchronization signal, flickering of the reproduced image can be prevented. Furthermore, there is no need to separately transmit the video inversion reference level for descramble processing, which is advantageous in terms of data transmission efficiency.

Furthermore, according to the present invention, it is possible to provide a scrambling method that can simplify the circuit configuration of the descrambling circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the scrambling method according to the present invention, FIG. 2 is a circuit diagram showing four 8 diagrams to explain the operation of FIG. FIG. 4 is a circuit diagram showing a conventional scrambling method, and FIG. 5 is a waveform diagram for explaining the circuit operation of FIG. 4. 100...Encoder section. 200...Decoder section. u, 29... Inversion level setting circuit. 3...Synchronous inversion circuit. n...Video inversion circuit. Agent Patent Attorney Noriyoshi Chika Yudo Yukio Yuyama

Claims (1)

[Claims] In a scrambling method that performs inversion processing on a horizontal synchronization signal and a video signal of a video signal, the horizontal synchronization signal is inverted at a predetermined level, and the leading level of the inverted horizontal synchronization signal is used for inverting the video signal. A scrambling method characterized in that the video signal is inverted and used as a reference level to obtain a scrambled signal.