JPS6228994A - Memory integrated circuit - Google Patents

Abstract

PURPOSE:To perform a high speed page mode utilizing latched data while a row address strobe signal is OFF by latching read out data at the leading edge of the row address strobe while a line address strobe signal is ON. CONSTITUTION:A read out data output RD from a memory part 1 is determined as the read out data after the prescribed time of the trailing edge of a row address strobe signal the inverse of CAS, and is made indeterminate with the OFF of the inverse of CAS. While a control signal CP is '0', the data RD are outputted as they are as data RD' from a latch 2, and the data RD are latched at the leading edge of the signal CP and while the signal CP is '1', the read out data are held. Also, when a control signal OC is '1', the output D0 of a tri-state buffer 3 becomes active, and the data RD' are outputted and the output D0 becomes high impedance at the '0' of the signal OC.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to dynamic memory integrated circuits (ICs).

[Conventional technology]

Conventionally, this type of memory IC requires two clocks: a row address strobe RA,S and a column address strobe CAS, and the address is set to the row address RA and column address CA according to the row and column of the memory cell array. Generally, minutes are transferred by time division. In this type of memo IJ'IC, an operation mode called page mode is often added in addition to normal read and write operations. Regarding this page mode, for example, see Book 1'-LSI Handbook (1988) published by Ohmsha.
It is explained on page 492 of 4th grade).

This page mode is a mode in which the data for one row of the memory cell array determined by the row address strobe RA8 and row address RA is considered as one page, and data is sent out at high speed using the booter column address strobe CAS and column address GA within the page. be. FIG. 4 shows a time chart for reading in the page mode. Up to time T, the operation is the same as normal read operation, and the output D of the bit selected by RAO and CAO is determined by the falling edge of RAS and the falling edge of CAS.
O is read. In this page mode, after this RAS
is on, synchronize with CA8 and enter any column with 0 people as CAI, CA2...CAn, the data DI in the page determined by the first RAO
, D2...Dn are sequentially read out.

On the other hand, the output of this type of memory IC is usually tri-stated because it is wired with the output of multiple memory ICs, and the output is controlled to be in a high impedance state when CAS is turned off. .

[Problem that the invention seeks to solve]

Typical specifications for the conventional dynamic memory IC mentioned above include tpc for the page cycle time of CA8 repetition in page mode, and jcAcc for the access time of the output cloth from the fall of CAS to the time from A8 on to output high impedance. Letting toFF be as follows.

tpc = minimum 120nli tcAc""Maximum 5Qns t CA8 - Minimum 5Qns t OFF - Minimum Qns tcp = small 5Qns Therefore, when operating with the minimum page cycle.

The effective time width of the output is Qns. However, in practical use, a certain effective time width is always required, so it is necessary to increase tcA8 by that amount to ensure the effective output width. For example, in order to secure an output effective width of 4 Qns, it is necessary to set 'CAs to 100 ns, and in this case, tr'c increases to 160 na, which is inconvenient for realizing a high-speed memory device.

An object of the present invention is to solve the above-mentioned problems and to provide memory
Our goal is to provide the following.

[Means for solving problems]

Memo IJIC of the present invention includes a memory array section that performs a read operation when both first and second control signals are on, and a memory array section that performs a read operation when both the first and second control signals are on, and a memory array section that performs a read operation when the first control signal is on and the read data from this memory array section is read out when the first control signal is on. The first control signal is configured to include a latch circuit that latches when the second control signal is off, and a tristate output circuit that receives the output of the latch circuit and puts the output into a high impedance state when the first control signal is off.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a memo IJIc showing an embodiment of the present invention. In this embodiment, the storage section 1 and the data latch 2
, an output buffer 3 , an inverter 4 , and an AND gate 5 . The storage unit 1 consists of a memory cell matrix of a memory array, an address decoder, etc.
The explanation will be omitted here. The read data RD from the storage section 1 is input to the data latch 2, and the output TLD' of the data latch 2 is outputted to the outside via the tri-state output buffer 3 as the read data output Do. In addition, the clocks of RAS and CAS control the storage unit 1, and the output of the inverter 4 of RA8 and the clocks of CAS
A signal CP for controlling the data latch 2 is generated from the output of the AND gate 5, and a signal OC for controlling the output buffer 3 is generated from the output of the inverter 4 of RAS.

FIG. 2 is a truth table showing the relationship between RAS, CA8, CP, and QC, and FIG. 3 is a timing chart of the page mode according to this embodiment.

The read data output RD from the storage unit 1 is determined as read data at the edge for a certain period of time from the falling edge of CAS, and then CA8
Undefined when off. While CP is "0", RD is output as is to RIy, RD is latched at the rising edge of CP, and CP
The read data is held while the bit is "1". Also, O.C.
When is "1", the output DO of the tri-state buffer becomes active and RF is read out, and when OC is "O", DOij becomes high impedance.

As a typical time example of this embodiment, even when the minimum page cycle tpc = 12On@, tOFF-1cP
-The minimum is 5Qns, and an output data effective width of 6Qns can be secured. Therefore, there is no need to widen the CAS on width in order to ensure the effective output width as in the conventional case. Also, R
Since the output is controlled to high impedance when AS is off,
Wire the outputs of multiple ICs.

-Door is also possible as before.

〔Effect of the invention〕

As explained above, the present invention provides CA
By adopting a configuration in which read data can be latched at the rising edge of S, the data latched while CAS is off can be effectively utilized, making it possible to execute a high-speed page mode with a minimum cycle time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a memory IJIC according to an embodiment of the present invention, and FIG. 2 is a clock RAS of the IC shown in FIG. A truth value diagram of CAS and internal signals CP and QC, FIG. 3 is a time chart of the page mode operation of FIG. 1, and FIG. 4 is a time chart of the page mode operation of the conventional memory IJIc. 1...Storage unit, 2...Data latch,
3... Output huffer, 4... Inverter, 5... AND gate. 7/-゛. Agent: Susumu Uchihara (', □Mine 1)
Kunimine 21 yen]

Claims (1)

[Claims] a memory array section that performs a read operation when both the first and second control signals are on; and a memory array section that latches read data from the memory array section when the first control signal is on and the second control signal is off. and a tri-state output circuit that receives an output of the latch circuit and puts the output in a high impedance state when the first control signal is off.