JPS62285555A - Optical transmission-reception circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit for optical data link not requiring a broad band amplifier at a reception side by applying 1/2 frequency division to a reference frequency when a digital signal is logic 1 and applying 1/4 frequency division when the signal is 0 so as to send a binary digital signal of 0/1. CONSTITUTION:A non-return zero (NRZ) code is not sent directly but send after being converted into a frequency shift keying (FSK) code. That is, the FSK code expresses a digital signal by using the pulse train of a frequency (f) and the pulse train of a frequency 2f, and a reference frequency whose frequency is 4f is oscillated, and the frequency 2f is obtained by 1/2 frequency division and the frequency (f) is obtained by 1/4 frequency division. The frequencies corresond to 0/1 of the digital signal to sent them. The frequency of the sent pulse train is far higher than the pulse frequency of the original signal, but the band requested for the amplifier is between f-2f and the portion close to the DC is eliminated from the band.

Description

Detailed Description of the Invention m Technical Field The present invention relates to an optical data link using F'SK modulation and having a simple circuit configuration.

An optical data link bidirectionally transmits and receives data among a plurality of transmitting and receiving circuits connected by optical fibers.

Each station has a transmitting circuit and a receiving circuit.

The transmitting circuit includes a circuit that modulates a digital signal to be transmitted, a circuit that amplifies the digital signal, and a circuit that drives a light emitting diode LED or a laser diode LD using the amplified current.

Optical fibers include silica glass fibers, multi-component glass fibers, and plastic fibers, and the appropriate one is selected in consideration of transmission distance and price.

The receiving circuit consists of a pin photodiode, an avalanche photodiode, etc. that converts an optical signal into a current signal, a circuit that amplifies the current, a circuit that binarizes it, a demodulation circuit, etc.

Since the original signal to be transmitted is a digital signal, it is a signal containing consecutive 0's and 1's.

This can be called a non-return zero (NRZ) code. The original signal may be code-modulated in various ways,
When using the original signal itself, the NRZ code is used.

It is called a non-return zero because the two values 0 and 1 are continuous and the value does not necessarily fall to O within one bit.

On the other hand, return zero (RZ) expresses 0 with a short pulse and 1 with a long pulse. Since it always drops to 0 within 1 bit, it is called return zero.

B) Conventional technology and its problems The mainstream of conventional technology was to transmit the NRZ code as is, or to use a self-synchronized code and decode it on the receiving side using a clock synchronized with the transmitted signal. .

Transmitting and receiving the NRZ code has the advantage that it is simple and does not require a modulation circuit.

However, this has the disadvantage that a wideband amplifier is required on the receiving side.

Since the digital signal is sent as is, O and 1
There is also a part where the bits are alternated one by one. There are parts where only ○ continues. There are parts where only 1 continues.

In order to correctly restore a pulse that is a rectangular wave, an amplifier circuit having a bandwidth many times the pulse repetition period f is required.

When a rectangular wave is decomposed into Fourier components, it includes many harmonics nf in addition to the fundamental wave f. Unless the circuit is capable of amplifying these harmonics, the rectangular wave cannot be directly amplified. Even if it is cut at an appropriate harmonic nf, a band of f-nf is required to amplify fast pulse changes.

On the other hand, since it is also necessary to amplify the part where only 0 or 1 continue, a band from 0 to E is also required.

In the end, a bandwidth of O%nf is required.

The method of using a self-synchronized code and decoding with a clock synchronized with the transmitted signal on the receiving side has the following drawbacks.

We can convert digital circuits into custom ICs, SSI (s
mall 5cale integrated cir
The transmitting and receiving circuits were constructed using

Therefore, there was a problem in terms of cost. Another drawback is that the dimensions are too large.

(1) An object of the present invention is to provide an optical data link circuit that does not require a broadband amplifier on the receiving side.

A second object of the present invention is to provide an inexpensive transmitting/receiving circuit for optical data links.

It is a third object of the present invention to provide a transmitter/receiver circuit for an optical data link that is small in size.

Internal Structure The present invention does not directly send the NRZ code, but converts it into an FSX code before transmitting it.

F S K (frequency 5hift ke
ying ) code is a pulse train of frequency f and 2f
A digital signal is expressed using a pulse train.

In the present invention, a reference frequency with a frequency of 4f is oscillated, divided by 2 to obtain a frequency of 2f, and divided by 4 to obtain a frequency of f.
Obtain the frequency of

This is transmitted in correspondence with 0 and 1 of the digital signal. The frequency of the transmitted pulse train will be much higher than the pulse repetition frequency of the original signal. However, the band required for the amplifier is between E and 2f. The portion close to direct current is excluded from the required band.

In addition, the present invention can be used to perform FSX modulation and demodulation.
SI can be used and costs can be significantly reduced. This is because no special circuit is required. Also, the size can be reduced.

This will be explained below with reference to the drawings.

FIG. 1 shows a transmitting circuit of the optical data link transmitting/receiving circuit of the present invention. FIG. 2 shows the receiving circuit.

The transmitting circuit consists of three SSIs and an LED.

Some external components consist of resistors, capacitors, and crystals for the oscillator.

In this example, 74HCO4, 74HC112, 5N75
I am using three 551s. Both are easily available. These are ICI, IC2, IC
I'll call it 3.

The ICI may be a Hex Inverter of the 7404 type. IC2 may be a JK flip-flop of the 74112 type.

IC3 is an open collector driver, and there are many types of this as well.

The power supply voltage is 5V, and capacitor C1 is used for stabilization.
Contains. Also, since a driver for one side of IC3 is unnecessary, the input is pulled up to the power supply using resistor R3, so that the Nant gate 16 does not function.

As it is, it is difficult to follow the circuit connections, so Figure 3 shows the same circuit in a more easily visible form.

For correspondence, the same elements are given the same number. The transmitting circuit will be explained with reference to FIG.

A crystal oscillator 10 is connected between the input and output of the inverter 11,
Resistor R4 is connected. Also, the input and output are grounded via capacitors Cz and C3.

Therefore, oscillation of the frequency of the oscillator occurs here. Let this be 4f.

The inverter 12 inverts the voltage at the oscillation terminal C of the oscillator 10 to produce a correct square wave pulse.

A rectangular wave pulse d of frequency 4E is input to the clock CK of two flip-flops Fl and F2.

Flip-flops F1 and Fz are JK flip-flops that can be reset and preset.

The reset terminal λ is a terminal whose output Q becomes O when it is 0.

The preset terminal PR is a terminal whose output Q becomes 1 when the preset terminal PR is O. Both terminals function with zero human effort.

Let SD be the digital data to be transmitted. This is a digital signal string that takes two values, O and 1.

It does not undergo any modulation and is the same as the NRZ code.

The transmission signal SD is input to the input 1 of the inverter 13. The inverted output is the preset input P of the flip 10 knob F1.
Connect to R.

Both the J input and K input of flip-flop F1 are connected to the power supply Vc.
Raise it to c. Also pull up the reset terminal to Vcc.

When J and both are 1, the flip-flop simply functions as a divider by two. In other words, the clock CKlr+1ψ−
This occurs in the nozzle output Q and the reverse output Q of the Rle wml/n item Yusuke.

When J=1 and K=Q, the output Q becomes 1.

When J=O, J=1, the output Q becomes 0.

When J=O1K=0, the output maintains the previous output Q.

The preset terminal PR and reset terminal of the flip-flop F2 are pulled up to the power supply voltage Vcc.

The output Q of F2 is input to both J and J of the flip-flop F2. The output Q of F2 is connected to the input of the Nandt gate 14. Nant gate 14 simply acts as an inverter.

The output of the Nandt gate 14 is connected to the base h of the transistor 15. Emitter is grounded. Collector i is connected to the anode of the LED via resistor R2.

The cathode of the LED is grounded.

The anode j of the LED is connected to the power supply Vcc via Rs.

The operation of the transmitting circuit will be explained.

When the fat transmission signal SD is "1", PR becomes 0 and Fl is preset.

In other words, the output Q is 1. Since the output Q is 1, the input to J of F2 is 1.

F2 is toggled and becomes a divider by two. 4 to clock CK
Since the frequency of f is input, a pulse with a frequency of 2f appears at the output Q of F2.

Q=1 and Q=O alternate, which turns the LED on and off.

When Q=1, the output of the Nandt gate 14 is 0 and the transistor 15 is off, so the voltage at point j becomes high and L
ED emits light. At this time, R1 functions as a current limiting resistor.

When Q=O, the output of the Nandt gate 14 is 1 and the transistor 15 is on, so the voltage at point j becomes lower than Vcc divided by R1 and R2, and the LED turns off.

It is supposed that more power is consumed when the LED is off, but anyway, at a frequency of 2E, the LED
flashes.

lbl When the transmission signal SD is 'O'', the preset input of F1 becomes PR:l.

This means that the presets will no longer work. Reset λ=1
And this isn't working either. The input to J is powered up by the power supply.

Therefore, this flip-flop acts as a normal toggled flip-flop.

In other words, it becomes a frequency divider by two. This is 1/1 of the clock pulse.
A pulse with a frequency of 2 is applied to the output Q.

The value of the output Q is input to J and K of the next stage flip-flop F2.

When the input to J is 0, the value of the output of flip-flop F2 remains unchanged even when receiving a clock pulse. Therefore, while the output Q of Fl is 0, the output of F2 remains unchanged.

When the output Q of Fl becomes 1, F2 becomes J=1, and the value of Q changes according to the clock pulse.

The output Q of Fl is a 2f pulse repetition, but the output Q of Fl becomes 1 once in one cycle, and at this time, the output Q of Fl becomes 1.
The output of 2 changes from 1 to 0 or from O to 1. Therefore, the output of F2 changes from 1 to 0 and from 0 to 1 in two periods of Fl.

Therefore, the output change of F2 is E.

That is, by Fl and F2, pulses of 174 frequencies of the fundamental pulse are obtained.

As is clear from the above explanation of fat and lbl, the repetition frequency of the output Q of F2 is 2f if 5D=l and f if SD=Q. It can be easily obtained by dividing the frequency by /4. 2r and f, this is FSK modulation.

power) configuration and operation of the receiving circuit FIG. 2 shows the receiving circuit.

This amplifies the photocurrent of photodiode PD and FSK
This is a circuit that demodulates the modulated signal.

The current-voltage converter is assembled with discrete elements. After this, it can be configured by SSI such as 74HCO4 and 74HC123.

Those written as IC4 are 123 type one-shots (
This is an SSI that includes two monostable (monostable) multivibrators.

IC5 is just 04 type Hex Invert
It is r.

Since it is difficult to trace the operation of this circuit diagram, the same circuit diagram has been rewritten and shown in FIG. 4 to make it easier to understand.

The capacitors C4 and C5 and the self-inductance Ll prevent noise from being mixed in from the power supply and suppress fluctuations in the power supply voltage.

These are noise filters that are normally inserted and are not related to the operation, so they are omitted in FIG.

First, the current-voltage conversion circuit will be explained.

The photodiode PDi receives an optical signal from an optical fiber. Photodiode PD is reverse biased and has an anode grounded.

A transistor Q! is used as the cathode of the PD. It is connected to the base. The collector n of Ql is connected to the power supply V through a resistor R9.
It is connected to cc.

'The emitter l of Ql is connected to the base of Q2. The emitter of Q2 is grounded.

A collector m of Q2 is connected to the other end n of a resistor R9 via a resistor R8. The collector m of Q2 is connected through a resistor R7 to a point which is the base of Qt and the cathode of PD. This resistor R7 converts current into voltage. □ In parallel with R7, a forward diode Dl is connected between mk. This is to suppress the voltage across R7 to 0.7V or less. Even if the input is large, Dl should be inserted so that the waveform will not be distorted.

A capacitor C8 is connected between point n and ground. This is to stabilize the voltage at point n. R9 is a small resistance, and should be sufficiently smaller than R8 (for example, R9 = 100Ω, Rs = 2 KQ).
Therefore, point n can be considered to be almost a power supply, but in order to stabilize it at high frequency, Cs (for example, 0.01 μF) is applied.
is used.

Point m is the output of the current-voltage converter.

Since the emitter and base of Ql and Q2 are connected,
The voltage at point k is twice the pn junction voltage drop as compared to ground.

The photodiode PD is reverse biased by such a voltage, and when the photocurrent Ip flows, the voltage at point m becomes higher than that at point R7IP only. This causes the voltage to change in proportion to the current.

Inverters 21 to 23, resistors Rto, R11, R
The part consisting of 12 is an AC amplifier circuit.

It may be said that it is extremely unusual to use an inverter to amplify analog quantities.

A differential amplifier circuit or the like is used for analog amplification. The inverter is a logic IC and handles signals that have already been established as digital signals.

The use of an inverter for analog amplification is an originality of the applicant (Patent application No. 60-2188401560.1)
0.1 application).

The 7404 series SSI inverter is available at an extremely low price. It is much cheaper than differential amplifier circuits, operational amplifiers, etc., and in the case of the 74o4 series, one 551
There are 6 inverters inside. Even if it is amplified in three stages, only half of one IC is used.

The feature of the present invention is not in the AC amplification circuit using an inverter, but since this amplification operation is not known, it will be explained.

Connect the input and output of the inverter to a feedback resistor. Connecting the input and output of the inverter in this way means that
In the first place, it is contrary to common sense and is new.

This may seem to cause oscillation, but it does not.

It may seem strange, but a well-connected input and output will remain at a voltage Vo that is about half of Vcc.

Vo is neither the L level nor the H level of the input. It is an intermediate voltage, and can be said to be a voltage in a region where input is prohibited. This is a stable state, and if there is no input voltage, the input and output will continue to be at vO.

When the output input is partitioned by a capacitor, the input/output is Vo if there is no AC signal input.

However, when the AC input voltage enters the inverter input, the input goes up or down from Vo. Then the output will move in the opposite direction. Since the output change is larger than the input change, an amplifying effect occurs.

However, since the input is connected to the output through a resistor, the input voltage is pulled towards the output voltage.

Therefore, when the resistance value is small, the amplification factor is also small.

This circuit consists of three stages of AC amplifier circuits each consisting of identical inverters.

- Give an example. RIO=50KQ%R11=l MΩ,
R12” 100 KG, Ctt == 0.01
Let μF%C12=2.2pF. The amplification level is approximately 10dB in the first stage and 2QdB in the second stage.

The third stage was 3 dB. In the third stage, the capacity of the power sampling capacitor is small (C12=2.2 pF), so the amplification factor is small.

The output U of the amplifier circuit is connected to a Schmitt trigger circuit by a resistor R13 and a capacitor C13.

A Schmitt circuit binarizes an input signal.

This is also one of the analog circuits, and the comparator I
C is often used.

However, here, two inverters are used.

The output of the inverter 24 is connected to the input of the inverter 25, and the output W of the inverter 25 is connected to the input V of the inverter 24 via a resistor R14.

R1o to RL2 provide negative feedback, while R14 provides positive feedback. A circuit in which two inverters are connected in series and connected through a positive feedback resistor is well known. It is well known that this allows waveform shaping.

When the input V becomes L, the output of the inverter 24 goes up and the 2
5 output goes down. Since the decrease in the output of 25 is positively fed back to the input V by the resistor λ, the input V further decreases, and the output W decreases decisively. R14 is, for example, 200 KQ.

For example, R13 is 62 KQ, C,3 is 0.01 P
It is F.

The exchange signal is mainly transmitted to the Schmitt trigger circuit through capacitor C13.

Inverter 26 simply inverts the signal.

Ml and M2 are one-shot multivibrators. The product of the external resistor and capacitor determines the width of the one-shot pulse.

The pulse width T1 of Ml is longer than one cycle (1/2f) of 2f, which is the fundamental frequency divided by two, and is two cycles (1/4).
It's shorter. In other words, . The pulse width of M2 is, for example, twice that of T1, but generally any width is sufficient. Tl, T2 are Rs, Cs, R
6, given by the value of Cr.

Assume that a higher signal (2E) of the FSX code is input.

This corresponds to '°1'" of the NRZ code.

The period of this signal is 1/2E, which is smaller than the width Tl of the one-shot pulse of Ml.

The 74123 type one-shot multivibrator is a retrigger pull, so if the next pulse change occurs while the Tl pulse continues, the output Q (1n H
It remains at +t level.

Since the output Q remains unchanged and is input to the second one-shot multivibrator, M2 is not fully trivialized. Output Q remains high.

That is, the output RD becomes H for a high frequency signal (2E). The pulse change at point X is too fast, Ml remains triggered, the voltage at point 7 does not move, and no pulse is applied to M2. Therefore, Q=0 and Q=1.

Assume that the lower signal (f) of the FSX code enters Ml. This corresponds to OIt of the NRZ code. The period of this signal (f) is 1/f, which is wider than the width T1 of the one-shot pulse of Ml.

Therefore, in each IA period, the output of M2 becomes 1, but T
It becomes 0 after 1. It is 0 between T1-1/f, but 1/
It is triggered after f and the output becomes 1 again.

In other words, the seven points generate a pulse train with a pulse width of T1 and a period of 1/f.

M2 is trigged by pulses at 7 points. Since the pulse width T2 of M2 is, for example, twice T1, it is longer than the pulse period 1/f.

-<T2 (3) M2 Hashi I-I
Since it is a J pull multi vibrator, such T
When a pulse with a pulse period shorter than 2 is input, the output Q remains at the H level.

Therefore, Q becomes L level. Thus, it can be seen that when the FSK code is at a high frequency (2f), RD=1, and when the FSK code is at a low frequency (f), RD==Q.

G) Effects (1) Transmitting digital signals as they are (NRZ code) requires an amplifier circuit that can flatten direct current (DC).

In the present invention, the NRZ code is converted into two pulse trains of faster frequency and transmitted at 2f, f). The band of the amplifier circuit is only required to be E to 2E.

There is no need to amplify the direct current. This means that it does not need to be a circuit that can also amplify direct current, such as a differential amplifier.

In fact, the present invention uses an AC amplifier circuit. It consists of inverters 21, 22, and 23. these are,
They are interconnected by coupling capacitors C9, C11, and C12. Because of these, the DC component cannot be amplified, and only fast frequency signals can be amplified.

(2) Since we decided to amplify only alternating current, the amplification stage becomes extremely simple. This is because the input and output of the inverter can be connected with a resistor, and the input and output can be cut off in direct current with a capacitor.

(3) Conventionally, direct current had to be amplified and a differential amplifier was used, which caused problems in both cost and size. Since a simple AC amplifier circuit using an inverter and a resistor is used, the cost can be reduced and the size can be reduced.

In fact, although the inverter IC74HCO4 in FIG. 2 has six inverters built in, the amplification stage and Schmitt trigger stage can be configured by one IC.

(4) The FSX demodulation circuit can also be configured with two one-shot multi-by-breaks Ml and M2. These can be constructed from two 74HC112 ICs using this single IC.

(5) The FSX modulation circuit also consists of a reference wave (4C) oscillation circuit and two JK flip-flops.

The 74112 type has two JK flip-flops, so you can configure a divide-by-2 or divide-by-4 circuit with just one.

[Brief explanation of drawings]

FIG. 1 is a transmitting circuit diagram according to an embodiment of the present invention expressed on an SSI IC. FIG. 2 is a receiving circuit diagram according to an embodiment of the present invention expressed on an SSI IC. FIG. 3 is a transmission circuit diagram in which the circuit in FIG. 14 has been rewritten to make it easier to see. FIG. 4 is a receiving circuit diagram in which the circuit in FIG. 2 has been rewritten to make it easier to see.

Claims (2)

[Claims] (1) An optical transmitter/receiver circuit that transmits a binary digital signal of 0 and 1, and a reference frequency oscillation circuit that has a frequency sufficiently higher than the bit rate of the digital signal to be transmitted;
When the digital signal is 1, divide the reference frequency by 2,
When the digital signal is 0, the transmitter consists of a frequency divider circuit that divides the reference frequency by four, a drive circuit that blinks the light emitting element using the output of the frequency divider circuit, a light receiving element, and a current flowing through the light receiving element. a current-voltage conversion circuit that converts into voltage;
An optical transmitting/receiving circuit comprising an AC amplifying circuit that AC amplifies a signal voltage, and a circuit that converts a signal frequency-divided by 4 to 0 and a signal frequency-divided by 2 to 1. (2) The reference frequency is 4^f, which is oscillated by a combination of a crystal oscillator and an inverter, and divided by 2 and 4 using two JK flip-flops F_1 and F_2, resulting in a frequency of 2^f. A pulse train with a frequency of T_
1, T_2 is 1/f<T_2, and 1/2^f<T
It is characterized by converting a frequency-divided signal by 4 to 0 and a signal frequency-divided by 2 to 1 using a circuit that connects two one-shot multivibrators in series such that _1<1/f. Optical transmitter/receiver circuit.