JPS62283666A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To regulate the size of a sidewall in a semiconductor device by setting a plurality of MOS field-effect transistors in which drain and source regions by low density impurity diffusing through a gate electrode set region on the same substrate, and setting the widths of the low density impurity regions two types or more. CONSTITUTION:A photoresist 6 is formed only on the left side transistor setting region L of a silicon wafer 1, patterned, and a low density layer source, drain 7 is formed by ion implanting to a right side transistor setting reign R. Then, an oxygen plasma is emitted to separate the photoresist 6 in an atmosphere to which methyl alcohol is introduced, cleaned, and a silicon oxide film 8 is grown on the whole surface. Then, the thickness l1 of the region L: the thickness r1 of the region R becomes approx. 1:1.4. Then, when the whole surface is anisotropically etched, sidewalls Wl, Wr are formed on the regions L, R, and the bottom widths l2:r2 become approx. 1:1.4. Thereafter, high density layers 9, 10 are formed on the regions 4, 7 by ion implanting. Thus, transistors having different electric characteristics are formed on the same semiconductor substrate.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (a) Field of Industrial Application This invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to highly integrated MOS field effect transistors.

(b) Conventional technology A so-called LDD in which the concentration near the gate electrode of the source and drain regions set via the gate electrode is reduced.
2. Description of the Related Art Semiconductor devices are known in which a plurality of MOS type field effect transistors, such as MOS type, DDD type, etc., are set on the same silicon substrate. In these semiconductor devices, each transistor region is set on a silicon substrate, each gate electrode is set in these regions, and then drain and source regions are formed by diffusing low concentration impurities through the gate electrode setting region, and then these substrates are An insulating film is grown in a vapor phase over the entire surface of the surface, and then the insulating film is anisotropically etched to form an insulating film remaining pattern of a predetermined width around the periphery of each gate electrode, and then an impurity diffusion process is further performed. It is manufactured by increasing the impurity concentration of each drain and source region except for the portion corresponding to the remaining insulating film pattern, and setting a lightly doped drain and source region with a predetermined width near the gate electrode.

When a low concentration layer with the same concentration is formed in each transistor region, the low concentration impurity is diffused all at once on the silicon substrate surface, but on the other hand, the low concentration impurity is diffused individually by masking with a photoresist or the like. In some cases, low concentration layers with different concentrations are formed. Further, plasma irradiation treatment and the like are often performed for the purpose of cleaning the vapor phase growth surface of the insulating film and removing the photoresist.

(c) Problems to be solved by the invention However, as semiconductor devices become more highly integrated, attempts have been made to fabricate semiconductor devices having multiple transistors with various different source and drain structures on the same silicon substrate. However, in the semiconductor device described above, the low concentration impurity region set in each transistor is formed by removing the impurity remaining at the periphery of the gate electrode when the insulating film formed over the entire surface of the low concentration impurity region is removed by anisotropic etching as described above. An insulating film pattern (hereinafter referred to as a sidewall) is formed by blocking the subsequent high-concentration diffusion of impurities, and therefore the low concentration is set by the size of this sidewall and, by extension, the thickness of the insulating film. The size of the impurity region will be controlled. In this regard, in the conventional technique described above, since the thickness of the insulating film formed is uniform, the sidewall is formed only in a uniform size, making it difficult to fabricate transistors with various electrical characteristics on the same substrate. was difficult.

In view of this situation, the inventors of the present invention have conducted intensive research and found that when forming an insulating film on the same substrate, it is possible to form the insulating film with selectivity in the thickness of the grown film, thereby reducing the size of each sidewall. We have discovered a processing method that can adjust the amount of water, and have completed this invention.

(d) Means for Solving the Problems Thus, according to the present invention, a plurality of MOS field effect transistors having drain and source regions set by low concentration impurity diffusion through a gate electrode setting region are set on the same substrate. After an insulating film is grown in a vapor phase over the entire surface, the insulating film is removed by anisotropic etching to form an insulating film remaining pattern of a predetermined width around the periphery of each gate electrode, and then further impurity diffusion treatment is performed. By increasing the concentration of impurities in each drain and source region except for the portion corresponding to the remaining pattern of the insulating film, the concentration of impurities in the drain and source regions near the gate electrode is increased.
It consists of forming an lnS type field effect transistor in the insulating film formation process, and at least one of the MOS type electric field By selectively subjecting the surface of an effect transistor to plasma irradiation treatment while supplying a carbon source, a plurality of MOSs in which the setting width of the low concentration impurity region near the gate electrode is set to two or more types.
A method of manufacturing a semiconductor device is provided, which is characterized in that a type field effect transistor is obtained.

In the method of this invention, selective plasma irradiation treatment on the same substrate means that during plasma irradiation, some surfaces of the same substrate are directly irradiated with plasma and others are irradiated indirectly. It means to do something. The above-mentioned indirect irradiation means insufficient irradiation or no irradiation, such as irradiation through a mask or the like. Therefore, a method is used in which the surface of the substrate to be subjected to plasma irradiation treatment is masked in advance by masking or the like, excluding the surface to be directly irradiated with plasma, to form a pattern, and then the surface of the substrate is irradiated with plasma. In this case, for masking, a mask, photorenost, etc. known in the art can be used. First, the photoresist, which serves as a diffusion mask when forming a low concentration layer with a different concentration in each transistor region, can be used as it is as a mask for the pattern formation described above after diffusion.

Oxygen plasma is usually used for the plasma irradiation, and suitable plasma irradiation conditions are those used for ordinary plasma etching, such as irradiation at about 100° C. for 0.5 hours.

The most distinctive feature of the method of the present invention is that the selective plasma irradiation treatment is performed while a carbon source is supplied. In other words, after performing this treatment, if an insulating film is grown all at once on this plasma-treated surface as described later, the film thickness will be greater on the directly plasma-treated surface than on the indirectly plasma-treated surface. The film is formed thickly, making it difficult to achieve so-called selective film growth.

The carbon source is not particularly limited as long as it becomes a gas containing carbon as a constituent element under plasma irradiation conditions, but methyl alcohol is preferred from the viewpoint of ease of gasification and supply. Further, it is preferable that the amount of the carbon source supplied is adjusted so that the carbon concentration in the plasma is always approximately 10%. Further, this carbon concentration can be used to adjust the thickness of the insulating film together with other plasma irradiation conditions (temperature, time, etc.).

In the present invention, after the plasma irradiation treatment, the peeled surface is usually cleaned with nitric acid or the like, and then an insulating film is formed.

The insulating film used in this invention is a normal silicon oxide film, which is formed all at once on the treated surface by a normal vapor phase growth method (CVD method) or the like. At this time, the insulating film is formed with selectivity in film thickness as described above. For example, the plasma irradiation treatment conditions (temperature 100°C 2 hours 30
(10% carbon concentration and 10% carbon concentration), the ratio of the thickness of the film formed on the directly plasma irradiated surface to that of the film formed on the indirect plasma irradiated surface is approximately 1.4:1.

Note that it is preferable that the film is formed to such an extent that even at the minimum thickness, the gate [pole] set in advance in that region is buried.

After the above operation, the insulating film formed as described above is subjected to etching on the entire surface, but in this case, anisotropic etching is performed, and as a result, the insulating film is left with a residual pattern that is left in an inclined manner at the periphery of each gate bridge. , forming a so-called sidewall, and the others are removed.

The width of the bottom surface of this sidewall depends on the thickness of the insulating film. For example, if you want to obtain a width of 0.3 μm, the thickness of the insulating film should be about 0.4 μm. .

After that, impurities are further diffused into the etched surface to form a high concentration impurity region, but at this time, the low concentration impurity region that remains protected by the sidewall formed as described above is spread according to the width of the bottom surface of the sidewall. The widths of the low concentration impurity regions can be set to two or more different sizes on the same substrate. Note that the above two or more types refers to the existence of at least two different setting widths, and even if one of the above is the same type as the other one, e.g. Often, it means that they can be of different types.

The above method provides a semiconductor device having transistors with different electrical characteristics on the same substrate, which is new in this field. Therefore, the present invention provides an MOS type field effect transistor in which drain and source regions are set through a gate electrode setting region, and a low concentration impurity region of a predetermined width is formed in the vicinity of the gate electrode of the drain and source regions on the same substrate. There are multiple settings for these M
The present invention provides a semiconductor device characterized in that a low concentration impurity region in an OS type field effect transistor has two or more set widths.

(E) Effect According to the present invention, when an insulating film is simultaneously grown in a vapor phase on a plasma-untreated surface and a plasma-treated surface while a carbon source is supplied, the growth state of the insulating film is different on both sides, that is, the growth state is different from that on the former side. The latter surface is formed thicker and selectively grows. Therefore, by anisotropic etching, sidewalls having different bottom widths corresponding to the respective thicknesses of the insulating film are formed, and the sizes of the regions protected by the sidewalls during subsequent impurity diffusion are different. .

The present invention will be described in detail below with reference to Examples, but the present invention is not limited thereby.

(F) Embodiment FIGS. 1 to 6 are process explanatory diagrams of a MOS type field effect r transistor having an LDD structure manufactured by an embodiment of the method of the present invention.

In FIG. 1, S
Each gate electrode (3) is connected via an insulating film (2) made of iOt.
) is set, and a silicon wafer (0.5 mm thick ) It is a partial configuration explanatory diagram of (1).

In order to form a low concentration layer source/drain region in the right side transistor setting area (R) of this silicon wafer (1), a photoresist (6) is formed and patterned only on the left side transistor setting area (L). Figure 2).

Next, a low concentration layer source/drain (7) is formed in the right transistor setting region (R) by ion implantation (FIG. 3). Here, if ion implantation into the low concentration layer is performed under the same conditions as in the left transistor setting region, ion implantation may be performed over the entire surface first.

Next, the silicon wafer patterned with the photoresist (6) was exposed to oxygen plasma for 30 minutes in an atmosphere where methyl alcohol vapor was introduced into oxygen plasma at a rate of 10%, and the temperature of the atmosphere was set to about 100'C. The photoresist (6) is peeled off by irradiating with. Thereafter, the silicon wafer is cleaned, and silicon oxide H (8) is grown on the metal surface of the silicon wafer using an atmospheric pressure CVD apparatus (not shown). As a result, the left transistor setting area (I7) is grown. The film thicknesses grown in the region (R) and the right transistor setting region (R) are different, and under the plasma irradiation conditions described above, the film thickness CQ of the region (L) is >: the film thickness (r+) of the region (R).
= 1: formed at a ratio of about 1.4 (
Figure 4).

When the entire surface of the Noricon wafer in this state is etched using an etching device (not shown) for a single silicon oxide film (8) with anisotropy, the left transistor setting area (shi) is etched.
Sidewalls (W&) (Yr) of different sizes are formed in the and right transistor setting region (R), and the bottom width of each sidewall (&!-) (r-
) can be obtained with a ratio of (C,): (r,)=approximately 1:1.4 (Figure 5).

Thereafter, ions are further implanted into the silicon wafer to form high concentration layers (9) (to) in the low concentration layer source/drain regions (4) and (7). At this time, each of the side walls (YN ) (Yr) and the low concentration layer (41×71) protected by the sidewall bottom width (f
f−)(r,), and since there are two or more widths of the low concentration layer on the same silicon wafer, a DD transistor is fabricated ( Figure 6).

(g) Effect of the invention - Δq1- ← +J Iyohirayochota=
To μ? - It is possible to create transistors with different lightning habits. Furthermore, it is possible to adjust the selectivity of the growth rate in the growth of the insulating film, and by increasing this selectivity, it is also possible to configure only a portion of the same semiconductor substrate into an LDD structure transistor. It also becomes possible to form a high concentration layer without a photomask.

[Brief explanation of the drawing]

1 to 6 are process explanatory diagrams of a MOS type field effect transistor of LDD III structure manufactured by an embodiment of the method of the present invention. (1)...Silicon wafer, (2)...
Insulating film, (3)...Gate electrode, (4)(7)...Low concentration layer source/drain region, (5)--Element isolation region, (6 )...
... Photoresist, (8) ... Silicon oxide film, (9) (10) ... High concentration layer, (L)
・−・Left transistor setting area, (R)・・・・
・・Right transistor setting area, (Ma12XVr)・・
...Side wall, (f2.) (r,)...
... Sidewall bottom width. Figure 1 Figure 2 Figure 3 Figure 5 Figure 6 Procedure correction layer June 23, 1985 1. Indication of the case Patent application filed on May 31, 1986 (2) Semiconductor device and its manufacturing method 3. Relationship with the case of the person making the amendment Patent applicant address 22-22 Nagaike-cho, Abeno-ku, Osaka City Name
(504) Shirepe Co., Ltd. Representative Saeki
Asahi 4, Agent 530 Address 1-3 Quarter, 5-chome Nishitenma, Kita-ku, Osaka
One Bill 5, Date of Amendment Order Voluntary Contents of Amendment 1. The title of the invention "Semiconductor device and manufacturing method" in the third line of page 1 of the M specification is amended to "Semiconductor device and manufacturing method thereof." 2. Correct "nitric acid" on page 8, line 8 of Domen to read "ri acid".

Claims (1)

[Claims] 1. A MO in which a drain and source regions are set through a gate electrode setting region, and a low concentration impurity region of a predetermined width is formed in the vicinity of the gate electrode of the drain and source regions.
1. A semiconductor device comprising a plurality of S-type field-effect transistors set on the same substrate, and in which the set widths of low concentration impurity regions in these MOS-type field-effect transistors are set to two or more types. 2. A plurality of MOS field effect transistors in which drain and source regions are set by diffusion of low-concentration impurities through gate electrode setting regions are set on the same substrate, an insulating film is vapor-phase grown on the entire surface, and then the insulating film is grown. is removed by anisotropic etching to form an insulating film remaining pattern of a predetermined width around the periphery of each gate electrode, and then an impurity diffusion process is performed to remove each drain and source except for the portion corresponding to the above insulating film remaining pattern. By increasing the impurity concentration in the region, a plurality of MOS type field effect transistors are formed in which the drain and source regions near the gate electrode are composed of low concentration impurity regions of a predetermined width. By selectively subjecting the surface of at least one of the MOS field effect transistors to a plasma irradiation treatment while supplying a carbon source, a plurality of MOS transistors in which the setting width of the low concentration impurity region near the gate electrode is set to two or more types.
1. A method of manufacturing a semiconductor device, characterized by obtaining a type field effect transistor.