JPS62283644A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62283644A JPS62283644A JP12650386A JP12650386A JPS62283644A JP S62283644 A JPS62283644 A JP S62283644A JP 12650386 A JP12650386 A JP 12650386A JP 12650386 A JP12650386 A JP 12650386A JP S62283644 A JPS62283644 A JP S62283644A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- semiconductor chip
- bumps
- leads
- screen printing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000011347 resin Substances 0.000 claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 22
- 238000007650 screen-printing Methods 0.000 claims abstract description 16
- 238000003825 pressing Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 24
- 238000010438 heat treatment Methods 0.000 claims description 9
- 229920001187 thermosetting polymer Polymers 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000010953 base metal Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に係り、特に半導体
チップの実装方法におけるバンプの製造方法と、このバ
ンプとリードとの接続方法に関するものである。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing bumps in a semiconductor chip mounting method, and a method for manufacturing bumps and leads. This is related to the connection method.
第３図はバンプとリードを利用した半導体チ・ノブの実
装例を示す断面図である。この図で、１は能動機能を持
つ半導体チップ、２はこの半導体チップ１上に所定のパ
ターンで形成されたパッド（外部電極）、３は前記パッ
ド２上に形成されたパップ（突起電極）で、この上にリ
ード４が電気的・機織的に接続され、半導体チップ１の
能動機能を取り出すようになっている。FIG. 3 is a sectional view showing an example of mounting a semiconductor chip/nob using bumps and leads. In this figure, 1 is a semiconductor chip with an active function, 2 is a pad (external electrode) formed in a predetermined pattern on this semiconductor chip 1, and 3 is a pad (projection electrode) formed on the pad 2. , and leads 4 are electrically and mechanically connected thereon to take out the active functions of the semiconductor chip 1.
第４図（ａ）〜（ｄ）に従来のバンプの形成工程を概略
的に示す。FIGS. 4(a) to 4(d) schematically show the conventional bump forming process.
まず、第４図（ａ）に示すように、所定のパターンでパ
ッド２が形成された半導体チップ１上全面にバンプ下地
金属３′をスパッタリングする。次に、第４図（ｂ）に
示すように、′メッキ用のレジス１・膜５を全面に塗布
した後、パッド２上にこのパッド２と同寸法のスルーホ
ール６を形成する。次いで、第４図（ｃ）に示すように
、電解メッキを行い、メッキ金属７を形成する。この場
合、メッキ液に浸っている導通部はレジスト膜５で被わ
れていないスルーホール６の部分のみであるので、結果
的にメッキされるのはパッド２上のみとなる。First, as shown in FIG. 4(a), a bump base metal 3' is sputtered over the entire surface of the semiconductor chip 1 on which the pads 2 are formed in a predetermined pattern. Next, as shown in FIG. 4(b), after coating the entire surface with a resist 1 and film 5 for plating, a through hole 6 having the same size as the pad 2 is formed on the pad 2. Next, as shown in FIG. 4(c), electrolytic plating is performed to form plated metal 7. In this case, the only conductive portion immersed in the plating solution is the portion of the through hole 6 that is not covered with the resist film 5, so that only the top of the pad 2 is plated as a result.
次に、第４図（ｄ）に示すように、レジスｌ−膜５を除
去し、バンプ下地金属３′をエゾチングすることによっ
てバンプ３が完成する。Next, as shown in FIG. 4(d), the resist l-film 5 is removed and the bump underlying metal 3' is etched to complete the bump 3.
第５図（ａ）〜（ｅ）に第４図で形成したバンプ３とリ
ード４の接続方法（以下この接続をボンデ、ボンデと記
す）を概念的に示す。まず、第５図（ａ）に示すように
、バンプ３とリード４の位置合せを行う。次に、第５図
（ｂ）に示すように、ある温度に加熱したツール８を各
リード４に均等に接触するように一定時間、一定圧力で
押し付ける。その結果、第５図（Ｃ）に示すように、バ
ンプ３とリード４が共晶または拡散によって接合され、
すなわち、電気的・機械的にボンディングされることに
なる。5(a) to 5(e) conceptually show a method of connecting the bumps 3 and leads 4 formed in FIG. 4 (hereinafter, this connection will be referred to as bonding or bonding). First, as shown in FIG. 5(a), the bumps 3 and leads 4 are aligned. Next, as shown in FIG. 5(b), a tool 8 heated to a certain temperature is pressed against each lead 4 at a certain pressure for a certain period of time so as to be in even contact with each lead 4. As a result, as shown in FIG. 5(C), the bump 3 and the lead 4 are bonded by eutectic or diffusion,
That is, they are electrically and mechanically bonded.
以上述べたような構造を持つバンプ３とリード４とのボ
ンデ、ボンデを行えば、半導体チップ１の持つ能動機能
をリード４に取り出すことが可能となる。したがって、
例えば外部端子と電気的に配線されているパッド２を有
する絶縁基板上に、前記リード４を何らかの形式２例え
ば半田共晶などの方法により接続することによって半導
体チップ１の能動機能を外部端子によって取り出すこと
のできる半導体素子として取り扱うことが可能となる。By performing bonding between the bumps 3 having the structure described above and the leads 4, it becomes possible to extract the active function of the semiconductor chip 1 to the leads 4. therefore,
For example, the active function of the semiconductor chip 1 is taken out by the external terminal by connecting the lead 4 by some method 2 such as solder eutectic on an insulating substrate having a pad 2 which is electrically wired with an external terminal. This makes it possible to handle the device as a semiconductor device that can be used.
このように、従来のバンプ製造工程は工程数が多く、繁
雑であった。また第６図に示すように、ボンディング時
に半導体チップ１とツール８が平行になっていない場合
、部分的にリード４とパップ３のボンディングが行われ
ないという問題点があった。As described above, the conventional bump manufacturing process has a large number of steps and is complicated. Further, as shown in FIG. 6, if the semiconductor chip 1 and the tool 8 are not parallel to each other during bonding, there is a problem in that the bonding between the leads 4 and the pads 3 is partially not performed.
この発明は、上記のような問題点を解消するためになさ
れたもので、バンブ製造工程を減少し、スループッ１−
を向上させるとともに、確実なボンデ、（ングが実現で
きる半導体装置の製造方法を得ることを目的とする。This invention was made to solve the above-mentioned problems, and it reduces the number of bump manufacturing processes and increases the throughput by 1-1.
The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can achieve reliable bonding and bonding.
この発明に係る半導体装置の製造方法は、パッドが所要
のパターンで形成された半導体チップの一主面上に、前
記パッドと同位置、同寸法のスクリーン印刷用マスクを
位置合せし、その上から熱硬化性である導電性樹脂をス
クリーン印刷した後、スクリーン印刷用マスクを除去し
、半導体チップ上に形成された導電花樹ｎθのパターン
上面を半導体チップと平行になるように平面板で押し付
は均一な高さのバンプを形成した後、前記バンプ上に熱
処理によってリードを接続するものである。In the method for manufacturing a semiconductor device according to the present invention, a screen printing mask having the same position and size as the pads is aligned on one main surface of the semiconductor chip on which pads are formed in a desired pattern, and After screen printing thermosetting conductive resin, remove the screen printing mask and press the top surface of the conductive flower tree nθ pattern formed on the semiconductor chip with a flat plate so that it is parallel to the semiconductor chip. In this method, after forming bumps of uniform height, leads are connected to the bumps by heat treatment.
この発明においては、バンプ材質を導電性樹脂としたた
めに、スクリーン印刷によるバンプの形成が可能となる
ことからバンブ工程数が減少し、 −スルーブツトが向
上する。またバンプとリードのボッディングを熱処理に
よって行うので、確実な接続ができろ。In this invention, since the bump material is a conductive resin, the bumps can be formed by screen printing, which reduces the number of bumping steps and improves throughput. Additionally, the bump and lead bodding is heat treated to ensure a secure connection.
第１図（ａ）〜、（ｄ）はこの発明の一実施例を示すバ
ンプ形成方法の工程図である。まず、第１図（ａ）に示
すように、半導体チップ１の一主面上に形成されたパッ
ド２と同位置、同寸法のスクリーン印刷用マスク９を半
導体チップ１のパッド２上に位置合せする。次に、第１
図（ｂ）に示すように、導電性例１１旨１０をスクリー
ン印刷し、その後、第１図（Ｃ）に示すように、スクリ
ーン印刷用マスク９を除去した後、半導体チップ１と平
面板１１とが平行になるように導電性樹脂１０を押し付
は成熱処理することによって、第１図（ａ）に示すよう
に、均一な高さのバンプ１００を得ることができる。FIGS. 1(a) to 1(d) are process diagrams of a bump forming method showing an embodiment of the present invention. First, as shown in FIG. 1(a), a screen printing mask 9 having the same position and size as the pad 2 formed on one main surface of the semiconductor chip 1 is aligned over the pad 2 of the semiconductor chip 1. do. Next, the first
As shown in FIG. 1B, conductive example 11 is screen printed, and then, as shown in FIG. 1C, after removing the screen printing mask 9, the semiconductor chip 1 and the flat plate 1 By pressing the conductive resin 10 so that the conductive resin 10 is parallel to the conductive resin 10 and subjecting it to heat treatment, a bump 100 having a uniform height can be obtained as shown in FIG. 1(a).
第２図（ａ）〜（Ｃ）にこの発明により得られたバンプ
１００とリード４のボンデ゛、（ング方法の概略図を示
す。第２図（ａ）に示すように、バンプ１００とリード
４との位置合せを行う。次に、第２図（ｂ）に示すよう
に、゛バンプ１００の高さが均一であるので全てのバン
プ１００とリード４を接触させる。したがって、全ての
パン、プ１００とリード４が接触することになる。この
状態で熱処理を行えばバンプ１００を構成する導電性樹
脂１０は熱硬化性であるので、バンプ１００とリード４
は電気的・機械的に接続されることになる。FIGS. 2(a) to 2(C) show schematic diagrams of a bonding method for bumps 100 and leads 4 obtained according to the present invention.As shown in FIG. Next, as shown in FIG. 2(b), all the bumps 100 are brought into contact with the leads 4 because the heights of the bumps 100 are uniform. The bumps 100 and the leads 4 will come into contact with each other.If heat treatment is performed in this state, the bumps 100 and the leads 4 will come into contact with each other since the conductive resin 10 constituting the bumps 100 is thermosetting.
will be electrically and mechanically connected.
このようなバンブ構成およびボンディング方法によれば
、バンプ１００に導電性樹脂１０を用いているため電気
的に接続されていることになり、またバンプ高さをそろ
えて成熱処理し、バンプ１００とリード４の接触を行っ
てから本熱処理しているため、機械的にも接合されてい
ることになり、半導体デツプ１の能動機能をリード４に
よって確実に取り出すことができる。According to such a bump configuration and bonding method, since the conductive resin 10 is used for the bump 100, the bump 100 is electrically connected, and the bump 100 and the lead are connected by aligning the bump heights and performing heat treatment. Since the main heat treatment is performed after the contact (4) is carried out, the bonding is also mechanically performed, and the active function of the semiconductor deep 1 can be reliably extracted through the leads 4.
なお、上記実施例では、バンプ高さをそろえで成熱処理
しているが、バンプ高さをそろえながら成熱処理しても
よい。また粘度の充分高い導電性樹脂を用いることによ
って成熱処理を省略してもよい。In the above embodiment, the heat-forming process is performed with the bump heights being made the same, but the heat-forming process may be performed while making the bump heights the same. Further, the heating treatment may be omitted by using a conductive resin having a sufficiently high viscosity.
この発明は以上説明したとおり、所定のパターンでパッ
ドが形成されｒコ能動機能を備えた半導体チップの一主
面上に、このパッドと同位置、同寸法のスクリーン印刷
用マスクを位置合せし、その上から導電性樹脂をスクリ
ーン印刷し、次に、スクリーン印刷用マスクを除去した
後、導電性Ｖ１４詣の上面を平面板で押し付けて半導体
チップと平行で、かつ均一な高さを有するバンプを形成
し、さらに前記バンブ上に熱処理によりリードを接続す
るようにしたので、バンプを形成ず石工程数が減少する
とともに、スフレープ・−）ｌ・が向上する効果がある
。またバンプ高さが均一であり、バンプとリードの接続
にツールを用いないため、従来のように部分的に接続不
良が発生することもない等の効果を有するものである。As explained above, this invention involves aligning a screen printing mask having the same position and size as the pads on one main surface of a semiconductor chip having pads formed in a predetermined pattern and having an active function, A conductive resin is screen printed on it, and then, after removing the screen printing mask, the top surface of the conductive V14 is pressed with a flat plate to form bumps that are parallel to the semiconductor chip and have a uniform height. Since the bumps are formed and the leads are connected by heat treatment on the bumps, there is an effect that no bumps are formed, the number of stone steps is reduced, and the flake is improved. Furthermore, since the bump height is uniform and no tools are used to connect the bumps and leads, there are no local connection failures that occur in the conventional method.
第１図（ａ）〜（ｄ）はこの発明の一実施例の工程を示
す断面図、第２図（ａ）〜（ｅ）はこの発明におけろリ
ードの接続工程を示す断面図、第３図はバンプとリード
を用いた半導体チップの実装状態を示す断面図、第４図
（ａ）〜（ｄ）は従来のバンプの形成工程を示す断面図
、第５図は従来のリードの接続工程を示す図、第６図は
従来のリードの接続不良状態を示す断面図である。
図において、１は半導体チップ、２はパッド、９はスク
リーン印刷用マスク、１０は導電性樹脂、１１は平面板
、１０ｏはバンプである。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 （外２名）第１図
第２図
第３図
乙
第４図
第５図
ム
第６図
手続補正書（自発）
い
１、事件の表示 ｎ願昭６１−１２６５０３ 号２
、発明の名称 半導体装置の製造方法３、補正をす
る者
代表者志岐守哉
４、代理人
５、補正の対象
明細書の特許請求の範囲の欄２発明の詳細な説明の欄２
図面の簡単な説明の欄および図面６、補正の内容
（１）明細書の特許請求の範囲を別紙のように補正する
。
（２）明細書第５頁１２行の「平面板」を、［導電性樹
脂をはしくように表面処理を施した平面板」と補正する
。
（３）同じく第６頁１１行の「平面板」を、「導電性樹
脂をはじくように表面処理を施した平面板」と補正する
。
（４）同じ（第６頁１３行の「第１図（ａ）」を、「第
１図（ｄ）」と補正する。
（５）同じく第８頁７行の「平面板」を、「導電性樹脂
をはじくように表面処理を施した平面板」と補正する。
（６）同じく第９頁２行の「第５図」を、「第５図（ａ
）〜（Ｃ）」と補正する。
（７）第５図（ｂ）を別紙のように補正する。
以 上
２、特許請求の範囲
能動機能をもつ半導体チップと、前記半導体チップの能
動機能を取り出すために前記半導体チップの一主面上に
設けたバンプと、前記バンプと電気的・ｍ械的に接続さ
れるリードとからなる半導体装置の製造工程において、
所定のパターンでパッドが形成された半導体チップの一
主面上に前記パッドと同位置、同寸法のスクリーン印刷
用マスクを位置合せする工程、前記半導体チップのパッ
ド上に選択的にスクリーン印刷法により導電性樹脂を塗
布し、この導電性樹胞表面を導電性樹脂をはじ（ように
表面処理を施した平面板で押し付けて前記半導体チップ
と平行で、かつ同一高さを有するバンプを形成する工程
、前記バンプとリードとを位置合せした後、前記バンプ
とリードとを熱処理により接続する工程を含むことを特
徴とする半導体装置の製造方法。1(a) to (d) are cross-sectional views showing the steps of an embodiment of the present invention, and FIGS. 2(a) to (e) are cross-sectional views showing the steps of connecting the leads in the present invention. Figure 3 is a cross-sectional view showing the mounting state of a semiconductor chip using bumps and leads, Figures 4 (a) to (d) are cross-sectional views showing the conventional bump formation process, and Figure 5 is a conventional lead connection. FIG. 6, which is a diagram showing the process, is a sectional view showing a conventional lead connection failure state. In the figure, 1 is a semiconductor chip, 2 is a pad, 9 is a screen printing mask, 10 is a conductive resin, 11 is a flat plate, and 10o is a bump. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3 Figure O 2
, Title of the invention: Method for manufacturing a semiconductor device 3, Person making the amendment Representative Moriya Shiki 4, Agent 5, Claims column 2 of the specification to be amended 2 Detailed description of the invention column 2
Brief Description of Drawings, Drawing 6, Contents of Amendment (1) The claims of the specification are amended as shown in the attached sheet. (2) "Flat plate" on page 5, line 12 of the specification is corrected to "flat plate whose surface has been treated with conductive resin." (3) Similarly, "flat plate" on page 6, line 11 is corrected to "flat plate whose surface has been treated to repel conductive resin." (4) Same (correct “Fig. 1 (a)” on page 6, line 13 to “Fig. 1 (d)”). (5) Similarly, “flat plate” on page 8, line 7 is corrected as “Fig. (6) Similarly, ``Fig. 5'' on page 9, line 2, should be corrected to ``Fig. 5 (a).
) to (C)”. (7) Correct FIG. 5(b) as shown in the attached sheet. Above 2, the claimed scope includes a semiconductor chip having an active function, a bump provided on one principal surface of the semiconductor chip in order to take out the active function of the semiconductor chip, and a bump that is electrically and mechanically connected to the bump. In the manufacturing process of semiconductor devices consisting of leads to be connected,
A step of aligning a screen printing mask having the same position and size as the pads on one main surface of the semiconductor chip on which pads are formed in a predetermined pattern, and selectively applying a screen printing method onto the pads of the semiconductor chip. A process of applying a conductive resin and pressing the conductive resin onto the surface of the conductive resin using a flat plate that has been surface-treated to form bumps that are parallel to and have the same height as the semiconductor chip. . A method of manufacturing a semiconductor device, comprising the step of aligning the bump and the lead and then connecting the bump and the lead by heat treatment.
Claims (1)
能動機能を取り出すために前記半導体チップの一主面上
に設けたバンプと、前記バンプと電気的・機械的に接続
されるリードとからなる半導体装置の製造工程において
、所定のパターンでパッドが形成された半導体チップの
一主面上に前記パッドと同位置、同寸法のスクリーン印
刷用マスクを位置合せする工程、前記半導体チップのパ
ッド上に選択的にスクリーン印刷法により導電性樹脂を
塗布し、この導電性樹脂表面を平面板で押し付けて前記
半導体チップと平行で、かつ同一高さを有するバンプを
形成する工程、前記バンプとリードとを位置合せした後
、前記バンプとリードとを熱処理により接続する工程を
含むことを特徴とする半導体装置の製造方法。A semiconductor device comprising a semiconductor chip having an active function, a bump provided on one main surface of the semiconductor chip to take out the active function of the semiconductor chip, and a lead electrically and mechanically connected to the bump. In the manufacturing process, a screen printing mask of the same position and size as the pads is aligned on one main surface of the semiconductor chip on which pads are formed in a predetermined pattern, and a screen printing mask is selectively placed on the pads of the semiconductor chip. a step of applying a conductive resin to the surface by a screen printing method, pressing the surface of the conductive resin with a flat plate to form bumps parallel to the semiconductor chip and having the same height, and aligning the bumps and the leads. A method for manufacturing a semiconductor device, comprising the step of connecting the bump and the lead by heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12650386A JPS62283644A (en) | 1986-05-31 | 1986-05-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12650386A JPS62283644A (en) | 1986-05-31 | 1986-05-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62283644A true JPS62283644A (en) | 1987-12-09 |
Family
ID=14936819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12650386A Pending JPS62283644A (en) | 1986-05-31 | 1986-05-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62283644A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0274041A (en) * | 1988-09-09 | 1990-03-14 | Toshiba Corp | Formation of electrode of electronic component |
| JPH02150031A (en) * | 1988-11-30 | 1990-06-08 | Fujitsu Ltd | Method of forming solder bump |
| US5196371A (en) * | 1989-12-18 | 1993-03-23 | Epoxy Technology, Inc. | Flip chip bonding method using electrically conductive polymer bumps |
| WO1995005675A1 (en) * | 1993-08-17 | 1995-02-23 | Epoxy Technology, Inc. | Method of forming electrically conductive polymer interconnects on electrical substrates |
| US5611140A (en) * | 1989-12-18 | 1997-03-18 | Epoxy Technology, Inc. | Method of forming electrically conductive polymer interconnects on electrical substrates |
| US6110760A (en) * | 1998-02-12 | 2000-08-29 | Micron Technology, Inc. | Methods of forming electrically conductive interconnections and electrically interconnected substrates |
| US7152957B2 (en) * | 2002-12-18 | 2006-12-26 | Canon Kabushiki Kaisha | Recording device board having a plurality of bumps for connecting an electrode pad and an electrode lead, liquid ejection head, and manufacturing method for the same |
-
1986
- 1986-05-31 JP JP12650386A patent/JPS62283644A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0274041A (en) * | 1988-09-09 | 1990-03-14 | Toshiba Corp | Formation of electrode of electronic component |
| JPH02150031A (en) * | 1988-11-30 | 1990-06-08 | Fujitsu Ltd | Method of forming solder bump |
| US6138348A (en) * | 1989-12-18 | 2000-10-31 | Polymer Flip Chip Corporation | Method of forming electrically conductive polymer interconnects on electrical substrates |
| EP0506859B1 (en) * | 1989-12-18 | 1996-05-22 | Epoxy Technology, Inc. | Flip chip technology using electrically conductive polymers and dielectrics |
| US5611140A (en) * | 1989-12-18 | 1997-03-18 | Epoxy Technology, Inc. | Method of forming electrically conductive polymer interconnects on electrical substrates |
| US5879761A (en) * | 1989-12-18 | 1999-03-09 | Polymer Flip Chip Corporation | Method for forming electrically conductive polymer interconnects on electrical substrates |
| US5918364A (en) * | 1989-12-18 | 1999-07-06 | Polymer Flip Chip Corporation | Method of forming electrically conductive polymer interconnects on electrical substrates |
| US5196371A (en) * | 1989-12-18 | 1993-03-23 | Epoxy Technology, Inc. | Flip chip bonding method using electrically conductive polymer bumps |
| WO1995005675A1 (en) * | 1993-08-17 | 1995-02-23 | Epoxy Technology, Inc. | Method of forming electrically conductive polymer interconnects on electrical substrates |
| US6110760A (en) * | 1998-02-12 | 2000-08-29 | Micron Technology, Inc. | Methods of forming electrically conductive interconnections and electrically interconnected substrates |
| US6143639A (en) * | 1998-02-12 | 2000-11-07 | Micron Technology, Inc. | Methods of forming electrically conductive interconnections and electrically interconnected substrates |
| US6509256B2 (en) | 1998-02-12 | 2003-01-21 | Micron Technology, Inc. | Methods of forming electrically conductive interconnections and electrically interconnected substrates |
| US7152957B2 (en) * | 2002-12-18 | 2006-12-26 | Canon Kabushiki Kaisha | Recording device board having a plurality of bumps for connecting an electrode pad and an electrode lead, liquid ejection head, and manufacturing method for the same |
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