JPS62277819A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To improve the signal operating range of the 2nd deltasigma converter receiving an output voltage of the 1st operational amplifier by using the 1st comparator to compare a signal level outputted from an output terminal of the 1st operational amplifier and a ground potential thereby applying specific selection. CONSTITUTION:The titled converter is provided with the 1st delta-sigma converter 100 having the 1st-3rd switched capacitor circuits, the 1st operational amplifier 117, the 1st comparator 118 and the 1st data flipflop circuit 119 and the 2nd delta-sigma converter 200 having the 4th switched capacitor whose input terminal T4 is connected to an output terminal 117c of the 1st operational amplifier 117, the 5th switched capacitor whose input terminal Ts is connected to a reference voltage source 2, the 2nd operational amplifier 212, the 2nd comparator 213 and the 2nd data flip-flop 214. Thus, the output potential of the 1st operational amplifier 117 is increased/decreased by a value corresonding to the output voltage of the reference voltage source 2 and the operating range of the signal in the 2nd delta-sigma converter 200 receiving the output voltage is improved.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention provides a plurality of Δ-
A/D converter i1 composed of a Σ converter! ! ! It is related to vessels.

(Prior art) Fig. 2 is a circuit diagram showing a general Δ-Σ converter. In Fig. 2, ■ is an analog signal input terminal, 2 is a reference voltage source, 3 to 10 are switches, 11 13 is a capacitor, 14 is an operational amplifier, 15 is a comparator, 16 is a data flip-flop, 17 is an output terminal, switches 3 to 6 and capacitor 1
1 constitutes one switched capacitor circuit (hereinafter referred to as "upper switched capacitor circuit"), and switch 7
10 and capacitor 12 constitute another switched capacitor circuit (hereinafter referred to as "lower switched capacitor circuit").

The switch 3.6 is closed at the same timing during a fixed period (sample period 31I'l), and the switch 4.5 is closed at a timing that does not overlap with the switch 3.6.

Since the switches 3 to 6 operate as described above, the analog signal input to the analog signal input terminal 1 is sampled as a charge in the capacitor 11 when the switch 3 is opened.
The signal is transferred to the capacitor 13 when the switches 4 and 5 are closed. The amount of charge in the capacitor 13 becomes the output voltage of the operational amplifier 14, and is compared with the ground potential by the comparator 15.

The output of the comparator 15 is held by the data flip-flop 1G from this point on during the sampling period.

The lower switched capacitor circuit is controlled at approximately the same timing as the upper switched capacitor circuit, but the timing of the switch 7.8 is controlled by the data flip-flop 16.
It differs from the upper switched capacitor circuit in that it is switched by the output of the upper switched capacitor circuit. That is, when the output level of the data flip-flop 16 is at a level indicating that the output potential of the operational amplifier 14 is higher than the ground potential,
Switches 7 and 10. By closing switches 8 and 9 at the same timing, the output voltage of reference voltage source 2 V rat
The output voltage of the operational amplifier 14 is lowered by injecting a charge corresponding to the amount into the capacitor 13. Conversely, data flip-flop 16
When the output level of the operational amplifier 14 is at a level indicating that the output potential of the operational amplifier 14 is lower than the ground potential, the switches 7 and 9
．． By closing the switches 8 and 10 at the same timing, charge corresponding to the output voltage V ref of the reference voltage source is extracted from the capacitor 13 and the output voltage of the operational amplifier 14 is increased.

The circuit shown in Figure 2 converts the analog input voltage with the maximum absolute value to ±V when the capacitors 11 and 12 are set to the same value.
It operates as an oversampling type A/D converter, that is, a Δ-Σ converter, which converts the data into a 1-bit code string (appearing at the output of the data flip-flop 16) representing the magnitude of rat.

Next, an explanation will be given of the operation when the values [11, 12, and 13 are set to the same value. When the output potential of the operational amplifier 14 at a certain sample point is slightly lower than the ground potential, and the analog input voltage at the next sample point is +■,,□, the output of the operational amplifier 14 at the latter sample point is The voltage is determined by comparator 15. +Vref (the voltage value of the feedback signal) added by the data flip-flop and the analog input voltage result in a value slightly lower than +2 V, . The same applies to the negative side, and the output amplitude of the operational amplifier 14 has a peak value of 2 with respect to the ground potential.
It becomes less than V, .

The transfer characteristics of the S-order Δ-Σ converter will be explained.

First, the Z conversion of the analog input voltage is
The output of +V raf or 1
Let q be the Z transformation of the quantization error that is added when it is determined that
Let the transformation be y. The operational amplifier 14 receives the analog input voltage and the feedback signal (+■..., or -v r
-r), y= (x Z-'y)/ (I Z-')+q,
'． y=x+ (1-Z-')q As can be seen from the above equation, in the Δ-Σ converter, the quantization error q (white) that is randomly added at the time of quantization appears as a differentiated output. Noise components within a signal band sufficiently lower than the reciprocal of the period (sampling frequency) are reduced due to differential characteristics.

In A/D converters, multi-stage converters using a plurality of Δ-Σ converters have been proposed in order to further reduce noise components within the above signal band (Reference: IEICE General National Conference 60). FYN0.603).

FIG. 3 is a circuit diagram showing an example of a conventional multi-stage converter, in which 20.30 is a Δ-Σ converter, 40 is a register that delays the signal by one sample, 50 is a differentiation circuit, 60 is an adder, 70 is an output terminal, and the Δ-Σ converter 20 is an operational amplifier 21. It is composed of a comparator 22, a data flip-flop 23, and two switched capacitor circuits, and has a Δ-
The Σ converter 30 is an operational amplifier 31. Comparator 32. It is composed of a data flip-flop 33 and two switched capacitor circuits.

The Δ-Σ converter 30 performs Δ-Σ conversion on the output signal of the operational amplifier 21 forming the Δ-Σ converter 20.

The converted signal is differentiated by a differentiating circuit 50, and an adder 60
is added to the output value of the Δ-Σ converter 20 one sample before. Here, the values of the quantization errors added by the comparators 22.32 are respectively ql and q2, the output value of the operational amplifier 21 is y3, and the output value of the Δ-Σ converter 20.30 is yl.
, y2, and the output value of the adder 60 is y4, then Y 1 =x+ (1-Z-') Q 1y3=x-Z
-'ql y2=y3+ (1-Z)q2 -X-Z-'Q 1 + (1-Z)q2y4=yl
Z + (1-Z)y2 -x+ (l-Z-')2q 2 , and the output terminal 70 has a random quantization error q
2 appears as second-order differentiated, the noise component within the signal band becomes even smaller than the noise component in the Δ-Σ converter shown in FIG.

(Problem to be solved by the invention) However, in the conventional multistage converter described above, the second
As mentioned in the explanation of the Δ-Σ converter in the figure, the output amplitude of the operational amplifier is twice the reference voltage, and this is converted into a Δ-Σ converter.
Therefore, the Δ-Σ converter 30 that performs Σ conversion uses a reference voltage that is twice that of the Δ-Σ converter 20, and the output amplitude of the operational amplifier 31 is set to the reference voltage (maximum human power amplitude) of the Δ-Σ converter 20. It is necessary to operate as a quadrupled power supply, and the input signal amplitude has to be reduced when the power supply voltage is constant.

That is, there is a problem in that it is more susceptible to the influence of circuit noise and it is difficult to obtain a high S/N ratio.

[Means for solving problems]

In order to solve these problems, the present invention provides a first Δ- a Σ converter, a fourth switched capacitor whose input terminal is connected to the output terminal of the first operational amplifier, a fifth switched capacitor whose input terminal is connected to the reference voltage source, a second operational amplifier, and a fourth switched capacitor whose input terminal is connected to the reference voltage source. A second Δ-Σ converter having two comparators and a second data flip-flop is provided.

〔Example〕

An embodiment of an A/D converter according to the present invention is shown in FIG. 1 is an analog signal input terminal, 2 is a reference voltage source, 100
is the first Δ-Σ converter, 200 is the second Δ-Σ converter,
300 is a differentiation circuit, 400 is an addition circuit, 500 is an output terminal, 101 to 112 and 201 to 208 are switches,
113-116 and 209-211 are capacitors, 117 and 212 are first and second operational amplifiers, and 117a.

'17b, 117c are an inverting input terminal, a non-inverting input terminal, an output terminal, and 212a of the first operational amplifier.

212b, 212c are inverting input terminals, non-inverting input terminals, and output terminals of the second operational amplifier; 118 and 213 are first and second comparators; 119 and 214 are first and second data flip-flops; Tl , T2 and T
3 is the first. The input terminals of the second and third switched capacitor circuits, T4 and T5, are the input terminals of the fourth and fifth switched capacitor circuits. switch 101
.about.104, capacitor 113 constitute a first switched capacitor circuit, and switches 105.about.108. Capacitor 114 constitutes a second switched capacitor circuit, and switched capacitors 109 to 112 . Capacitor 115 constitutes a third switched capacitor circuit. In addition, the switch 201~
204. Capacitor 209 constitutes a fourth switched capacitor circuit, and switches 205 to 208 . Capacity 210 is the fifth
The switch constitutes a chitocapacitor circuit.

Next, the operation of the A/D converter configured as described above will be explained. Switches 101 to 104 and capacitor 113 that constitute the first switched capacitor circuit sample the input analog signal and transfer it to capacitor 116 by the same operation as switches 3 to 6 and capacitor 11 in FIG. The data flip-flop 119 holds the output signal of the comparator 118 at this point for the remainder of the time taken to transfer charge from the capacitor 113 to the capacitor 116 during the sampling period (usually half the sampling period). At t2, one of the switches 108 and 112 is closed as follows. That is, at time t1, switches 106, 107, 109 and ILL are closed, and the capacity is 1.
14 and 115 are given charges corresponding to zero and the reference voltage, and when the output level of the data flip-flop 119 is at a level indicating that the output potential of the operational amplifier 117 was higher than the ground potential at the end of time t1. teeth,
By closing the switches 110 and 112, the output voltage of the reference voltage source 2 1. ．． The output potential of the operational amplifier 117 is lowered by injecting a charge corresponding to the amount into the capacitor 116. Conversely, when the output level of data flip-flop 119 is at a level indicating that the output potential of operational amplifier 117 was lower than ground potential at the end of time t1, switch 106
, 108, the output voltage of the reference voltage source 2 ■1. ．． The output potential of the operational amplifier 117 is raised by extracting the charge corresponding to the amount from the capacitor 116. In this case, time t
Since the feedback signals for the addition of analog input voltages performed at 1 are added at time t2, the maximum output amplitude of operational amplifier 117 at the end of time t2 is ±V rat.

However, the capacitances 113 to 116 have the same value.

The Δ-Σ converter 200 performs the same operation as the Δ-Σ converter shown in FIG. 2, and performs Δ-Σ conversion on the output signal of the operational amplifier l17 at time t2. In this case, since the maximum amplitude of the input voltage is force ■□, the reference voltage is also ■, ..., f, and the output amplitude of the operational amplifier 212 does not exceed ±2V, ..., f.

The transfer characteristic of the A/D converter in Fig. 1 is A in Fig. 3.
Using the output value used in the /D converter, y l =x+ (1-Z-') q 1y3=yl
-ql-yl=-ql y2=y3+ (1-Z-')q2 =-ql+(1-Zpost)q2 y4=yl+ (1-Z-')y2 =x+ (1-Z-')"q 2, and the same characteristics as the A/D converter of FIG. 3 can be realized by improving the output amplitude of the operational amplifier 212 of the Δ-Σ converter 200 to 1/2.

〔Effect of the invention〕

As explained above, the present invention compares the level of the signal output from the output terminal of the first operational amplifier with the ground potential using the first comparator, and based on the comparison result, the level of the signal output from the output terminal of the first operational amplifier is compared with the ground potential. By selecting the operation of the third suinotito capacitor circuit, the output potential of the first operational amplifier can be increased or decreased by an amount corresponding to the output voltage of the reference voltage source, and the maximum output voltage of the first operational amplifier can be increased or decreased by an amount corresponding to the output voltage of the reference voltage source. can be reduced to half that of the conventional one, which has the effect of improving the operating range of the signal in the second 8-Σ converter to which the output voltage of the first operational amplifier is input.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of an A/D converter according to the present invention, FIG. 2 is a circuit diagram showing a general Δ-Σ converter,
FIG. 3 is a circuit diagram showing a conventional A/D converter. 1...Analog signal input terminal, 2...Reference voltage source, 100, 200...Δ-Σ converter, 101-1
12.201~208...Switch, 113~11
6,209~211... Capacity, 117,212...
...Operation amplifier, 117a, 212a...Inverting input terminal, 117b, 212b...Non-inverting input terminal, 1
17c, 212c, 500...Output terminal, 118°213...Comparator, 119.214...Data flip-flop, 300...Differentiating circuit, 400...
...addition circuit, T1. T2. T3, T4. T5...
・Input terminal.

Claims (1)

[Claims] A that is equipped with two Δ-Σ converters, one transforms the analog input signal into Δ-Σ, the other transforms the quantization error of the former into Δ-Σ, and calculates the output signals of both to obtain an output digital signal.
/D converter, a first Δ-Σ converter having first to third switched capacitor circuits, a first operational amplifier, a first comparator, and a first data flip-flop;
a fourth switched capacitor whose input terminal is connected to the output terminal of the first operational amplifier; a fifth switched capacitor whose input terminal is connected to the reference voltage source; a second operational amplifier; and a second comparator. a second Δ-Σ converter having a second data flip-flop, and the first to third switched capacitor circuits use a switch to connect one terminal of the capacitor to the input terminal and the ground terminal at non-overlapping timings. and the other terminal of the capacitor is alternately connected to the inverting input terminal and the ground terminal of the first operational amplifier at timings that do not overlap with each other, and the first switched capacitor circuit has an input terminal that receives an analog signal. The second and third switched capacitor circuits have their input terminals connected to a reference voltage source, and the first operational amplifier has a capacitor connected between an inverting input terminal and an output terminal, and has a non-inverting input. The terminal is connected to a ground terminal, and the first comparator compares the level of the signal output from the output terminal of the first operational amplifier with the ground potential, and depending on the result, the second and third operational amplifiers are connected to the ground potential.
An A/D converter that selects an operation of a switched capacitor circuit.