JPS62275396A - Eeprom device - Google Patents

Abstract

PURPOSE:To avoid miserasing or miswriting actions due to an unfixed level, etc., of an internal circuit set immediately after a power supply is applied, by providing a voltage detecting circuit and keeping forcibly a timer circuit under a reset state until the power supply voltage reaches a prescribed level. CONSTITUTION:It is feared with a timer circuit that the output V4 of a counter circuit BC4 set at the final stage is set at a high level in an extremely short period during which the external control signal reaches a normal level after application of a power supply since the initial values of binary counters BC1-BC4 are unfixed immediately after application of the power supply. In this case, however, the output signal Vcs of a voltage detecting circuit is set at a low level when the power supply is applied. Thus a node NA can be set at a high level and therefore, the power supply voltage can keep an oscillation circuit OSC and the circuits BC1-BC4 under the reset states for a period during which the working of an internal circuit and the internal signal are set under the normal states. Thus it is possible to avoid undesired miserasing and miswriting actions immediately after the power supply is applied.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] This invention is an EEPROM (Electrically Erasable Programmable Read Only Memory).
Regarding devices, for example, if the peripheral circuits are CMOS
The present invention relates to a technique that is effective for use in devices configured with (complementary MOS) circuits.

[Conventional technology]

Semiconductor nonvolatile memory elements that can electrically write and erase data, such as MNOS (metal nitride oxide semiconductor), are made of a relatively thin silicon oxide film and a relatively thick silicon nitride film formed on it. Insulated gate field effect transistor (hereinafter simply referred to as MNO
(referred to as an S transistor), and can electrically write and erase stored information. The MNOS technology is described in, for example, Japanese Patent Laid-Open No. 156370/1983.

In an erased state or a state in which no stored information is written, the threshold voltage of the N-channel MNO5 transistor is a negative voltage. In order to write or erase stored information, a high electric field is applied to the gate insulating film so that carrier injection occurs due to a tunneling phenomenon.

According to the above publication, the MNOS transistor is formed in a P-type well region formed in an N-type semiconductor substrate. Furthermore, MOSFETs constituting the peripheral circuit are formed in a well region that is independent of the well region for the MNOS transistor.

In a write operation, for example, the ground potential Ov of the digging circuit is applied to the well region serving as the base gate of the MNOS transistor, and a high voltage for writing is applied to the gate. In the source region and drain region,
Depending on the information to be written, a low voltage of 0V or a high voltage of the writing level is applied. At this time, a channel is induced in the channel forming region of the MNOS transistor, that is, in the surface of the silicon region between the source region and the drain region, in response to the positive high voltage of the gate. The potential of this channel becomes equal to the potential of the source and drain regions. When a voltage of ov is applied to the source region and the drain region as described above, a high electric field corresponding to the high voltage of the gate acts on the gate insulating film. As a result, electrons as carriers are injected from the channel into the gate insulating film due to a tunneling phenomenon. This allows M.N.O.
The threshold voltage of S changes, for example, from a negative voltage to a positive voltage.

When a high voltage at a write level is applied to the source region and the drain region, the potential difference between the gate and the channel is reduced to a small value. Such a small voltage difference is insufficient to cause electron injection by tunneling. Therefore, the threshold voltage of MNOS does not change.

In addition, in the case of erasing, while applying Ov to the gate of the MNOS transistor, a positive high voltage is applied to the well region serving as the base gate to cause a tunnel phenomenon in the reverse direction and transfer electrons as carriers to the base gate. This is done by reverting to

[Problem that the invention seeks to solve]

In a conventional EEPROM, in one write cycle, a write operation is performed only on selected memory cells among memory cells formed in the same memory array. Therefore, when performing a multi-bit write operation, each bit is written individually, so the write time becomes longer.

Therefore, the inventor of the present application first provided a latch circuit in a data line in a memory array configured by arranging memory cells including MNOS transistors in a matrix, and held information read out by a word line selection operation. Then, by a series of operations consisting of a first write operation in which rewrite information is sent to this latch circuit, and a second write operation in which after the erase operation, actual write is performed to the MNOS transistor according to the information held in the latch circuit. , we have considered performing a write operation on a plurality of memory cells coupled to one word line.

In this case, in order to input an arbitrary write data signal in the first write operation, we considered providing a timer circuit for the write system control circuit to identify the end of the operation. That is, each time data is input, the timer circuit is reset and restarted, and write data that is input one after another is captured. If the next write data is not input within a certain period of time set by the timer circuit, in other words, if the time amplifier signal is output from the timer circuit, it is assumed that the data to be written has been completed. , the reset input is prohibited and the next erase operation is started. However, it has been found that when such a timer circuit is provided, the following new problem arises. In other words, immediately after the power is turned on, the signal level of the counter circuit that constitutes the timer circuit and the internal circuit that forms its manual control signal becomes unstable, and when the timer circuit becomes operational, a time-up signal is output. ,
If a series of operations including an erase operation and a second write operation, which are the next operation steps, are automatically performed, there is a risk that the stored information will be destroyed.

The purpose of this invention is to realize an EEPR that prevents erroneous erasing or erroneous writing when the power is turned on while realizing high-speed writing operation.
Our objective is to provide an OM device.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a latch circuit that holds the read signal and information held by this latch circuit are attached to data lines in a memory array in which memory cells including semiconductor non-volatile memory elements that can be electrically written and erased are arranged in a matrix. Accordingly, a level conversion circuit is provided which transmits the voltage necessary for a write operation to a data line, and upon receiving an operation mode signal supplied from an external terminal, converts the memory element connected to the addressed word line during a write operation. a first write operation in which the stored information in the latch circuit is misplaced in write data after the stored information is taken into the latch circuit; and an erase operation in which the stored information in the storage element coupled to the addressed word line is erased; The 21st write operation of writing to the memory element connected to the word line according to the stored information of the latch circuit is performed in a time-series manner, and the trigger signal is used to reset and restart the operation, and the time-up output A timer circuit that determines the end of the first write operation and shifts to the erase operation is forced into a reset state when the power supply voltage is below a predetermined voltage.

[For production]

According to the above means, when the power is turned on, the timer circuit that determines the end of the first write operation is placed in a reset state during a period when the internal circuit operates unstablely.
Unwanted destruction of stored information due to the erase operation or the second write operation can be prevented.

〔Example〕

FIG. 4 shows a circuit diagram of a main part of an embodiment of an EEFROM device to which the present invention is applied.

The EEFROM device of this embodiment includes an address buffer (not shown), an X decoder X-DCR, and a Y decoder Y-D.
It includes an address selection circuit consisting of a CR, a circuit for forming voltages for write/erase operations in response to output signals and control signals of the address selection circuit, and a control circuit C0NT for forming the control signals. There is.

The EEPROM device has a relatively low power supply voltage Vcc, such as +5V supplied from the outside, although it is not particularly limited.
It is operated by a high negative voltage -vpp, such as -12v. X address decoder X- that constitutes the above selection circuit
The DCR and the like are composed of CMO3 circuits. C.M.O.
The S circuit operates by being supplied with a relatively low power supply voltage Vcc such as +5V. Therefore, the level of the selection/non-selection signal formed by the address X decoders X-DCR and Y-DCR is set to +5V, and the low level is set to OV, which is the ground potential of the beam circuit. .

Although the element structure itself constituting the illustrated EEPROM device is not shown because it is not directly related to the present invention, its outline is as follows.

That is, the entire illustrated device is formed on a semiconductor substrate, such as one made of N-type single crystal silicon.

The MNOS transistor is of an N-channel type, and is formed on a P-type well region or a P-type semiconductor region formed on the surface of the semiconductor substrate. An N-channel MOSFET is similarly formed on the P-type semiconductor region.

A P-channel MOSFET is formed on the semiconductor substrate.

One memory cell can be one MN, although it is not particularly limited.
OS transistor and two MOs connected in series with it
It is composed of SFET. In one memory cell, one MNOS transistor and two MOSFETs have a so-called stacked gate structure in which, for example, the gate electrode of the MNOS transistor partially overlaps the gate electrode of each of the two MOSFETs. As a result, the size of the memory cell is reduced to one MNOS transistor and two MOSFETs that make up the memory cell.
The structure is substantially integrated with the ET, resulting in miniaturization.

Although not particularly limited, each memory cell is formed in a common well region. CM like X decoder, Y decoder
The N-channel MOSFET for configuring the O3 circuit is formed in a P-type well region that is independent from a common P-type well region for each memory cell.

In this structure, the N-type semiconductor substrate constitutes a common base gate for a plurality of P-channel MOS FETs formed thereon, and is set to the power supply voltage VCC level of the circuit. N-channel M for configuring CMO3 circuit
The well region as the body gate of the OS FET is maintained at circuit ground potential O volts.

In FIG. 1, memory array M-ARY includes a plurality of memory cells arranged in a matrix. One memory cell consists of an MNOS transistor Q22, its drain and a data line (bit line or shift line) D.
MO3FETQ2 for address selection provided between
1 and an isolation MO3FET Q23 provided between the source of the MNO3I transistor Q22 and the common source line, although this is not particularly limited. Note that when the stacked gate structure as described above is adopted, MN
MO in the channel formation region of OS transistor Q22
The channel forming regions of SFETQ21 and Q32 are directly adjacent to each other.

Therefore, MNO3I - the drain of transistor Q22,
Source is to be understood as a term of convenience.

The gates of the address selection MO3FETQ21, etc. of the memory cells arranged in the same two rows are commonly connected to the first word line Wll, and the gates of the corresponding MNOS transistors Q22, etc. are connected to the second word line W12. Commonly connected. Similarly, the gates of the other memory cell address selection MOSFETs and MNOS transistors arranged in the same row are connected to the first word line W21. W
22 in common.

MO for selecting addresses of memory cells arranged in the same column
The drains of SFETQ21 and the like are commonly connected to the data line Di. Similarly, the drains of the address selection MO5FETs of other memory cells arranged in the same column are commonly connected to the data line D2.

The source of the isolation MO3FET Q23 in each memory cell is shared, forming a common source line C8.

The memory array M-ARY of this embodiment is operated by the following potential.

First, in a read operation, the potential Vw of the well region WELL is set to a low level equal to the ground potential of the y' circuit, 0 volts. The common source NIAcs is a 0 isolation MO3FE which is set to a low level substantially equal to the ground potential.
The control line coupled to the gate of TQ23 connects these MO
In order to turn on the 3FET Q23, the voltage is set to a high level equal to the power supply voltage Vcc. The second words IW12 to W22, each coupled to the gate electrode of the MNOS transistor, are at a potential equal to the beam ground potential, that is, a voltage between the high and low threshold voltages of the MNOS transistor. . The word line to be selected from among the first word lines Wll to W21 is set to a selection level equal to the power supply voltage Vcc or to a high level, and the remaining word lines, that is, unselected word lines are equal to the ground potential. It is set to a non-select level or low level. Data line DI to D2
A sense current is supplied to the data line to be selected. If the MNOS transistor in the memory cell selected by the first word line has a low threshold voltage, then that memory cell forms a current path to the data line to which it is coupled. If the MNOS transistor in a cell has a high threshold voltage, the memory cell will form virtually no current path, so reading data in the memory cell will be
This is done by detecting the sense current.

In the write operation, the well region WELL is V-
A negative high voltage equal to Vpp is applied to the isolation MO3.
The control lines coupled to the gate electrodes of FETs Q23 are brought to a high negative potential to turn those MO3FETs Q23 off. The first word lines Wll to W21 are
It is set to a non-select level or low level equal to the beam ground potential. One of the second word lines W12 to W22 is brought to a selection level such that y'ta is equal to the voltage Vcc, and the remaining second word lines are brought to a negative high voltage close to the voltage -Vpl). be done. Depending on the data to be written into the memory cell, the data line
High level or negative voltage equal to voltage Vcc -
It is set to a low level with a negative high voltage close to vpp.

In the erase operation, the well region WELL and the common source line C8 are set to an erase level equal to the power supply voltage Vcc or to a high level. The first word lines 1WIL to W21 and the second word lines W12 to W22 are
For erasing, basically each circuit's power supply voltage Vc
c has a level equal to 1' and a level substantially equal to the voltage -vpp. However, according to this embodiment, the levels of the first and second word lines are determined so that erasing of memory cells in each memory row is possible, although this is not particularly limited. The first word line corresponding to the memory row that needs to be erased among W11 to W21 is set to an erase level equal to the power supply voltage Vcc, and the first word line corresponding to the memory row that needs to be erased is The corresponding first word line is set to a non-erasing level such as the ground potential of the beam circuit.The second word line of the second word lines W12 to W22 corresponding to the first word line set to the erasing level is
The word line is set to an erase level such that V' is equal to the negative voltage -vpp, and the second word line corresponding to the first word line set to the non-erased level is set to a non-erasing level such that is equal to the power supply voltage Vcc. set to erasure level.

According to this embodiment, as described above, the power supply voltage VCC is applied to the well region, that is, the base gate of the MNOS transistor.
A configuration is adopted in which the information stored in each MNOS transistor is erased by applying this voltage.

On the other hand, the O3FE between N channels that constitutes the CMO3 circuit
The body gate of T is required to be brought to a potential, for example O volts, independently of the body gate of the MNO3I-transistor. Therefore, as mentioned above, the base gate of each memory cell, that is, the semiconductor region WELL in which the memory array M-ARY is formed, is an N-channel MOS F constituting peripheral circuits such as an X decoder and a Y decoder.
It is electrically isolated from the semiconductor region (well region) in which the ET is formed.

If you want to enable partial erasure of the memory array M-ARY, you can form each memory cell in an independent well region, or form memory cells arranged in the same row or column in a common well region. You can do it. In this embodiment, as described above, the entire memory cell, ie, the memory array M-ARY, is formed in one common well region WELL.

The first and second word lines Wll to W21 and W12
to W22 are each driven by an X decoder X-DCR. Although not particularly limited, the X-decoder X-DCR consists of a plurality of unit decoder circuits in one-to-one correspondence with the memory rows of the memory array M-ARY. One unit decoder circuit is composed of, for example, a NOR gate circuit N0RI that receives an address signal, a gate circuit G, and a level conversion circuit LVC as shown in the figure.

At least during the read operation, the gate circuit G
The output of the corresponding NOR gate circuit is
The first word line is transmitted to the word line, and the first word line is made to have a level substantially equal to the ground potential of the circuit in a write operation, regardless of the output of the corresponding NOR gate circuit. According to this embodiment, in order to enable the selective erase operation described above, the gate circuit G connects the output of the corresponding NOR gate circuit to the corresponding first word line during the read operation as well as during the erase operation. configured to transmit. A specific circuit example of the gate circuit G is not directly related to the present invention, so a description of the specific circuit will be omitted.

During a write operation, if the output of the corresponding NOR gate circuit is at a high selection level, the level conversion circuit LVC changes the second word line to a selection level equal to the power supply voltage VCC in response to the output of the NOR gate circuit. If the output is a low level non-selection level, the second
The word line is brought to a non-select level equal to a negative voltage -vpp. During an erase operation, if the output of the corresponding NOR gate circuit is at a high selection level, the level conversion circuit LVC changes the second word line to an erase selection level equal to the negative voltage -vpp in response to the output of the NOR gate circuit. If the output is at a low non-selection level, the second word line is accordingly set to an erase non-selection level equal to the power supply voltage VCC.

The gates of the isolation MOSFET Q23 and the like are commonly coupled to a control line to which a control voltage Vig generated by a control voltage generation circuit Vtg-G is supplied.

The sources of these isolation MO5FETQ23 and the like are shared and constitute a common source line C3. The control voltage Vig supplied to the separation MO3FETQ23 is
In a write operation to the MNOS transistor as described later, the word line to which the memory cell to be selected among the second word lines W21 and W22 is coupled is set to a high level (5V), and the well region WE as a base gate is set to a high level (5V).
LL is set to about -12V, and the data line, for example, D
When I is set to about -1Ov, the above MO3FE'['Q
23 is brought to a low potential, such as about -IQV, to turn it off. As a result, even if the data line D2 is +5■
Even if the data line D2 is set to a high level, current is prevented from flowing from the data line D2 to the memory cell to which the above writing is to be performed.

The common source line CS is coupled to the output terminal of the common source vA driver circuit DVR.

Basically, the drive circuit DVR can drive the common source line CS to the level of the power supply voltage Vcc during an erase operation, and can also drive the common source line C3 to the ground potential of the circuit during a read operation. By this, when the well region WELL is brought to the power supply voltage Vcc level in the erase operation, the MO
It is possible to prevent the junction between the electrode coupled to the common source line C3 of SFETQ23 and the well region WELL from being biased in the forward direction. Furthermore, a current path required for a read operation can be formed between the common source line C3 and the ground point of the circuit.

The drive circuit DVR is not particularly limited, but as shown in FIG. MOS connected in parallel between
It consists of FETs Q27 and Q28 and a CMOS inverter circuit IV.

The above MO3FETQ27. The control i1 signal er is supplied to the gate of Q2B(7), and the control signal er is inverted by the inverter circuit IV and supplied to the gate of MO5FETQ26. As a result, the above MO3FET
Q27. Q2B and Q26 are turned on/off in a complementary manner depending on the level of the control signal or. control signal o
Basically, r is MO5FETQ during erase operation.
26 is turned on, and MO3FETQ27 and Q
To turn on 28, it is set to a high level equal to the power supply voltage Vcc, and during read and write operations, is set to a low level equal to 10 volts. According to this embodiment, the control signal er corresponds to the timing of change in the potential of the well region so as to prevent the PN junction formed by the MOSFET etc. formed in the well region WELL from being put into a forward bias state. and its output timing is controlled.

According to this embodiment, the second word line W12. MO3FETQ2 is connected between W22 and common source vAC8, respectively.
4. Q25 is provided. These MO3FETQ
24. Q25 is switch-controlled by control signal 7r/we. Although not particularly limited, the control signal or/we
Its high level is set to a level equal to the power supply voltage Vcc, and its low level is set to a level equal to the ground potential. MO3FETQ24. Q25 is the second word & IW12. It is made into a P-channel type so that it can be turned off well even when a negative potential is applied to W22. Switch MO3FETQ24. During a read operation, transistors Q25 and the like are turned on so as to short-circuit the gates of the MNOS transistors Q22 and the common source line C3 so that they are at the same potential. These switches MO3FETQ
24. Q25 is provided between each second word line and the common source line C3 for the following reason.

That is, MO3FETQ27 in the drive circuit DVR
．． Q28 is turned on when the control signal or is set to a low level equal to zero volts during a read operation. In this case, MO3FETQ27. Q28, although they are connected in parallel as shown,
As a result, the potential of the common source line C8, which has a non-negligible on-resistance, increases due to the current flowing through it during reading. In particular, MO3FETQ27. Q2B is P
When consisting of channel type, these MO3FETQ2
7. Since Q28 does not have the driving ability to change the common source line CS to the ground potential of the circuit, the potential of the common source line C8 rises by a large amount. That is, the current transfer electrodes of MO3FETs Q27 and Q28 coupled to the common source line C8 act as source electrodes for the positive potential applied via the memory array M-ARY and the common source lcs. , common source! When lAc5 reaches a potential below its respective threshold voltage, it is substantially turned off. Such an increase in the potential of the common source vAC8 causes an increase in the effective threshold voltage due to the substrate effect of the MNOS transistor, and reduces the conductance of the MNOS transistor, which should have a low threshold voltage. In other words, the read current flowing through the MNOS transistor with a low threshold voltage is reduced. Short circuit MO3FETQ above
24. Q25 is connected to each second word line W1 during a read operation.
2. The W22(7) potential is made substantially equal to the potential of the common VAC3, thereby preventing an increase in the effective threshold voltage of the MNOS transistor.

Well region W where the memory array M-ARY is formed
A control voltage Vw-G generated by a control voltage generation circuit Vw-G is supplied to ELL.

This voltage Vw is set to a negative high voltage of about -12V during a write operation, set to a potential of about +5V during an erase operation, and set to about Ov at other times.

According to this embodiment, in order to speed up the read operation, each data line D1 . D2 has data line DI, and D2 is connected to column switch MO3FET.
Q29. N-channel MO electrically isolated from Q30
5FETQ31. Q32 is provided. That is, the MO3FETQ31 . N-channel MO as Q32 etc. and Y gate (column switch) circuit C-5W
SFETQ29. Q10, etc. are provided in series. MO5FETQ31 for the above data line separation. Q3
2 is formed in the same P-type well region WELL as the MNOS transistor.

These MO3FETQ31. A control voltage Vc generated by a control voltage generation circuit Vc-G is applied to the gate of Q32.
is supplied. This control voltage Vc is set to a negative high voltage such as -12V only in the write operation state, and is set to a high level such as the power supply voltage Vcc during other read and erase operation states. This allows the MO3FETQ31. Q32 is turned off during the write operation state. In addition, the above MO3FETQ3
1, Q32 is the well region WE in the erase operation state.
When LL is set to a high level such as power supply voltage Vcc, it is turned off. Therefore, the above MO3FET
Q31. Q32 is turned on only during read operation. As a result, during the write operation, the MO3FETQ31, Q32, etc. are turned off, so even if the potential of the data line is set to a negative high voltage, the columns 4+MO3FETQ29. The connection point with Q30 is placed in a floating state. This causes the switch MO3FETQ29. to be coupled to the interconnection point. Q3
It is possible to prevent the source and drain of 0 and the well region in which they are formed from being forward biased.

MO3FE constituting the above column switch circuit C-5W
TQ29. Q3(1) gate has Y decoder Y-DC
An output signal of R is provided. During a read operation, each output of the Y-decoder Y-DCH is set to a selection level equal to the zo power supply voltage Vcc or a non-selection level equal to zoro volts.

The common data line CD is connected to the output terminal of the data input circuit DIB constituting the input/output circuit 10B and the sense amplifier SA.
and an output sofa circuit OBG.
It is coupled to the input terminal of OB. This input/output circuit I
The input terminal of the data input circuit and the output terminal of the data output circuit constituting OB are coupled to external terminal I10.

According to this embodiment, each data line Di, D2 is provided with a latch circuit FF for holding the previous memory information prior to a write operation, and at the time of a write operation, the memory information of the θ edge circuit FF is provided. Accordingly, a level conversion circuit LVC is provided which selectively changes the potential of the data line to a negative high voltage -vpp. These allow simultaneous writing of data into multiple memory cells coupled to one selected word line.

The control circuit C0NT receives a chip enable signal, a write enable signal, and a write enable signal supplied to external terminals CE, WE, and OE.
Various operation modes are determined by receiving the output enable signal and the write voltage supplied to the external terminal VGIp, and the gate circuit G and level conversion circuit LV
It outputs various control signals for controlling the operations of circuits such as the C1 control voltage generation circuit Vig-G, the drive circuit DVR, the data input circuit DIR, and the data output circuit DOB.

An outline of the operation of the EEFROM device of this embodiment will be explained below.

Although not particularly limited, the read operation mode is CESW
The standby operation mode is indicated by the high level of the signal CE. The write operation mode is indicated by the low level, low level, high level, and low level of the signals GE, WE, OE, and vpp. In this embodiment, when a write operation is instructed, the stored information of all the memory cells connected to the word line for which the address was previously instructed is once read out and stored in each latch circuit FF shown in FIG. Retained. That is, the potential of the well region WELL where the MNOS transistor is formed is set to the ground potential Ov of the circuit, and the potentials of the data line D1 and the like are set to a level according to the read signal. Also, at this time, the control voltage Vc is the power supply voltage V
It is set to a high level like cc. As a result, the MO3FETQ31. Since Q32 is turned on,
The data signal supplied from the external terminal is taken into the latch circuit corresponding to the data line D1 etc. of the memory cell to be written. Although not shown, any bit can be rewritten in the memory cell connected to the word line. In this case, the data lines corresponding to the data to be written are sequentially switched according to the specification of the Y address, so that the write signal consisting of any plurality of bits supplied from the external terminal is sequentially taken into the corresponding latch circuit. It will be done. That is, a first write operation is performed.

After this, an erase operation of the MNOS transistor coupled to the word line is performed. That is, the potential of the well region WELL is set to a high level such as the power supply voltage Vcc, and the potential of the second word line connected to the gate of the MNOS transistor is set to a negative high voltage such as -vpp.

At this time, although the control voltage Vc is set to the high level as described above, MOSFETQ31. Q32 is turned off by the high level of the well region WELL in which it is formed.

After that, according to the information of the latch circuit FF, a substantial write operation is performed on the memory cells for one word line all at once.
That is, the second write operation is performed. At this time,
The potential of the well region WELL and the potential of the data line D1 corresponding to the data to be written are set to a negative high voltage. In synchronization with this, the control voltage Vc is also set to a negative high voltage, so that the data line isolation MO3FETs Q31, Q32, etc. are all turned off. As a result, column switch MOSFETQ29. In this embodiment, the PN junction between the semiconductor region on the data line side such as Q30 and the well region in which it is formed is prevented from being forward biased by the negative high voltage. The EEFROM can perform a write operation similar to that of a static RAM from the outside.

The following timer circuit is utilized to identify the end of the first write operation.

FIG. 1 shows a circuit diagram of one embodiment of a timer circuit.

The timer circuit includes an oscillation circuit O8C and binary counter circuits BC1 to BO2 connected in series.The output signal VO of the oscillation circuit O3C and the signal VO inverted by the inverter circuit Nl are supplied to the first stage circuit BCI. By doing this, a 4-bit counter circuit is constructed.

The oscillation circuit oSC and each of the binary counter circuits BCI to BO2 are put into a reset state by the high level of the reset signal R, and put into an operating state by the high level. This reset signal R is formed via the next input gate circuit. The trigger signal Tg and the count output v4 of the final stage of the counter circuit are P-channel MO
3FETQ1. It is supplied to a CMO5/7 (NOR) gate circuit consisting of Q2 and N-channel MO3FET Q3°Q4. In this embodiment, in order to prevent malfunctions when the power is turned on, the NOR gate circuit is
The ground potential of the circuit is supplied to the channel MO3FETs Q3 and Q4 via an N-channel MOSFET Q5 serving as a power switch that receives the output signal Vcs of the voltage detection circuit. Further, between the output terminal (node NA) of the NOR gate circuit and the power supply voltage Vcc, there is a P-channel MO3FET that receives the output signal Vcs of the voltage detection circuit.
Q6 is provided.

The voltage detection circuit includes a P-channel MOSFET QI1 whose gate is supplied with the circuit ground potential, and diode-connected N-channel MOSFETQ12. N-channel MO3 receiving Q13 and internal chip selection signal GE
Consists of a series circuit of 4 FETQIs. This circuit consists of the MO3FETQ12. A voltage detection operation is performed using the combined threshold voltage of Q13 as a reference voltage. That is, the second
As shown in the operating waveform diagram in the figure, the rise of the power supply voltage VCC when the power is turned on is
Until the combined threshold voltage of 3 is reached, these MOS
FETQI 2. Ql3 is turned off and its output is at a high level according to the power supply voltage VCC, and the power supply voltage V
When cc exceeds the combined threshold voltage of MO3FETQI 2 and Ql3, these MOSFETQI 2 and Q
l3 is turned on and forms a low level output signal. For this reason, the above Pchi+:/nel MOSFETQ11
is made to have a sufficiently high conductance compared to the conductance of MOSFETs QI2, Ql3, and Ql4. The voltage detection output obtained from the connection point of MO3FET QI 1 and Ql2 is the inverter circuit N3 and N
As shown in FIG. 2, the output signal Vc3 is amplified by 4, thereby forming an output signal Vc3 that is kept at a low level until the power supply voltage Vcc reaches a predetermined voltage. Note that the internal chip selection signal CE is set to a high level because the external terminal (CE) is maintained at a low level for a certain period of time when the power is turned on due to a relatively large parasitic capacitance at the corresponding external terminal. It is. In a steady state after power-on, when the internal chip selection signal CB is in a low level non-selected state, the MOS
The FET QI 4 is turned off to cut off its DC current path, and its output is set to a high level to substantially invalidate the voltage detection output.

The output signal (node NA) of the NOR gate circuit is connected to the P-channel MO3FETQ7. QB and N channel Mo
5FETQ9. The above-mentioned reset signal R is formed via a NOR gate circuit consisting of Q10. Note that the other input of this NOR gate circuit, MOSFETQ8 and QIO
A control signal C is supplied to the gate of. This control signal C becomes high level when not writing, and sets the reset signal R to low level regardless of the trigger signal Tg to reset the operation of the oscillation circuit O8C and the counter circuit.

The normal operation of the timer circuit in a steady state after power-on is completed, in other words, the third write operation is performed to capture the write data in the first write operation in the write mode.
This will be explained next with reference to the timing diagram shown in the figure. In such a normal operating state, since the voltage detection output VC3 is at a high level, the N-channel Mo3FETQ5
is turned on, and P-channel MO3FETQ6 is turned off. In this state, write data D
Since the trigger signal Tg is generated every time in is supplied, the node NA is set to a low level in response to the high level of the trigger signal Tg. As a result, the control signal C
Since O8C is set to a low level, the operation of the oscillation circuit O8C is stopped and the binary counter circuit is reset in synchronization with the trigger signal Tg. If the next write data Din is input before the set time T of the binary counter circuit, in other words, the output signal 4 of the final stage circuit BC4 is set to high level, the trigger signal Tg will be activated. The timer circuit is reset. Similarly, when write data Din is supplied one after another at a cycle shorter than the above-mentioned time T, the data is taken into the latch circuit shown in FIG. 4. Then, within the above time T, the next write data Di
If r+ is not input, the trigger signal Tg will not be generated as shown by the dotted line in the same figure, so the output signal 4 of the timer circuit becomes high level, and the operation shifts to the erase mode, which is the next operation step. At this time, the output node NA of the NOR gate circuit is maintained at a low level due to the high level of the signal 4, so it is assumed that the first write operation has been completed, and even if the write data Din is input from now on, the output node NA of the NOR gate circuit is maintained at a low level. If so, even if the trigger signal Tg is generated, it will not be accepted.

In the above timer circuit, the operation of the internal circuit immediately after tfQ is turned on is caused by the fact that the control terminals CB, WE, OE, etc. have relatively large parasitic capacitances in an unstable state before the operating voltage rises to a sufficient voltage. , power supply voltage Vc
It is set to high level with a delay from the rise of c. This gives an apparent indication of the write operation mode. In other words, if the potential of the node NA is set to a low level while the internal control signal C is set to a low level, the oscillation circuit O3C and the binary counter circuits BCI to BO2 are activated, and the binary counter circuits BCI to BO2 are activated. Since the initial values of the counter circuits BCI or BO2 are undefined, the output ■4 of the final stage counter circuit BC4 becomes high level within a very short time after the power is turned on until the external control signal reaches the normal level. There is a risk of being exposed. Once the output v4 is set to a high level, the internal circuit automatically shifts to the erase operation or the second write operation, resulting in undesirable destruction of stored information.

According to this embodiment, even if the write mode is apparently instructed when the power is turned on, the output signal Vcs of the voltage detection circuit is set to a low level, so that the node NA can be set to a high level. Accordingly, the oscillation circuit O3C and the counter circuits BC1 to BO2 can be maintained in the reset state until the power supply voltage reaches a normal state for the operation of the internal circuits and the internal signals. As a result, it is possible to prevent undesired erroneous erasing and erroneous writing immediately after the power is turned on as described above.

The effects obtained from the above examples are as follows. That is, (1) In accordance with the write operation mode, the storage information of the memory cell coupled to the selected word line is taken into the latch circuit, and then the write data is taken into the latch circuit one after another using a timer circuit. In an EEFROM device having a series of operational functions consisting of a first write operation, an erase operation, and a second write operation for substantially writing into a memory cell according to the information stored in the latch circuit, a voltage detection circuit is provided, and the power supply voltage is set to a predetermined value. By forcibly maintaining the timer circuit in the reset state until the voltage reaches , it is possible to prevent erroneous erasing or erroneous writing due to an unstable level of the internal circuit immediately after power is turned on. .

(2) As a writing method to the MNOS transistor,
After the storage information of the memory cell coupled to the selected word line is taken into the latch circuit and the data to be written is taken into the said latch circuit, one word line is written according to the erase operation of the memory cell and the data taken into the said latch circuit. By performing the writing for the number of bits, it is possible to obtain the effect that multi-bit data can be written at high speed.

(3) According to the above (2), writing operations can be performed from the outside in the same way as in a static RAM, resulting in the effect that an easy-to-handle EEPROM device can be obtained.

(4) With the potential of the semiconductor substrate fixed at a predetermined voltage such as a positive power supply voltage by using a negative high voltage,
Writing and erasing of the MNOS transistor can be performed. Therefore, a P-channel MO operated by the above power supply voltage and a signal level such as the ground potential of the circuit.
Since 3FETs can be formed on a semi-conductor substrate, peripheral circuits such as address decoders and address buffers can be constructed from CMO5 circuits. As a result, it is possible to achieve the effect of realizing low power consumption and high-speed operation by using three CMO circuits.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. Needless to say, the specific configuration of the timer circuit can take various embodiments. Also,
The output signal of the voltage detection circuit may directly force the timer circuit to be reset.

Furthermore, the isolation MO3FET Q3 of each memory cell may be omitted and the source of the MNOS l-transistor may be connected to the reference potential line. In this case, the reference potential line is kept in a floating state during the write operation. , the ground potential of the circuit is applied during read and erase operations. In addition, the column switch MO3FET is
It may be configured by a P-channel MO3FET.

In this case, the switch M provided in the memory array
O5FETQ31. Q32 etc. can be omitted.

Further, the specific circuit configuration of the X decoder, the latch circuit, and the voltage supply circuit that selectively supplies a negative high voltage using the control signal may be any.

In the present invention, as a write operation, information stored in a memory cell is taken into a latch circuit, data to be written is supplied to the latch circuit using a timer circuit, and then an erase operation is performed and the memory cell is processed according to the information stored in the latch circuit. It can be widely used in EEFROM devices that perform a series of operations such as writing to.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, during a write operation, the first write operation involves loading the memory information of the memory cell coupled to the selected word line into the -H latch circuit, and then loading the write data into the latch circuit one after another using a timer circuit. In an EEPROM device, a series of operation sequences consisting of an erase operation based on a time-up output of the timer circuit and a second write operation of substantially writing into the memory cell according to the information stored in the latch circuit is performed. By setting the timer circuit to forcibly maintain the reset state until the IT source voltage reaches a predetermined voltage, it is possible to prevent erroneous erasure or erroneous writing due to an unstable level of the internal circuit immediately after power is turned on. can do.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the timer circuit according to the present invention, Fig. 2 is a waveform diagram for explaining an example of the operation of the voltage detection circuit, and Fig. 3 is a circuit diagram showing an example of the operation of the timer circuit. FIG. 4 is a circuit diagram of an embodiment of a main part of an EEFROM device to which the present invention is applied. oSC: Oscillation circuit, BCI or BO2: Binary counter circuit, M-ARY: Memory array, X-D
CI2...X decoder, Y-DCR...Y decoder, L
VC...Level conversion circuit, G...Gate circuit, DRV...
・Drive circuit, FF...Latch circuit, Vc-G, Vig-
G, Vw-G...Control voltage generation circuit, VSC...Negative voltage supply circuit, SA...Sense amplifier, C-5W...Column switch circuit, DIB...Data input circuit, DOB...
Data output circuit, OBG...output buffer, WELL...
・Well region, C0NT...Control circuit Figure 3 V4 T←2 T1

Claims (1)

[Claims] 1. A memory array configured by a matrix arrangement of memory cells including semiconductor non-volatile memory elements that can be electrically written and erased, and a data line in the memory array that holds the read signal. a latch circuit to
A level conversion circuit forms the potential of a data line in a write operation according to the information held in the latch circuit, and a memory coupled to a word line addressed in a write operation in response to an operation mode signal supplied from an external terminal. a first read operation for taking memory information of the element into the latch circuit; and a first read operation for transmitting a write signal to the addressed data line to replace the memory information in the latch circuit.
a write operation, an operation of erasing information stored in a storage element coupled to the addressed word line, and a step in which information stored in the latch circuit is written to the storage element coupled to the word line by a level conversion circuit. A write system control circuit that performs the second write operation in chronological order, and a reset and start-up are performed in response to a predetermined trigger signal supplied at the time of the first write operation, and the erase operation is performed by the time-up output of the write system control circuit. An EEPROM device comprising: a timer circuit for causing the transition; and a power supply voltage detection circuit for forcibly bringing the timer circuit into a reset state when the power supply voltage is below a predetermined voltage. 2. The semiconductor nonvolatile memory element is composed of an MNOS transistor, and the relationship between the gate electrode of the MNOS transistor, the substrate gate, and its drain voltage, which are supplied for write/erase operations of the MNOS transistor, is as follows:
A patent claim characterized in that the PN junction between a well region in which a memory cell is formed and a semiconductor region to which a data line in this well region is coupled is changed with a time difference so as to maintain a reverse bias state. EE described in paragraph 1 of the scope of
PROM device.