JPS62272561A - 1-transistor type memory cell - Google Patents

Abstract

PURPOSE:To obtain a memory cell for performing a DRAM of approx. 64Mbit by using a trench type capacitor buried through a thin insulating film in a P<+> type substrate, and an N-channel MIS transistor of vertical SOI structure having an upper part as a source electrode. CONSTITUTION:A trench type capacitor of N<+> type polysilicon 24 buried through a thin insulating film 25 in a P<+> type substrate 21, and an N-channel MIS transistor of vertical SOI structure having the upper part of the polysilicon 24 as a source electrode are employed. For example, a trench structure is formed by RIE on the substrate 21, and the polysilicon 34, a P<-> type polysilicon 23 and an N<+> type polysilicon 22 are formed through the film 25. Further, after a field oxide film 28 and a gate oxide film 26 are formed, a gate electrode 27, a word line 29 and an interlayer insulating film 30 are formed, a contact hole is then opened to form a bit line 31, thereby obtaining a 1-transistor type memory cell in which a vertical MOS transistor is laminated on the trench type data storage capacitor.

Description

[Detailed description of the invention] 3 Detailed explanation of the invention [Industrial application field] The present invention relates to an element structure of a semiconductor memory.

[Conventional technology]

The element structure of conventional large-scale semiconductor memory, especially if it is limited to one-transistor type memory, is stacked up by each company FJI (
M., Koyanagi et al.
i, Engineering EDM 3481197B), or a type that uses the side wall of the groove as a capacitor (H, !3unami et
al: Ezx, Eng. 11) M 806, 1982)
There were two trends. The currently announced element structure is that the area of one cell is approximately 9 μm2, and 4
Application to ~16 Mbit DRAM is being considered. (N, ?, Rlchardson, et
al: Engineering Elmi, Engineering ICI) M 714, 1985
) [Problems to be Solved by the Invention] However, there is a strong demand for increasing the capacity of semiconductor memories, and the above-mentioned conventional technology is considered to have a limit of up to 16 Mbit. Therefore, the present invention is intended to solve these problems, and its purpose is to develop a DRAM of approximately 64 Mbit.
The purpose of the present invention is to provide a structure of a one-transistor type memory cell for realizing this.

[Means for Solving the Problems] The structure of the one-transistor memory cell of the present invention includes a trench-type capacitor made of N+ polysilicon embedded in a P+ substrate with a thin insulating film interposed therebetween, and a source-mi electrode directly above the trench-type capacitor. Vertical SOI trench structure 5 channel MIS
The present invention is characterized in that a transistor is used, and the gate electrode of the n-channel transistor is formed in cell 7 alignment by anisotropic etching such as RIE.

〔Example〕

FIG. 1 is a layout diagram of a one-transistor type memory cell in an embodiment of the present invention, where 1 is a word line and 2 is a bit line. Various materials can be considered for the word line and bit line, such as aluminum, silicide, polycide, and polysilicon.
N wiring is used. Reference numeral 3 designates the gate/X pole of the memory cell connected to the word line, and reference numeral 4 designates a capacitor that holds data. 5 is a contact hole between the bit line and the transistor of the memory cell. In FIG. 1, the area indicated by X and Y is the area occupied by 11)it.

FIG. 2 is a schematic cross-sectional view taken along the straight line AB in FIG. 1. 21 is a P single crystal silicon substrate;
22 is P+ single crystal or polycrystalline silicon, 23 is P+
24 is P+ polycrystalline silicon. 25 is a thin insulating film, and 21, 25, and 24 form a data holding capacitor. 26 is a gate insulating film, 27 is a gate electrode, and a signal from a word line 29 is applied to a region 23. Form an S-shaped channel. 28 is a field insulating film, 30 is an N-opened edge film τ', and 31 is a bit line. The memory cell of the present invention is
Basically, vertical MO3) transistors are stacked on top of a trench-type data retention capacitor;
OS) transistors are characterized by having an SOI trench structure and by forming gate electrodes by self-alignment. The manufacturing process will be explained below.

FIG. 3 is a schematic diagram of the manufacturing process of the memory cell of the present invention. In (α), a trench structure is created by RIE or the like using a P+ silicon substrate 21, and a thermal oxide film or a thermal nitride film is grown on the sidewalls at 25°, and then an n+ polysilicon 2
4. P-polysilicon23. FIG. 2 is a cross-sectional view of the film when deposited with n polysilicon 22. FIG. (b) is a cross-sectional view when polysilicon is etched after the alignment process and a field oxide film is formed. Furthermore, the crystallinity of the transistor portion is improved by laser annealing or the like. It goes without saying that a CvD oxide film or the like can be used instead of the field oxide film 28.

In (C), after forming the gate rk film, the gate electrode '2. z
FIG. 2 is a schematic diagram showing a state where the film is formed by CVD or sputtering, and then etched in an oblique direction by RIE or the like. (d) is a diagram when an interlayer insulating film 30 is formed after forming 29 word lines. Finally, contact holes are opened and bit lines are formed, as shown in FIG.

The above is an example of the manufacturing process for only the memory cell portion, and it is natural that an actual memory would involve many more steps, or that there would be some degree of freedom in the order of the steps.

〔Effect of the invention〕

As described above, according to the present invention, by stacking a vertical MOS (MOS) transistor on a trench-structured data storage capacitor, memory cells that could previously be miniaturized to only 9 (μR) can be made with the same design.・1/3 according to the rules
It is possible to do the following. Furthermore, by optimizing the dimensions of each part, a 64 Mbit DRAM can also be created.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a layout diagram of a memory cell according to the present invention. Figure f42 is a schematic cross-sectional view of the memory cell of the present invention. FIGS. 3(α) to 3(d) are schematic diagrams of the manufacturing process of the memory cell of the present invention. Applicant Seiko Epson Co., Ltd. Agent Mogami Patent Attorney (and 1 other person) <4) (Js Figure 3

Claims (2)

[Claims] (1) A trench type capacitor made of n^+ polysilicon embedded in a P^+ substrate via a thin insulating film, and a vertical SOI with the upper part of the n^+ polysilicon serving as the source electrode. A one-transistor type memory cell characterized by using an n-channel MIS transistor having a structure. (2) The gate electrode of the n-channel MIS transistor is R
The one-transistor type memory cell according to claim 1, characterized in that it is formed in self-alignment by anisotropic etching such as IE.