JPS62271570A - Ad conversion system for liquid crystal display device - Google Patents

Abstract

PURPOSE:To operate an A/D conversion part at a low frequency and to contrive reduction of the cost by A/D-converting picture signals enclosed by continuous two or more data signal lines and making said signals into modulation signals for displaying the half tone of one scan line in a liquid crystal matrix. CONSTITUTION:An A/D converter 1 converts the picture signals in data scan signals, and shift registers 2 and 3 stores them during a C period of 2H for continuous synchronizing signals N0-N2 and a D period of 2H for continuous synchronizing signals N3-N5. The contents in the registers 2 and 3 aretransferred to memories 4 and 5 at the timing of a signal P, and held for 6H. The signals from the memories 4 and 5 drive signal electrodes Y<1>1-Y<1>108 and Y<2>1-Y<2>108 in the crystal matrix 8 through crystal drive circuits 6 and 7. Scan electrodes in the matrix 8 are driven by scan signals X1-X41. Since two continuous sampling pulses in the first and latter halves during the periods C and D alternately drive odd signal electrodes and even signal electrodes in the matrix 8 to modulate brightness, and A/D conversion speed can be slowed down.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a liquid crystal television set that improves the processing of video signals by 1% and enables the use of low-speed AD converters. Is it a conventional liquid crystal matrix? The configuration of the liquid crystal television used is as follows. The video signal taken out from the television broadcast receiving circuit is converted into a digital partial signal by an AD converter.

The numbers of this digitally converted video image A are sequentially written into the shift register. - When the writing of the digital video signal corresponding to the scanning line is completed, the contents of the shift register are transferred to the memory all at once. A brightness modulation signal corresponding to the digital video signal stored in this memory is applied to the signal of the liquid crystal display panel. Figure 1 shows the scanning electrodes and signal electrodes of the liquid crystal matrix panel.
,
, , y, 1, y, 2°, etc. indicate the poles of the signals, respectively. The liquid crystal is driven by a conventionally known voltage equalization method, and the drive voltage waveform Fi for full selection and half selection of selected picture elements when the number of scanning lines is N is given by the drive voltage waveform Fi in FIG.

The ratio α of the effective values of the full selection and half selection voltages is given by:
When a-1m-z, α is the largest. In the case of N-An, α-1,17 is close to the limit of practical contrast. Already 8
A prototype liquid crystal television with 8748 picture elements (1 row x 108 columns) has been announced, and its block orientation is shown in Figure 3. 1
is an AD converter, and 2.5 is an A/D converter with 108 shift registers each storing one scanning line of digital video signal r memory.

4 and 51' are memories that hold primary digital signals only during the period when the scanning electrodes of the panel are driven. 6.7 is a liquid crystal drive circuit with *i variable modulation according to the above memory signal, and its output is connected to the signal electrode "1'+" of the liquid crystal matrix 8.
Y2'+ Ym”...'”'”' Yloll”
And Y l ” h Y 1” hy32...
...Ysos: are connected to each other. Scanning signals from the scanning electrodes of the liquid crystal window 11 and the screen 8 X l to X 4
1 is connected. The structure f' of the liquid crystal matrix is the same as that shown in FIG.

FIG. 4 is a timing diagram illustrating FIG. 5.

The H day is the water synchronization signal, and its period 1H = 6E5μB
It is. As mentioned above, since the number of scanning lines of the liquid crystal matrix is practically about 40, two rows of picture elements are driven in one scanning period of the 11 pixels. There are 242 effective scanning lines in one field of television broadcasting, so 242 lines ÷ (A
The video signal is sampled every 311 times from O×2)-3. Y' to AMHL at Nl'F from synchronization signal No.
N (N *1 * 2 +・・・・・・・・・108
) is held in the shift register 2. During the 2H period, y 2 N(N-1, 3,...
...10B) A digital signal is held in the shift register 3 for i control.

The digital video signals of the periods A and B are transferred to the memories A and 5 at the timing of the signal P, and are held for a period of 6H. FIG. 5 is a timing diagram of the sampling pulse tA during the sampling period AVc. In the row of picture elements, 81
Since x4/3ζ108, t%'a 1;, A,
・・・・・・・・・108 samplings are performed at ttn*”.The expected period is IH=65.5μe, water Q, 5
It becomes 11B. Therefore, the conversion speed during the AID conversion period is also equal to or higher than α5tts. Currently high speed AD
Converters are difficult to operate under certain conditions and must always be high. Therefore, it becomes difficult and difficult to implement IC. Also, if the number of conversion stations 12I2 is high, it is not convenient for converting the digital section to an IC.

The present invention is characterized in that A/D conversion bead generation is performed by combining data within one scan of a liquid crystal matrix from video signals within two consecutive fc horizontal synchronizing signals.

In the case of a liquid crystal display, scanning equivalent to that of a television cannot be performed due to the problem of crosstalk at the selection point.

Therefore, as in the prototype example, <AID conversion is performed every 5 H periods or every M period of more than 5 H periods. However, AI
According to the thinning cycle of D conversion, it becomes possible to reduce the number of scanning lines of television broadcasting to two or more. According to the drawing below,
The invention will now be described in full detail.

Figure tJS6 is a timing chart showing all the sampling periods of the video signal from the television receiving circuit in the present invention. C period rJ consisting of 2H of consecutive synchronization signals No or N
1 This is the AD change period of the first video signal, and the memory period for the shift register 2.

Father, sync signal N! The D interval consisting of 2H from to N6 is the AD change period of the second video signal, and the memory interval to the shift register 3 is 6.

The contents of 2.3 are transferred to the memory 45 at the timing of the signal P and held for 6Hw1.

FIG. 7 is a timing diagram of the sampling pulse to during period 0 in FIG. 54 samplings &1 during horizontal synchronization signal No. and N1 period which is the first half of C period
+°a j2'+ ...... Performed at t54'.

This converted digital signal is sent to the signal electrode Y1 #Yg......Ysoy of the liquid crystal display.
i=brightness modulation data of the driving voltage. Δt is the interval between the synchronization signal N0 and the sampling pulse t1°. Also, tmO and tn+1' (Nmi1.....54
) is set to 1 μB. I heard the horizontal U3 signal N, which is the latter half of the C period, and the same 54 times in the N1 period.
Performed at R'. This converted digital signal is sent to the signal electrodes Y2+Y4 of the liquid crystal display 11,...
. . . It becomes the brightness modulation data of the voltage that drives Y 101. The interval between the father synchronization signal Nl and tsso is Δ℃+α5
It is set to μ6. tIIo and t11++ (N-55,
. . . 107) has an interval of 1μ8. FIG. 8 shows a state in which the converter after /l/D conversion of the video signal is stored in the shift register.

From the above, it is possible to simultaneously select the video signals of two consecutive television broadcasts as signals of one pixel column during one scan of the liquid crystal screen 11. The sampling period is 1 μB, which is twice that of the conventional method. In this embodiment, the case where two video signals are combined is described, but it is also possible to combine two or more signals. However, since the number of signals to be stored affects the resolution of the reproduced image, it must be selected according to the number of scans of the liquid crystal matrix (IJ). N=40 and 8 picture elements
In the case of 1 row x 10 8 columns, the effect of combining two to three video signals on the resolution of the image is practically negligible.

As detailed above, according to the present invention, it is possible to lower the frequency of the A/D converter used in LCD TVs, and when commercialized,
In particular, it contributes greatly to lower prices.

[Brief explanation of the drawing]

Figure 1 shows a liquid crystal matrix panel. Figure 2 is a diagram of driving waveforms for the liquid crystal. Figure 3 is a professional diagram explaining the conventional LCD TV. Are figures 4 and 5 like figure 3? A timing diagram for explaining. FIGS. 6 and 7 are timing diagrams for explaining the present invention. FIG. 8 is a memory state diagram of the shift register according to the present invention;
. Applicant: Seiko Epson Corporation Figure 2 Figure 3 Figure 4 Figure 5 (1, I Figure 6 Figure 8

Claims (1)

[Claims] In a liquid crystal display device that displays an image with halftones, by controlling the voltage applied to the signal electrode of a liquid crystal matrix having signal electrodes and scanning electrodes, image signals in two or more consecutive data scanning signals can be AD An AD conversion method for a liquid crystal display device, characterized in that the AD conversion method is converted into a modulation signal for halftone display within one scanning line of the liquid crystal matrix.