JPS62262443A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS62262443A JPS62262443A JP10610286A JP10610286A JPS62262443A JP S62262443 A JPS62262443 A JP S62262443A JP 10610286 A JP10610286 A JP 10610286A JP 10610286 A JP10610286 A JP 10610286A JP S62262443 A JPS62262443 A JP S62262443A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- poly
- layer
- wiring layer
- barrier layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 3
- 239000010936 titanium Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims description 3
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 238000002844 melting Methods 0.000 abstract description 7
- 229910021332 silicide Inorganic materials 0.000 abstract description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 7
- 230000008018 melting Effects 0.000 abstract description 6
- 150000004767 nitrides Chemical class 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
埋め込み配線層としてポリＳｉを有し、その上部にこれ
と接続するＡｌ配線層を有する半導体装置において、両
層間に高融点金属の窒化物またはシリサイドのバリア層
を挟むことにより、Ａｌ配線層とポリＳｔとの反応によ
る不具合を防止する。[Detailed Description of the Invention] [Summary] In a semiconductor device having poly-Si as a buried wiring layer and an Al wiring layer connected thereto above, a barrier layer of high-melting point metal nitride or silicide is provided between both layers. By sandwiching the Al wiring layer and the polySt, problems caused by the reaction between the Al wiring layer and the polySt can be prevented.
本発明は埋め込み配線層を有する半導体装置の配線構造
とその製造方法に関する。The present invention relates to a wiring structure of a semiconductor device having a buried wiring layer and a manufacturing method thereof.
半導体装置は集積度がＩＣ，ＬＳＩと上がるに従って配
線層も多層化され、相互に交叉する場所も多くなって来
ている。このとき下層配線は絶縁層の中に埋め込んで表
面を平坦にし、上部配線層に出来るだけ段差が生じない
ようにして断線防止に努めると同時に、上下配線層の間
の接続は材質的に経年変化のない安定したものであるこ
とが必要である。As the degree of integration of semiconductor devices increases from IC to LSI, wiring layers are multilayered, and the number of locations where they intersect with each other is increasing. At this time, the lower layer wiring is buried in an insulating layer to make the surface flat, and at the same time, efforts are made to prevent disconnections by minimizing steps in the upper wiring layer, and at the same time, the connection between the upper and lower wiring layers changes over time due to the material. It needs to be stable and free of turbulence.
従来、下層の埋め込み配線層としてポリＳｔを使用し、
上部配線層に旧を使用する方法が用いられているが、こ
の構造のものはＡｌとポリＳｉの間に反応が起こり、こ
れが障害の原因となる欠点を有している。そのため、こ
れの効果的な且つ簡易な解決方法が要望されている。Conventionally, polySt was used as the lower buried wiring layer,
A method of using aluminum for the upper wiring layer has been used, but this structure has the disadvantage that a reaction occurs between Al and poly-Si, which causes trouble. Therefore, an effective and simple solution to this problem is desired.
第３図（ａ）〜（ｃ）は従来例における埋め込み配線形
成工程の断面模式図である。FIGS. 3(a) to 3(c) are schematic cross-sectional views of the buried wiring forming process in the conventional example.
第３図（ａ）はポリＳｉの被膜を被着した状態を示す。FIG. 3(a) shows a state in which a poly-Si film is applied.
この図において、Ｓｉ基板１の上に絶縁膜層例えばＳｉ
Ｏｚ膜層２を形成し、このＳｉＯｚ膜層２に開口を設け
た後、表面全面にＣＶＤ法で厚さ約１．５μｍのポリＳ
＋３を被着する。In this figure, an insulating film layer, for example, Si
After forming the Oz film layer 2 and providing openings in this SiOz film layer 2, polysilicon with a thickness of approximately 1.5 μm is deposited on the entire surface by CVD method.
Deposit +3.
第３図（ｂ）は埋め込み配線層を形成した状態を示す。FIG. 3(b) shows a state in which a buried wiring layer has been formed.
ドライエツチングによりＳｉＯ□膜２の表面が露出する
までエツチングして全体の表面を平坦に仕上げる。ドラ
イエツチングは、ＣＦ４ ＋ Ｏ□のガスを用い、圧力
０．５ Ｔｏｒｒ、パワー３５０ｕで行う。Dry etching is performed until the surface of the SiO□ film 2 is exposed, and the entire surface is finished flat. Dry etching is performed using CF4 + O□ gas at a pressure of 0.5 Torr and a power of 350 u.
第３図（ｃ）は上部配線層を形成した状態を示す。FIG. 3(c) shows a state in which an upper wiring layer has been formed.
スパッタリング法により旧配線５の被膜を約１μｍ被着
し、後パターニングする。A film of about 1 μm is applied to the old wiring 5 by sputtering, and then patterned.
この方法により形成したものは、下層の埋め込み配線層
のポリＳｉ３と上部の＾ｌ配線５が直接、接続されてい
るので半導体装置を使用している間にＡ１配線５がポリ
Ｓｉ３を吸い上げ、ポリＳｉ３に空洞が生ずると云う欠
点を有している。In the case formed by this method, the poly-Si3 of the lower buried wiring layer and the upper ^l wiring 5 are directly connected, so while the semiconductor device is in use, the A1 wiring 5 sucks up the poly-Si3 and the poly-Si3 is removed. It has the disadvantage that cavities are formed in Si3.
又、Ｓｉ基板１の表面にＮ型領域を形成し、埋め込み配
線層のポリＳｉ３もＮ型にした構造のものでは、上部の
Ａｌ配線５がポリＳｉ３の中に拡散して来るとポリＳｉ
３をＰ型に変えＰＮ接合をポリＳｉａ中に形成すると云
う不都合がある。In addition, in a structure in which an N-type region is formed on the surface of the Si substrate 1 and the poly-Si3 in the buried wiring layer is also N-type, when the upper Al wiring 5 diffuses into the poly-Si3, the poly-Si
There is an inconvenience that 3 is changed to P type and a PN junction is formed in polySia.
従来例において、埋め込み配、％？Ｉ層のポリＳｉと上
部配線層のＡｌ配線が反応することにより起こる不具合
を防止するため、両層の間にバリア層を挟むものである
。In the conventional example, embedded allocation, %? In order to prevent problems caused by reactions between the poly-Si of the I layer and the Al wiring of the upper wiring layer, a barrier layer is sandwiched between the two layers.
上記問題点の解決は、Ｓｉ基板（１）上の絶縁膜層（２
）の開口部に埋め込んだポリＳｉ（３）と、このポリＳ
ｉ（３）の上部に形成したバリア層（４）と、更にその
上に形成したＡｌ配線（５）を有してなる本発明による
半導体装置により達成される。The solution to the above problem is the insulating film layer (2) on the Si substrate (1).
) and this poly-Si (3) embedded in the opening of
This is achieved by the semiconductor device according to the present invention, which includes a barrier layer (4) formed on top of i(3) and an Al wiring (5) further formed thereon.
特に、前記バリア層（４）をチタン、タングステン若し
くはモリブデンの窒化物とすることにより本発明は容易
に実施することが出来る。In particular, the present invention can be easily implemented by making the barrier layer (4) a nitride of titanium, tungsten, or molybdenum.
又、前記バリア層（４）をチタン、タングステン若しく
はモリブデンのシリサイドとすることにより本発明は容
易に実施し得る。Furthermore, the present invention can be easily carried out by forming the barrier layer (4) from titanium, tungsten, or molybdenum silicide.
更に、Ｓｉ基板（１）上の絶縁膜層（２）の開口部にポ
リＳｉ（３）を埋め込み、前記ポリＳｉ（３）の上部に
バリアＮ（４）を形成する工程と、更にその上に屓配線
（５）を形成する工程とを有している本発明による半導
体装置の製造方法により達成することが出来る。Furthermore, a step of embedding poly-Si (3) in the opening of the insulating film layer (2) on the Si substrate (1) and forming a barrier N (4) on top of the poly-Si (3); This can be achieved by the method for manufacturing a semiconductor device according to the present invention, which includes the steps of forming the wiring (5).
埋め込み配線層としてのポリＳｉと、その上部のＡｌ配
線の間に高融点金属の窒化物またはシリサイドのバリア
層を挟むことにより、Ａｔ配線とポリＳｉとの反応によ
る不具合を防止する。By sandwiching a barrier layer of high melting point metal nitride or silicide between the poly-Si as the buried wiring layer and the Al wiring above it, problems caused by reactions between the At wiring and the poly-Si are prevented.
第１図（ａ）〜（ｄ）は本発明の実施例（１）における
埋め込み配線形成工程の断面模式図である。FIGS. 1(a) to 1(d) are schematic cross-sectional views of the embedded wiring forming process in Example (1) of the present invention.
これら図において、第３図と同じ名称のものは同じ符号
で示す。In these figures, parts with the same names as in FIG. 3 are designated by the same reference numerals.
第１図（ａ）はポリＳｉの被膜を被着した状態を示す。FIG. 1(a) shows a state in which a poly-Si film is applied.
この図において、Ｓｔ基板１の上に絶縁膜層例えばＳｉ
Ｏ□膜Ｎ２膜形２し、このＳｉｎｇ膜層２に開口を設け
た後、表面全面にＣＶＤ法で厚さ約１．５μｍのポリＳ
ｉ３を被着する。In this figure, an insulating film layer such as Si is formed on an St substrate 1.
After forming an O□ film N2 film type 2 and providing an opening in this Sing film layer 2, a polysilicon film with a thickness of approximately 1.5 μm is deposited on the entire surface by CVD.
Apply i3.
第１図（ｂ）は埋め込み配線層を形成した状態を示す。FIG. 1(b) shows a state in which a buried wiring layer has been formed.
ドライエツチングによりＳｉｎｇ膜２の表面が露出する
までエツチングして全体の表面を平坦に仕上げる。ドラ
イエツチングは、ＣＦ４ ＋ Ｏ□のガスを用い、圧力
０．５ Ｔｏｒｒ、パワー３５０ Ｗで行う。Dry etching is performed until the surface of the Sing film 2 is exposed to make the entire surface flat. Dry etching is performed using CF4 + O□ gas at a pressure of 0.5 Torr and a power of 350 W.
これまでは従来例と全く同様な方法で形成される。Up to now, it has been formed in exactly the same manner as in the conventional example.
第１図（ｃ）は上部配線層としてＡｌ配線を形成した状
態を示す。FIG. 1(c) shows a state in which Al wiring is formed as the upper wiring layer.
この図において、まずバリア層の窒化チタン（ＴｉＮ
） ４を厚さ５００〜１０００人、スパッタリング法
で被着形成する。ついで、スパッタリング法によりＡｌ
配線５の被膜を約１μｍ被着する。In this figure, first, titanium nitride (TiN) is used as the barrier layer.
) 4 to a thickness of 500 to 1000 layers by sputtering. Then, by sputtering method, Al
A coating of about 1 μm is applied to the wiring 5.
第１図（ｄ）はＡｌ配線とバリア層をパターニングした
状態を示す。FIG. 1(d) shows the patterned state of the Al wiring and barrier layer.
フォ］・レジストをマスクにしてＡｌ配線５およびＴｉ
Ｎ層４を同時に、異方性ドライエツチングによりパター
ニングする。異方性ドライエツチングはガス：ＣＣｌ４
、圧カニ０．Ｉ Ｔｏｒｒ 、パワー： ３５０ Ｗで
行う。Al wiring 5 and Ti using the photoresist as a mask.
At the same time, the N layer 4 is patterned by anisotropic dry etching. Anisotropic dry etching uses gas: CCl4
, pressure crab 0. I Torr, power: 350 W.
第２図（ａ）〜（ｄ）は本発明の実施例（２）における
埋め込み配線形成工程の断面模式図である。FIGS. 2(a) to 2(d) are schematic cross-sectional views of the embedded wiring forming process in Example (2) of the present invention.
第２図（ａ）は高融点金属の被膜を被着した状態を示す
。FIG. 2(a) shows a state in which a film of a high melting point metal is applied.
この図において、埋め込み配線層のポリＳｉ３を形成す
るまでの工程は第１図（ａ） 、（ｂ）におけるものと
全く同じである。埋め込み配線層ポリＳｉ３を形成後、
表面にスパッタリング法で高融点金属例えばモリブデン
（Ｍｏ） ６を５００〜１０００人被着する。In this figure, the steps up to the formation of the poly-Si3 buried wiring layer are exactly the same as those in FIGS. 1(a) and 1(b). After forming the embedded wiring layer poly-Si3,
500 to 1000 high melting point metals such as molybdenum (Mo) 6 are deposited on the surface by sputtering.
第形成（ｂ）は熱処理によりシリサイドを形成した状態
を示す。Formation (b) shows a state in which silicide is formed by heat treatment.
約８００℃でＮ２中で熱処理すると、Ｍｏ６はポリＳｉ
３と接触する下側の部分より漸次シリサイド化しバリア
層４となるモリブデンシリサイド（ＭｏＳｉｚ ）を形
成する。When heat treated in N2 at about 800°C, Mo6 becomes polySi
Molybdenum silicide (MoSiz) is gradually silicided from the lower portion in contact with the barrier layer 4 to form a barrier layer 4.
第２図（ｃ）は金属Ｍｏをエツチング除去した状態を示
す。FIG. 2(c) shows a state in which the metal Mo has been etched away.
ＮＨ４ＯＨ＋ ＨｚＯ□の液でエツチングして金属ＭＯ
を除去する。 このときシリサイドのＭｏＳｉｔ １１
４が若干周囲のＳｉＯ□膜Ｎ２膜形２き出ているが、そ
の量は僅かであるため、後工程で形成するＡｌ配線層の
段差には殆ど影響しない。Metal MO by etching with NH4OH + HzO□ solution
remove. At this time, the silicide MoSit 11
4 protrudes a little from the surrounding SiO□ film N2 film type 2, but the amount is so small that it hardly affects the level difference of the Al wiring layer formed in a later process.
第２図（ｄ）はＡｌ配線層をパターニングした状態を示
す。FIG. 2(d) shows the patterned state of the Al wiring layer.
Ａｌをスパッタリングで約１μｍ被着して後パターニン
グし、Ａｌ配線５を形成する。Al is deposited to a thickness of about 1 μm by sputtering and then patterned to form an Al wiring 5.
第１の実施例、第２の実施例ともに下層の埋め込み配線
層ポリＳｉ３と、上層のＡｌ配線５との間に薄いバリア
層４を設けてポリＳｉとＡｌが直接接触するの避けてい
るため、両者間の反応は生じない。In both the first and second embodiments, a thin barrier layer 4 is provided between the lower buried wiring layer poly-Si 3 and the upper layer Al wiring 5 to avoid direct contact between the poly-Si and Al. , no reaction occurs between the two.
ここで、ポリＳｉは一般に伝導性を良くするためＮ型ま
たはＰ型不純物をドープしたものが使用されるが、ノン
ドープのものであってもバリア層の効果は同じである。Here, poly-Si is generally doped with N-type or P-type impurities to improve conductivity, but the effect of the barrier layer is the same even if it is undoped.
又Ａｌ配線は純Ａｌであっても、Ａ１合金であってもよ
い。Further, the Al wiring may be made of pure Al or may be made of an A1 alloy.
第１の実施例ではバリア層として比抵抗の比較的小さい
ＴｉＮとしたがこれをＴｉ２Ｎ、曲、Ｗ、ＦＪ、ＭｏＮ
％ ＭＯ２Ｎ、ＴａＮ ５ＴａＪｓ Ｚｒ−としても
効果は同様である。In the first embodiment, TiN, which has a relatively low resistivity, was used as the barrier layer.
% MO2N, TaN 5TaJs Zr-, the effect is similar.
また、第２の実施例ではバリア層としてＭｏ５ｔｚとし
たがこれをＴｉＳｉｚ、ＷＳｉｚとしても良好な結果を
得ることが出来る。Further, in the second embodiment, Mo5tz was used as the barrier layer, but good results can also be obtained by using TiSiz or WSiz instead.
埋め込み配線層としてのポリＳｉと、その上部のＡｌ配
線の間に高融点金属の窒化物またはシリサイドのバリア
層を設けているので、Ａｌ配線とポリＳｉとの反応によ
り生じていた、ＡｔがポリＳｉを吸い上げ空洞が発生す
る、又はポリＳｉ層中にＰＮ接合を形成する等の欠点を
なくすることが出来る。Since a barrier layer of high melting point metal nitride or silicide is provided between the poly-Si as the buried wiring layer and the Al wiring above it, the At generated by the reaction between the Al wiring and the poly-Si is removed from the poly-Si. It is possible to eliminate drawbacks such as the generation of cavities due to the absorption of Si or the formation of PN junctions in the poly-Si layer.
第１図（ａ）〜（ｄ）は本発明の実施例（１）における
埋め込み配線形成工程の断面模式図、第２図（ａ）〜（
ｄ）は本発明の実施例（２）における埋め込み配線形成
工程の断面模式図、第３図（ａ）〜（ｃ）は従来例にお
ける埋め込み配線形成工程の断面模式図である。
この図において、
１はＳｔ基板、
２は絶縁膜層（Ｓｉｎｔ）、
３はポリＳ１％
４はバリア層、
５はＡｌ配線、
６は高融点金属
卒１ 因FIGS. 1(a) to (d) are schematic cross-sectional views of the embedded wiring forming process in Example (1) of the present invention, and FIGS. 2(a) to (d) are
d) is a schematic cross-sectional view of the buried wiring forming process in Example (2) of the present invention, and FIGS. 3(a) to 3(c) are cross-sectional schematic diagrams of the buried wiring forming process in the conventional example. In this figure, 1 is the St substrate, 2 is the insulating film layer (Sint), 3 is poly S1%, 4 is the barrier layer, 5 is the Al wiring, 6 is the high melting point metal.
Claims (1)
め込んだポリＳｉ（３）と、 このポリＳｉ（３）の上部に形成したバリア層（４）と
、 更にその上に形成したＡｌ配線（５）を 有してなることを特徴とする半導体装置。 〔２〕前記バリア層（４）がチタン、タングステン若し
くはモリブデンの窒化物よりなることを特徴とする特許
請求の範囲第１項記載の半導体装置。 〔３〕前記バリア層（４）がチタン、タングステン若し
くはモリブデンのシリサイドよりなることを特徴とする
特許請求の範囲第１項記載の半導体装置。 〔４〕Ｓｉ基板（１）上の絶縁膜層（２）の開口部にポ
リＳｉ（３）を埋め込み、前記ポリＳｉ（３）の上部に
バリア層（４）を形成する工程と、 更にその上にＡｌ配線（５）を形成する工程とを有して
いることを特徴とする半導体装置の製造方法。[Claims] [1] Poly-Si (3) embedded in the opening of the insulating film layer (2) on the Si substrate (1), and a barrier layer (4) formed on the poly-Si (3). ), and an Al wiring (5) formed thereon. [2] The semiconductor device according to claim 1, wherein the barrier layer (4) is made of titanium, tungsten, or molybdenum nitride. [3] The semiconductor device according to claim 1, wherein the barrier layer (4) is made of titanium, tungsten, or molybdenum silicide. [4] A step of embedding poly-Si (3) in the opening of the insulating film layer (2) on the Si substrate (1) and forming a barrier layer (4) on top of the poly-Si (3); A method for manufacturing a semiconductor device, comprising the step of forming an Al wiring (5) thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10610286A JPS62262443A (en) | 1986-05-09 | 1986-05-09 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10610286A JPS62262443A (en) | 1986-05-09 | 1986-05-09 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62262443A true JPS62262443A (en) | 1987-11-14 |
Family
ID=14425150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10610286A Pending JPS62262443A (en) | 1986-05-09 | 1986-05-09 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62262443A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6914336B2 (en) | 2000-01-25 | 2005-07-05 | Nec Electronics Corporation | Semiconductor device structure and method for manufacturing the same |
| JP2014192314A (en) * | 2013-03-27 | 2014-10-06 | Citizen Holdings Co Ltd | Semiconductor device manufacturing method |
-
1986
- 1986-05-09 JP JP10610286A patent/JPS62262443A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6914336B2 (en) | 2000-01-25 | 2005-07-05 | Nec Electronics Corporation | Semiconductor device structure and method for manufacturing the same |
| JP2014192314A (en) * | 2013-03-27 | 2014-10-06 | Citizen Holdings Co Ltd | Semiconductor device manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5838051A (en) | Tungsten policide contacts for semiconductor devices | |
| JP2757927B2 (en) | Method of interconnecting spaced silicon regions on a semiconductor substrate | |
| JPH06177132A (en) | Manufacture of interconnection structure in integrated circuit | |
| JPH07193024A (en) | Semiconductor device and its manufacture | |
| JPH06163578A (en) | Method for forming contact hole | |
| JPS62262443A (en) | Semiconductor device and manufacture thereof | |
| JPH0283978A (en) | Semiconductor device | |
| KR100431309B1 (en) | Method for forming metal interconnection in semiconductor device | |
| KR100265839B1 (en) | Metal wiring method for semiconductor device | |
| JPH0228956A (en) | Semiconductor integrated circuit device | |
| KR100252915B1 (en) | Metal line of semiconductor device and method for fabricating the same | |
| JP3189399B2 (en) | Method for manufacturing semiconductor device | |
| JPS63253647A (en) | Semiconductor device | |
| KR0139599B1 (en) | Mechod of forming metal wiring in semiconducotr device | |
| JP3038873B2 (en) | Method for manufacturing semiconductor device | |
| KR100318273B1 (en) | Method for forming bit line of semiconductor device | |
| KR100290771B1 (en) | Method of forming contact plug of semiconductor device | |
| JPH01274452A (en) | Manufacture of semiconductor device | |
| JPH02203526A (en) | Semiconductor device | |
| JPH07111969B2 (en) | Method for manufacturing semiconductor device | |
| JPH0355846A (en) | Manufacture of semiconductor device | |
| JPH0230113A (en) | Semiconductor integrated circuit device | |
| JPH05335426A (en) | Semiconductor device and its manufacture | |
| KR20000041700A (en) | Method of forming contact of semiconductor device | |
| JPH06232277A (en) | Manufacture of semiconductor device |