JPS62259140A - Address generating circuit - Google Patents

Abstract

PURPOSE:To obtain an address generating circuit that can decrease the number of instruction steps produced by the generation of addresses, by deciding with control whether the code extension of an offset address supplied to an adder should be carried out or not. CONSTITUTION:When an index operation filed IDX is equal to '00', the address qualification data (i) is held as it is in a selection field IX24 and an offset address A is outputted as it is to the contents of a generated address. Then the address value AD2 with which the codes of the address A are infinite is outputted to an output terminal 22. When the field IDX is equal to '01', an adder 23 is set under an inhibition mode with the input of the address A. Thus the adder 23 performs an addition (i+AD2) and outputs it. Then the adder 23 is set under a code extension mode with IDX=10 and regards the address A as a number having a code. Thus the code is extended up to the bit length equal to (i) and the adder 23 performs an addition (i+A=i+AS.AD1) and outputs it. When IDX=11 is satisfied, the same addition as that carried out in a mode of IDX=10 is performed and outputted via a selector 26. At the same time, the addition is set again to the field IX24 via a selector 25 for the updating of indexes.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an address generation circuit, and more particularly to a method of generating addresses using index modification in a memory address generation circuit of a one-chip signal processing processor. related.

(Prior art) Conventionally, an address generation method using index modification is described in "New Edition Information Processing Handbook" edited by Information Processing Society of Japan, Volume 17 &
Chapter I3 [3], published July 20, 1981, Ohmsha P,
No. 793-794. The conventional method will be explained below based on the drawings.

FIG. 5 is a circuit diagram showing a conventional address generation circuit. In the same figure, 10 is the offset specified by the command.
An input terminal for inputting the address (A), 11 is an input terminal for inputting the modification setting address (i) specified by the command, 1
2 is an output terminal to which generated address data is output, 13 is an index register (hereinafter abbreviated as IX), and 14 is a two-manual adder (hereinafter abbreviated as ADD).

Next, the operation of the conventional example will be explained using FIG.

First, the modification setting address (
i) is set to lX13 via input terminal 111
Next, the offset address (A
) is specified via the input terminal 10, the address generation circuit adds the data (i) of lX13 in the ADD 14 and outputs the resulting address data (A+i) to the output terminal 12. Then, the address of a memory (not shown) is specified by the value of this address/data output A+i=X.

In particular, signal processors typically use binary 2's complement representation as their data format.

The data (i) of lX13 and the offset address (A) specified by the instruction were added using a signed number. this is,
Due to the characteristics of two's complement arithmetic, the operation i+α (α: constant) that increments in the plus direction and i-α that increments in the minus direction are the same instruction for memory address specification (modified setting address (i)). This is because the same addition process is performed for word length address data.

(Problems to be Solved by the Invention) However, in the above conventional circuit configuration, within the limited instruction word length, the word length assigned to the offset address data or index modification data cannot be coded. One bit is required. As a result, the range of absolute values of address values that can be generated by - number of instruction operations is narrowed, the number of instruction steps for address generation increases, the scale of the program increases, and the processing time increases.

The present invention is intended to solve these problems, and an object of the present invention is to provide an index-modified address generation circuit that can make maximum use of the address generation bit width in the instruction word length.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides an index register for temporarily storing a modification setting address specified by an index operation instruction, and an index register for temporarily storing a modification setting address specified by an index operation instruction. The adder includes an adder that adds the output from the adder and an offset address specified by an arithmetic instruction, and a control circuit that controls whether or not to perform sign extension of the offset address 1 to address input to the adder.

(Operation) According to the present invention having the above configuration, the data value of the offset address specified by the operation instruction is added to the output of the index register in the adder, and the data value is 1.
Generates a memory address for the chip signal processing processor. Here, the adder is set to a sign extension mode in which the control circuit performs sign extension of the offset address input to the adder, or the adder is set to a prohibition mode in which sign extension of the offset address is prohibited. ,
Two types of generated address value ranges can be selectively used.

Therefore, the present invention can solve the above problems.

It is possible to provide an address generation circuit that can reduce the number of instruction steps associated with address generation.

(Example) Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the figure, 20 is an input terminal for inputting the offset address (A) specified by the instruction, 21 is an input terminal for inputting the modification setting address (i) specified by the instruction, and 22 is the generated address data. output terminal, 23
is m = 8-bit two-person ADD, 24 is IX, 25,
26 is a 2-man power 1-output selector (hereinafter abbreviated as SEL)
, 27 is a sign bit extension inhibition gate of the offset address (A), and 28 is an operation setting terminal of the sign bit extension inhibition gate 27.

Further, FIG. 2 is a diagram showing the internal structure of microinstructions of a one-chip signal processing processor. In the same figure, TYP
I and TYP2 are type fields, x is an index register selection field, i is address modification setting data (m bits), IDX is an index operation field, A is an offset address field (n bits), and AD.

is a data bit of the internal structure of A, AS is a 1-bit sign bit, and AD is an n-1 data bit.

Note that there is a magnitude relationship of m>n.

Next, the operation of this embodiment will be explained.

First, using the index operation command shown in FIG. 2(a),
First, address modification data i is set in lX24 in FIG. 1, and then, using the operation instruction in FIG. Do this.

A process of outputting generated data to the output terminal 22 is performed.

At this time, the calculation specification of ADD23 and S E L25,2
The operation designation in step 6 will be explained using FIG.

FIG. 3 is a diagram showing the relationship between 2-bit IDX and generated address contents in this embodiment, and shows four types of states that can be selected by specifying the index operation field IDX.

When IDX=OO, the address modification data i set by the index operation command is held as is in the module X24 in FIG. 5EL2 in the diagram
6 is switched. As a result.

An address value AD is output to the output terminal 22, assuming that A is sign-infinite.

When IDX=01, the address modification data i set by the index operation instruction is held in lX24 in FIG. 1, and when the offset address A is input to the input terminal 20 in FIG. The prohibition gate 27 is set to the prohibition mode, and the addition process of i+ADH is performed, regarding A as a signless AD. This addition result is output to the output terminal 22 via 5EL2'6.

When IDX=IO, the address modification data i set by the index operation instruction is held in lX24 in FIG. 1, and when the offset address A is input to the input terminal 20 in FIG. 1 by the operation instruction, ADD23 , the sign extension prohibition gate 27 is set to the sign extension mode and A is regarded as a signed number, and sign extension is performed to the bit length m equal to i, i+A=i+AS-AD (however, AS-
AD is the signed number representation of A). This addition result is output to the output terminal 22 via the 5EL26.

When IDX=11, after performing the same addition process as IDX=10, the output of ADD23 becomes 5EL2.
At the same time, 5EL2 is output to the output terminal 22 via 5EL2.
5 to lX24 again to update the index.

Next, the difference between the above-mentioned unsigned addition and signed addition will be explained. In this embodiment, m = 8 bits.

In the case of n=6 bits, the range of the modification setting address (i) that can be specified with the index operation instruction is 0≦i≦255 in decimal notation, and the range of the offset address A is 0≦A≦63 as sign infinity. ．． 13 as a signed number
2≦A×31. Therefore, when considering the range of memory addresses that can be accessed using these address data values, for 1=63, Figures 4(a) and 4(b) showing the state of the adder mode in this embodiment )become that way. Therefore, in the signed addition shown in FIG. 4(b), it is advantageous to perform addressing within a range of 64' before and after the modified setting address (i), and in the unsigned addition shown in FIG. This is advantageous when addressing is performed in a range of 64' in the increasing direction of addresses with the set address (i) as a reference. In either case, for - times of memory access, address generation can be performed in two steps of an index operation instruction and an arithmetic instruction, or in one step of an arithmetic instruction after index register setting.

In the above embodiment, the bits when sign extension is prohibited are set to 11.
Although it is fixed at 0 $1, if it is fixed at 111 F+, it is also possible to set the addressing mode only on the subtraction side for index-qualified addresses.

(Effects of the Invention) As explained above, according to the present invention, the process of adding the data value of the offset address specified by the arithmetic instruction is performed in two types, the signed addition mode and the unsigned addition mode, By being able to select two types of generated address value ranges, it is possible to provide an address generation circuit that can reduce the number of instruction steps associated with address generation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the internal configuration of microinstructions of a one-chip signal processing processor, and FIG. 3 is a diagram showing the relationship between IDX and generated address contents in this embodiment. 4 is a diagram showing the state of the adder mode in this embodiment, and FIG. 5 is a diagram showing the state of the adder mode in this embodiment.
It is a circuit diagram showing a circuit. 20.21...Input terminal, 22...Output terminal. 23... Adder. 24... Index register, 25.26... Selector, 27... Sign bit extension inhibit gate, 28... Operation setting terminal.

Claims (1)

[Claims] In a one-chip signal processing processor, an index register that temporarily stores a modification setting address specified by an index operation instruction, and an output from the index register and an offset address specified by an operation instruction are added. An address generation circuit comprising: an adder; and a control circuit that controls whether or not to perform sign extension of the offset address input to the adder.