JPS62257219A - Input level setting system for analog/digital - Google Patents

Abstract

PURPOSE:To surely regulate an A/D converter input level within a prescribed range by providing a logic circuit receiving data of each bit of a shift register receiving a digital signal and a gain control means controlling the gain of a level amplification means. CONSTITUTION:An analog signal is inputted to an analog/digital converter 2 via a level amplification means 1 having a prescribed initial gain. The output is inputted to a shift register 3 and a data at each bit of the shift register is inputted to the logic circuit. The output from the logic circuit is inputted to the gain control means of the level amplification means 1 to change the gain of the level amplification means 1 thereby setting the input level of the A/D converter to be within the processing enable range of the A/D converter 2. Thus, the gain change of the means 1 is realized independently of manual operation, then the operation is facilitated remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an analog/digital signal that is commonly used in equipment that converts signals input using an analog digital signal into digital digital signals and performs recording. Concerning the level setting force formula for digital converter input.

BACKGROUND OF THE INVENTION Various devices are used to convert an audio signal input as an analog signal into a digital signal and record it on a magnetic tape or the like. Such a device consists of an analog signal input section, an amplifier circuit that amplifies the analog output from the input section, and an analog/'digital (hereinafter abbreviated as A/D) input section into which analog No. 13 from the amplifier circuit is input. ) converter;
The digital signal from the A/D converter is input, and includes, for example, a signal processing circuit that performs encoding processing for magnetic recording.

The A/D converter included in the above-mentioned device is a 6Δ/D converter in which upper and lower limit values of the level that can be digitized are set in advance based on the level of the input analog signal. When the input level of the A/D converter exceeds the upper limit value and/or the lower limit value, the A/D converter enters an overflow state, and a digital signal of the same level as the analog input of that level is output and recorded.

Therefore, when the level of the analog signal input to the 11τI\/D converter falls below the upper limit or lower limit, the gain of the amplifier circuit is changed to raise the A/D converter input level to the upper limit. It is necessary to set it so that it is within the range of 3 and/or the lower limit.

Problems to be Solved by the Invention Conventionally, the gain of the amplifier circuit has been changed manually by visually observing an input level meter installed in, for example, a digital sound recording device. Therefore, there was a problem in that it required rectification and that it was difficult to accurately adjust the gain.

An object of the present invention is to provide an analog/digital converter input level setting method that can solve the above-mentioned problems and reliably regulate the A/D converter input level within a predetermined range. It is.

Means for Solving the Problems The present invention comprises: a level amplification device to which an analog signal is input and whose gain is variable; an analog/digital converter to which an analog signal from the level amplification device is input; A shift register to which the pin No. 3 from the pin converter is input, a logic circuit to which the data of the 6 pins of the shift register is input, and an output from the logic circuit is given to control the gain of the level increase means. This is an analog/digital converter input level setting force type having a characteristic that it includes a gain control means.

The working analog signal is input to the analog/digital converter 2 through a level amplifying means having 2 inputs in a predetermined initial state. The output is input to the shift register, and
Data for each pin of the Trenostar is input to a logic circuit. The output from the logic circuit is input to the gain control means of the level amplification means to change the gain of the level amplification means,
Set the analog/digital converter input level to be within the processable range of the analog/digital converter.

Embodiment FIG. 1 is a block diagram showing the electrical configuration of an embodiment of the present invention, such as a digital J sound device, and FIG. 2 shows the principle of the electronic volume 1 which is the level amplification means shown in FIG. FIG. 3 is a block diagram showing the electronic volume 1.
FIG. 8 is a waveform diagram showing the output waveform during gain setting and the waveform after setting with lines No. 8 and No. 8, respectively. In the ff51 diagram, the analog U sound (H number is input to electronic volume 1, and the amplified analog number 4513 is input to A/D converter 2.
is input. The approximately 4-bit digital signal f3 output from the l\/D converter 2 is input to the shift register 3 of 4 bins F of A-D bits, and is held for each bit of the shift register 3. Ru. shift register 3
The signal processing circuit t to which the digital signal is input is,
The digitally converted signal is recorded and encoded and recorded on a recording medium such as a magnetic tape.

The second recording is performed, for example, by a magnetic disk 5 on a magnetic tape 6.

In connection with electronic volume 1, in order to input a level control signal to be described later to electronic volume II, open 1r arbitrarily.
Switch means 7 are provided.

One terminal 7a of the switch means 7 is connected to the electronic volume 1, and the other terminal 71+ is commonly connected to the counters 8 and 9. The counter 8.9 includes an A N D circuit 10.
Each of the 11 outputs is converted into 4 elements. The AND circuit 10 includes the inverted No. 42 of the D bit of the shift register 3 and the A N
D l1lil W612 Nodekado he person jJ
@Reru. The D bit No. 43 of the shift register 3 and the output of the NOR circuit 13 are input to the AND circuit 11 . The AND circuit 12 and the upper NOR circuit 13 are respectively input with the l~, n, and c bit signals of the shift register 3. Also, the electronic volume 1 is connected to a ladder resistance circuit consisting of resistors R1 to R5. Gain change amount setting means 1
5, and each resistance R1~ which constitutes the change amount setting means 15 and η.
Each terminal of R5 and line! 1~! 5 and a changeover switch means 1G connected by 5. In the initial state, the changeover switch means 16 is set to LINE! Signal output line J from 1! 6.

The changeover switch means 16 receives the signals from the counters 8 and 9.
1'' is input, the change-over switch means 1G changes the target for receiving the signal derived to the output line 16 to the line! 2
．． No.3. . . , 15. When the signal from the counter 8.9 is "0", the switching operation of the changeover switch means 16 is not performed.

In this embodiment, first, in order to input an equal sign for controlling the electronic volume 1, the switch means 7 is turned on. The output of the A/D converter 2 is transferred to the A N D circuit i 011 il by the shift register 3 as shown in Table 11 below.
12 and the NOR circuit 13, and output.

Table 1 shows the data formats of bits l\ to D of the shift register 3 and the output signals of the AAND circuits 10 to 12 and the NOR circuit 13 corresponding to each format. In Table 1, the AND circuit 10°11.12 and the NOR circuit 13 are represented by reference numerals 10 to 13, respectively. Also, the D bit of the shift register 3 performs a minus 7 lag function, and the remaining A - In C focus, a bell and a bell are expressed.

(Margins below) Table 1 For example, if the number of quantization bits of the A/D converter 2 is 4, then the shift register 3 is shifted in units of 4 bits.

When the input signal level to the A/D converter 2 as described above exceeds the upper and lower limits T I-11 and T H2 shown in the third figure, the outputs are as shown in the PtS1 table. :NO1,1G
This results in overflow.

Now, if an overflow occurs in the N ol state, the A, B, and C bits of shift register 3 will all become "1",
The AND circuit 12 outputs "1", and the counter 8 counts this as "1". When the next four bits are input to the shift register 3, if the respective bit data of the shift register 3 are in the same state, the counter 8 becomes "2", and if they are in different states, the counter 8 is reset.

First, if shift register 3 overflows in the state No. 16 in Table 1, A, B of shift register 3,
All C bits become "0", and the NOR circuit 13 becomes "1".
", and the D bit is "1", so both inputs to the l\ND circuit 11 are "1".

In other words, the output becomes "1", and the counter 9 compares this with "1". When the 0th order 4 bits/to is input to the shifter 3, in the same state, Oats<-70-. If so, the counter 9 becomes ``2'', and a random cent is made in a different state.

In this way, when either the counter 8 or 9 becomes "2", the Yukatsunta 8.9 outputs "1", and the electronic volume 1 uses this signal to decrease the gain by the unit setting amount. This circuit repeats the above operation and sets the gain of the first volume 1 to an appropriate value. After that, if the switch means 7 is shut off and the analog recording signal is input, the analog recording signal with the level waveform as shown in FIG. 2 (1) will be obtained.
The electronic volume 1 produces a waveform as shown in FIG. 2 (2), and the output of the A/D converter 2 does not exceed 70-.

If the quantization focus number of A/D converter 2 is different,
The number of bits of the shift register 3 may be prepared in the same number as the number of bits, and inputted to the A N D circuit 12 and the NOR circuit 13. Furthermore, the switch means 7 may be a switch means that conducts/cuts conduction using a timer.

Effects As described above, if the present invention is applied to Vt, the analog signal becomes
The signal is input to the analog/digital converter via a level amplification means having a predetermined initial gain. The output thereof is input to a shift register, and the data for each bit of the N7 register is input to a logic circuit. The output from the logic circuit is input to the gain control means of the level amplification means to change the gain of the level amplification means and set the analog/digital converter input level to be within the processable range of the analog/digital converter. do.

Therefore, the level of the analog/digital converter input is
The setting can be reliably set within the range that can be processed by the analog/digital converter, and the gain of the level amplifying means can be changed without manual operation, making repeat production much easier.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the principle of the electronic volume 1 shown in FIG.
Pt53 is a waveform diagram showing the analog signal waveform of gain fabrication 11 of this embodiment and the analog signal waveform after gain fabrication. 1...Amplifier, 2...A/D converter, 3...
Shift register, 7...Switch hand f2.8, 9...
・Counter, 10.11.12...A N D circuit,
13...NOR circuit agent patent attorney number of strokes Keibe part 2

Claims (1)

[Claims] Level amplification means to which an analog signal is input and whose gain is variable; an analog/digital converter to which the analog signal from the level amplification means is input; and a digital signal from the analog/digital converter is input. a logic circuit into which data of each bit of the shift register is input; and gain control means to which an output from the logic circuit is applied and which controls the gain of the level amplification means. /Digital converter input level setting method.