JPS6225334A - Instruction processing system - Google Patents

Abstract

PURPOSE:To perform in parallel the storage of the 1st and the 2nd instruction code groups in a queue storage means, conversion from the 2nd instruction code to the 1st instruction code, and the execution of the 1st instruction code. CONSTITUTION:An instruction code on an internal data bus 111 is the instruction code of a host device in native mode and an execution unit 102 is in the native mode, so an instruction code selector 104 selects the instruction code on the internal data bus 11 and the execution unit 102 decodes the instruction code to perform processing. In emulation mode, on the other hand, the instruction code on the internal data bus 111 is the instruction code of a low priority device and this instruction code is sent to a code conversion memory 105 and converted into the instruction code of the host device. The instruction code selector 104 selects the instruction code in the code conversion memory 105 and outputs the instruction code which is converted into a host device instruction to the execution unit 102.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an M:J that decodes instruction codes, and an arithmetic processing unit that executes four data processes under the control of circuits, which are integrated on a single semiconductor substrate. This applies to the instruction processing method of the information processing device.

[Conventional technology]

Recently, personal computers, office combinations, information processing projects, equipment such as -a
It is also widely used in ys. These information processing devices are
[Usage] The scope is wide, and the number of software accompanying it has also increased, and now there are a huge number of them.

In parallel with the increase in software, information processing equipment is also becoming more sophisticated and faster in line with user demands.

However, as new models are being commercialized one after another, the current situation is that even information processing equipment that has been commercialized as the latest model quickly becomes obsolete.

Conventional models (hereinafter referred to as lower models) have a lot of software available, but the instruction codes for lower models are
It is completely different from the instruction code of the latest models (hereinafter referred to as higher models). Compatibility between the software of the latest higher-end models and the software of older lower-end models has become a problem.

@Figure 8 is a configuration diagram of a conventional information processing device.

The CPU 801 is a microcomputer that executes the instruction set of the host model. The memory 802 stores programs to be executed and processing data, and is connected to the CPU 3Q1 and input/output device 802 via a bus. However, it is impossible for the CPU 801 to interpret it as an instruction code for a higher-level model and perform correct processing.

Furthermore, it is impossible to ignore this huge number of conventional software for lower-level models because it cannot be used for higher-level models. Therefore, up until now, the methods for using software for lower models on higher models are: 1) rewriting the source program of the software for lower models for the higher model and using it on the higher model; There was a way to create completely new software based on the instructions given.

However, the first method has the problem that it takes a lot of time to rewrite all the software currently available for lower-level models for higher-level models. In addition, the second method includes creating new software that is the same as the previous software, or
There is a problem in that it requires more man-hours and costs. In other words, the above two methods cannot be used now that the amount of software for lower +3A users is enormous. Therefore, conventionally, an information device 900 having a configuration as shown in FIG. 9 has been considered.

Next, the configuration and operation of the information processing device 900 will be explained with reference to FIG.

Figure 9 shows a microcomputer 9 that executes the instruction set of the host model.
01 and a microcomputer 902 that executes the instruction set of lower models.
2 is a block diagram of an information processing device 900 equipped with both 0 and 0. FIG. In FIG. 9, a microcomputer 901 that executes an instruction set of a higher-level model and a microcomputer 902 that executes an instruction set of a lower-level model are connected to an emulator control device 903. When executing software for a higher-level model, the address bus 905 and data bus 906 are connected to the microcomputer 901 that executes the instruction set of the higher-level model under the control of the emulator 1 controller 903, and the memory 904
Execute the program for the higher model in . When executing software for a lower model, an address bus 905 and a data bus 906 are connected to a microcomputer 902 that executes an instruction set for the lower model under the control of the industrial controller 903. Run the program for your model. In this way, software for both lower-level and higher-level models can be executed.

[Problem that the invention seeks to solve]

The conventional information processing device described above is equipped with two microcomputers, one for executing the instruction code of the higher-level model and the other for executing the instruction code of the lower-level model, which has the disadvantage that the system scale of the information processing device becomes large. . Along with this, there is also the drawback that the price becomes high. In addition, installing two microcontrollers means that when microcontroller 5 for executing instruction codes of the lower model is idle, the microcontroller for executing instruction codes of the other higher model is not used.
When a microcontroller for executing instruction code of a higher-level model is occupied, the other microcontroller for executing instruction code of a lower-level i*i is not being used, so only one microcontroller is always being used. , the disadvantage is that hardware is wasted.

[Means for Solving the Problems] The information processing device based on the present invention executes various data processing by sterilization of the decoding circuit that decodes the first instruction code group stored in the program storage means. 3 in a semiconductor integrated 1V circuit with an r6 arithmetic processing unit integrated on a single semiconductor substrate.
The instruction code group of multiple Dil and the second all-machine code 8p
storage means for storing the first instruction code group and Z20 command code group in the program storage means to the queue storage means; an execution means for executing a first instruction code group; and an enemy instruction code conversion storage means for generating a first instruction code group from a second instruction code group; storing the second instruction code group in the queue storage means, converting the second instruction code into the eleventh instruction code by the instruction code conversion storage means, and executing the first Ofi instruction code by the execution means. (to be executed in parallel).

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus related to the present invention. The ti↑ information processing device 100 has two modes: 1
One is a mode in which instructions are executed as instructions for higher-level models (hereinafter referred to as native mode), and the other is a mode in which instructions are processed as instructions for lower-level machines (hereinafter referred to as emirasin mode). The information processing device 1000 microcombi 1, -10] shown in FIG. It is equipped with The microcomputer 101 includes an execution unit 102, an input/output device 1103, an instruction code selector 104, a code conversion memory 105, a QUEUgl 06, and a fetch unit 10.
Consists of 7. The QUEUE 106 can store and store two or more instructions, and when read, sends the instructions one by one to the internal dataverse 111 in the order in which they were written. From QUEUE 106, QRDY signal 109 and QFULL signal 110, which are status signals of Qugugi 06, are sent.
is being sent. The QRDY signal 109 is sent to the execution unit 102 and the fetch unit 107, and eight
It shows whether there is an instruction code to be processed in QUEUE 106 or not. If there is an instruction code to be processed, the active level becomes "1". QFULL (
P! No. 110 is sent to the fetch unit 107 and indicates whether or not there is still room in the QUEU'FJ 106 to write an instruction code. QU
If the EUE 106 is unable to write an instruction code at once, it becomes active 1 novel ``1''''. If the QUIIEUE 106 is not used, the information processing device operates as shown in FIG. 4, and the execution unit 102 cannot read the next instruction food from the memory 108 until it finishes executing the instruction code. At any given time, only one of the processes, fetch or execute, can be performed. If Tokoi has QUEUE106,
Even if the execution unit 102 is executing the instruction code,
A fetch from the memo 1,110B is performed according to instructions from the fetch unit 107, and is stored in the QUEUE 106. QRDY signal 109 is active level "'1"
In this case, instruction codes are sent one after another from QUEUE 106, so that when the previous instruction code is taken into execution unit 102, the next instruction has already been sent from QUEUE to internal data bus 111. Therefore, the fifth
As shown in the figure, fetch and execution are performed in parallel, and the processing time is reduced compared to the case without QUhCUE as shown in FIG.

The fetch unit 107 has QUEUE 106
D) QRDY MM 109 S Yohi QFULL
110, QUEUE 10 is sent from the memory 108.
Write the instruction to 6 at 11@. QFULL (
: No. 3 110 is an inactive 1 novel ″′0″′,
QRI) When the Y signal 109 is at active level "'1".

QUEUE 106 still has room to write instructions, and QFULL signal 110 is inactive level 1.
0" and the Q, R, D Y signal 109 is also inactive 1/bell "'0"', the QUEUE 106 does not contain an instruction to be processed, so the fetch unit 10
From 7, the At1nos information is sent onto the internal address 113 and sent to the memory 10 via the external At1/S bus 114.
Uke is taken on 8th. Then, the instruction code is sent from the memory 108, and the external data
F; 106 ic write n, stored. QUB
When the Ug 106 becomes full, the QFULL signal 110 becomes an active level "1" and the fetch unit 107 no longer sends out the at-I-space information. Q
When the F U L L signal 110 becomes inactive level “0”, the QUEUE 1 is output from the memory 108 again.
The instruction code is written to 06.

The code conversion memory 105 stores a code conversion table for converting instruction codes of a lower model into instruction codes of an upper (one model).

The instruction code 1/actor 104 is connected to the internal data bus 111.
Either the above code or the converted instruction code in the code conversion memory 105 is selected and sent to the execution unit 102.

The memory 108 stores programs to be executed by the microcomputer 101 in native mode, programs to be executed in emulator mode, processing, and environment data.

Inside the execution unit 102, a program counter (hereinafter referred to as PC) 115, a program status word (hereinafter referred to as PSW) 116.1/register group 11
7 is included.

P8W116 has a mode setting flip-flop 11 for setting native mode and Emmy1/-thin mode.
8 is installed. There are also two flags, a carry flag, etc., but they are not shown in this figure. When this mode setting flip-flop 118 is @1'', the single-chip microcomputer 101 is in native mode,
Interprets and executes the fetched instruction code as an instruction code for the upper model. Furthermore, when the mode setting flip-flop 118 is '0'', the single-chip microcomputer 101
enters emulation mode and processes the fetched instruction code as an instruction code for a lower model.

The command processing executed by the execution unit 102 will be described below with reference to the flowchart of FIG. MOV is
Transfer commands transfer data between registers, 17 registers and memory, direct data transfer of l/registers, or direct data transfer of 0 to memory. AI:)
D is an addition instruction, i/jistabras 17jista, 1
/disk plus memory, memory plus 1/disk plus memory, 1/
Processes the register plus data and memory plus data, and stores the calculation results in 1/register or memory.

SUB is a decrement 3J instruction, register minus register,
register minus memory, memory minus register, 1
Processes 7 register minus data and memory minus data and stores the results in 1 register or memory. INA,n is an input/output command that transfers data stored in the at 1/slot of the input/output device f#103 specified by the second operand to the accumulator input. OUT
, k, n are input/output instructions that transfer the contents of accumulator A' to address n of the input/output device 103 specified by the second operand. INT is an interrupt instruction, I
When NT is executed, the PC115 and PSW115 are saved in the stack area and branched to a predetermined interrupt vector. Then, the mode setting flip-flop 11 in the PSW 116
Forcibly set to 8 to enter native mode. 11
The 18 T I instruction is an instruction for returning to the main program. When this instruction is executed, the P C, P 5W12') information before the interrupt instruction saved in the stack area is restored, and the program returns to the main program again.

Next, the operation of the information processing device 100 will be explained. Since the C information processing device 100 uses the QUg[J'2 106, even if the execution unit l-102 is executing an instruction code, a fetch from the memory 108 is performed according to an instruction from the fetch unit 107.

It is stored in QUEUE 106. QRDY signal 10
9 or active l/bell 11”, QUEUE1
Since instruction codes are sent out one after another from QUEUE 106 onwards, when the previous instruction code is received into the execution unit 102, the next instruction has already been sent out from the QUEUE 106 to the internal data bus 111. The operations up to this point are common to both the native mode and the Emmy 17-mode. Vc < a work is eutive mode and emi x l
/- Shimin mode will be explained separately.

First, the case of native mode will be explained.

The instruction code on the internal data bus 111 is an instruction code of a host model. Since the execution unit 102 is operating in native mode, the instruction food selector 104 selects the instruction code on the internal data bus 111 and outputs it to the execution unit 102.

Execution unit 102 decodes this instruction code and processes each instruction described in FIG. At this time, the next eight instruction codes have already been output onto the internal data bus 111, and the process is waiting for the previous instruction code to finish processing. In this manner, as shown in FIG. 5, fetching of the instruction code and execution of the instruction code are performed in parallel, so the processing time is reduced compared to the case without QUEUE as shown in FIG.

Next, the case of emulation mode will be explained. The instruction code on the internal data bus 111 is the instruction code of the lower model. The instruction code of the lower model is sent to the code conversion memory 105, and is converted into the instruction code of the higher model by the code conversion table in the code conversion memory 105. That is, when the code conversion memory 105 inputs the instruction code of the MOV instruction for the F-rank model, the code conversion memory 105 converts the MOV instruction code for the lower model.
When the instruction code of the MOV instruction for higher models that performs the same processing as the V instruction is input, and the instruction code of the ADD instruction for lower models is input, the instruction code of the ADD instruction for higher models that performs the same processing as the ADD instruction for lower models is converted. Convert to code. Since the execution unit 102 is operating in the emulation mode, the instruction code selector 104 selects the instruction code in the code conversion memory 105 and outputs the instruction code converted to a higher-level model instruction to the execution unit 102. The execution unit 102 decodes this instruction code and executes MOV.
If the transfer is ADD, if the addition is SUB,
Perform subtraction. The operation of execution unit 102 after converting the instruction code is similar to that described in FIG.

At this time, the next instruction code has already been converted.

As described above, as shown in Fig. 7, instruction code fetch, instruction code conversion, and instruction code execution are performed in parallel (7), so the processing time is reduced compared to the case where QUEU is not used in Fig. 6. be done.

〔Effect of the invention〕

As explained above, the present invention has the function of executing the instruction set of the lower model and the function of executing the instruction set of the higher model, so it has the advantage of being able to execute software for both the lower model and the higher model. be.

In addition, since the information processing device according to the present invention uses an instruction code conversion memory, the microcontroller that has the function of executing the instruction set of the higher-level model can also process the instructions of the lower-level model without installing two microcontrollers. Since it is possible to do so, there are two microcontrollers: one for lower-level models and one for higher-level models.
It can be made smaller compared to information processing equipment that used to have one housing, and
There is also the advantage that cost reduction is possible.

Furthermore, the information processing device related to the present invention includes QUEUE.
Since the instruction code is not read from the memory every time the instruction is processed, the instruction code is fetched and executed in parallel, resulting in faster program processing speed. .

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of the r# report processing unit a according to the present invention.
The figure is a flowchart in native mode, the WJ3 figure is a flowchart in emulation mode, Charmy 1, the fourth factor is a time chart when QU13UE is not used, and the fifth
The figure is a time chart of 1 using QIJEUE,・■
Figure 6 shows QU'E in the 1n information processing device according to the present invention.
47 is a time chart when QUEUE is used in the information processing apparatus 3 according to the present invention, and FIG.
The upper rack without the link function (I block diagram 1, 9th
The figure is a configuration diagram of a conventional quadruple high-level machine with an EMI x l/-john function for lower-level models. 102... Execution unit, 103... Input/output device, 104-... Instruction code selector, 1
05... Code conversion memory, 106...
・QUEUE, I O7...Fetch unit, 108...Memory, 109...Q,
RD Y signal, 110...QFULL signal,
111...inner g1! Dekubus, 112...
... External data bus, 113 ... Internal address bus, 114 ... External address bus, 115
゛Old゛PC1116...psw, 117...
...1/Jister, 118...Mode 1α constant flip-flop, 801...CPU, 802
...Memo! J-803...Input/output device, 901...Microcomputer for higher-end models, 902...
・・・・Bottom・Microcontroller for Cryiso species, 903・・・・・・℃
Mu1/- John space device, 904... Memory, 905... Address bus, 906...-
・Data bus. Agent: Susumu Uchihara, patent attorney

Claims (1)

[Claims] In a semiconductor integrated circuit in which arithmetic processing units that perform various data processing are integrated on a single semiconductor substrate under the control of a decoding circuit that decodes a first instruction code group stored in a program storage means, a plurality of storage means for storing a first instruction code group and a second instruction code group; and instruction reading means for sending the first instruction code group and the second instruction code group in the program storage means to the storage means. and execution means for executing the first instruction code group;
instruction code conversion storage means for generating the first instruction code group from the second instruction code group;
storing the instruction code group and the second instruction code group in the storage means, converting the second instruction code into the first instruction code by the instruction code conversion storage means, and executing the instruction code. An instruction processing method characterized in that the execution processing of the first instruction code by means is executed in parallel.