JPS62250671A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of leakage and latch-up and thereby to secure a normal operation, by a construction wherein an element region inside an insular region is surrounded by a P-type high-concentration impurity layer, while an oxide film having the same film thickness as a gate oxide film is provided on the insular region except the element region and under a gate electrode. CONSTITUTION:The title device has a structure wherein an annular P<+> layer 6 is so provided as to surround an element region 3a separately therefrom and one end of a gate electrode 8 overlaps partially with the P<+> layer 6, while an oxide film 9 having the same film thickness as a gate oxide film 7 is provided on an insular region 3 except the element region 3a and under the gate electrode 8. Therefore, a thick parasitic transistor of the oxide film is not formed in the end portion of a gate. When radiations are applied, accordingly, the leakage due to the application of radiations can be prevented from occurring between source and drain regions 4 and 5, as is the case with prior art, and therefore a transistor operates normally.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor device, and particularly to a MoS transistor that can operate normally in an environment exposed to radiation.

[Technical background of the invention and its problems]

As is well known, when a MoS transistor is irradiated with radiation such as gamma rays, fixed charges accumulate in the oxide film and surface states are generated, which shifts the threshold voltage (Vtb) in the negative direction and reduces the channel mobility. is degraded by 1 Ru (R, Freema)
n et al,, I E E E Trans.

Nucl, Sci, N5-25. No, 6. I)1
216.1978>. Specifically, radiation causes NMO
Since the threshold voltage of an S transistor is shallow and that of a PMOS transistor is deep, lowering the process temperature (G, W, Hut) is required.
5solid 5tate TeChnOIOQV
Suppression of element parameter fluctuations due to factors such as P, 70° 1979) is progressing.

By the way, the amount of threshold voltage shift due to radiation is proportional to the second to third power of the oxide film thickness (G, F, Derbenwick
k etal,, I E E E Trans,
Nucl, Sci, N5-22. No, 6. p2
151.1975), the threshold voltage changes significantly in a parasitic MOS transistor formed through a thick field oxide film. Therefore, the parasitic field transistor formed at the end of the gate is always on, and leakage occurs between the drain and source regions. A problem arises in that a normal transistor cannot be obtained due to the occurrence of current.

Furthermore, in a bulk C (complementary type) MOS, radiation turns on a parasitic thyristor, causing latch-up. Moreover, radiation causes latch-up not only in input/output circuits but also in internal circuits, but conventionally no latch-up measures have been taken to extend to internal circuits.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is designed to prevent leakage and latch-up caused by a drop in threshold voltage of a parasitic MoS transistor made of a thick field oxide film at the gate end due to radiation exposure. An object of the present invention is to provide a semiconductor device that operates normally.

[Summary of the invention]

The invention of cylinder 1 surrounds the element region within the island-like region with a P-type high concentration impurity layer while being separated from the element region, and
The gate electrode is provided so that one end thereof partially overlaps with the high-1 degree impurity layer, and an oxide film with the same thickness as the gate oxide film is provided on the island-like region excluding the element region and under the gate electrode. The main feature is to prevent leakage and latch-up caused by a decrease in the threshold voltage of a parasitic MOS transistor, and to ensure normal operation.

The invention of the present invention 2 differs from the invention of the present invention 1 in that a particularly high-concentration P-type impurity layer is provided on the substrate surface of the field oxidation layer rather than under the field oxide film, and one end of the first gate electrode is This differs in that it is provided so as to reach the concentrated impurity layer, and in addition to achieving the same effects as the invention of cylinder 1 of the present application, it is intended to simplify the process.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 Please refer to FIGS. 1 to 3. Here, Figure 1 shows NMOS
A plan view of the transistor, FIG. 2 is a sectional view taken along the line AA in FIG. 1, and FIG. 3 is a sectional view taken along the line BB in 1rA.

1 in the figure is a P-type silicon substrate. The surface of this substrate 1 has field oxidation I! (Shaded area in Figure 1) 2
is provided. In the island region 3 surrounded by the field oxide 112, there is an N+ type source/drain region 11i.
4.5 are provided spaced apart from each other. Furthermore, on the surface of the substrate below the field oxide 11!2, a ring-shaped P+ layer (marked with It is set in.

A gate electrode 8 is provided on the island region 3 with a gate oxide film 7 interposed therebetween. Here, one end (right end) of this gate electrode 8 extends over the field oxide 1!2 and partially overlaps the P+ layer 6. Furthermore,
Said steel island 11 surrounded by said field oxidation 11!2
An oxide layer 9 having the same thickness as the gate oxide WA7 is provided above the gate electrode 3 (excluding the element region) and below the gate electrode 8.

According to the first embodiment, the annular P'' 116 is the element region 3a.
The gate electrode 8 is provided so as to surround and be separated from the P+ layer 6, and one end of the gate electrode 8 partially overlaps the P+ layer 6, and an island-like region 3 excluding the element wA region 3a.
Above and below the gate electrode 8 is the same as the gate oxide film 7.
Since the structure includes the thick oxide film 9, a parasitic transistor with a thick oxide film is not formed at the gate end. Therefore, when exposed to radiation, it is possible to prevent leakage caused by radiation between the source and drain regions 4.5 as in the conventional case, and the transistor operates normally. Furthermore, when the present invention is applied to a 0MO8 transistor, P+
Since the potential of the P-type silicon substrate 1 is equal to the source potential due to the presence of the layer 6, it has excellent resistance to latch-up and improves overall radiation resistance.

Example 2 Please refer to FIGS. 4 to 6. Here, Figure 4 shows NMo5
A plan view of the transistor, FIG. 5 is a sectional view taken along line A-AI in FIG. 4, and the sixth factor is a sectional view taken along line BB in FIG. 4. In addition, the same members as in Example 1 are given the same reference numerals, and the description thereof will be omitted.

21 in the figure is a first field oxide film provided on the surface of the P-type silicon substrate 1. As shown in FIG. The substrate surface inside the first field oxidation 1121 is provided with a second field oxidation! 22.22 is provided. In the island region 23 surrounded by the second field oxide film 22.22, N+ type source/drain regions 4.5 are provided spaced apart from each other. On the surface of the substrate 1 between the first and second field oxide films 21 and 22, a layer is formed so as to surround the element region 23a in the island region 23 at a distance therefrom.
A partially cut-out annular P+ layer 24 is provided. A gate electrode 25 is provided on the island region 23 via the gate oxide film 7, and one end of the gate electrode 25 is connected to the P+
The end of layer 24 has been reached. In the NMo5 transistor having such a structure, the P+ layer 24 is connected to the gate electrode 23.
It is formed in a self-consistent manner.

According to the second embodiment, similarly to the first embodiment, a parasitic MOS transistor with a thick oxide film is not formed at the gate end. Therefore, when exposed to radiation, it is possible to prevent leakage caused by radiation between the source and drain regions 4.5 as in the conventional case, and the transistor operates normally. Also,
When the present invention is applied to a CMOS transistor, P4''
Since the potential of the P-type silicon substrate 1 is equal to the source potential due to the presence of the four-layer type 4, resistance to latch-up is excellent, and radiation resistance is improved overall. Furthermore,
Since the P+ layer 24 is formed in a self-aligned manner with respect to the gate electrode 25, PM
The P" type source/drain region of the OS transistor and the
The two layers can be formed in the same process, simplifying the process.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a highly reliable semiconductor device that can prevent leakage current and latch-up caused by radiation exposure and can operate normally.

[Brief explanation of drawings]

FIG. 1 is a plan view of an NMO8 transistor according to Example 1 of the present invention, FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1, and FIG. 3 is a cross-sectional view taken along line B-B in FIG. FIG. 4 is a plan view of an NMOS transistor according to the second embodiment of the present invention, and FIG.
The figure is a sectional view taken along line AA in FIG. 4, and FIG. 6 is a sectional view taken along line 8-B in FIG. 4. 1...P-type silicon substrate, 2.21.22...Field oxide film, 3.23...Island region, 3a, 23
a... Element region, 4... N1 type source region, 5...
...N+ type drain region, 6.24...P+ layer (high concentration impurity layer), 7...gate oxide film, 8.25...
- Gate electrode, 9... oxide film.

Claims (2)

[Claims] (1) A P-type semiconductor substrate, a field oxide film provided on the surface of this substrate, source/drain regions provided spaced apart from each other in an island-like region surrounded by this field oxide film, and the field oxide film. A P-type high-concentration impurity layer is provided on the substrate surface below the film so as to surround the element region in the island-like region in a state that is spaced apart therefrom, and a P-type high concentration impurity layer is provided on the island-like region via a gate oxide film. a gate electrode provided with one end partially overlapping the high concentration impurity layer;
A semiconductor device comprising: an oxide film having the same thickness as the gate oxide film provided on the island region excluding the element region and under the gate electrode. (2) a P-type semiconductor substrate, a first field oxide film provided on the surface of this substrate, a second field oxide film provided on the surface of the substrate inside this field oxide film, and a second field oxide film provided on the surface of the substrate inside this field oxide film; a source/drain region provided spaced apart from each other in an island region surrounded by a field oxide film, and an element region in the island region on the substrate surface between the first and second field oxide films. a P-type high-concentration impurity layer provided so as to surround and be spaced apart from this, a gate electrode provided on the island-like region via a gate oxide film and having one end reaching the high-concentration impurity layer; A semiconductor device comprising: an oxide film having the same thickness as the gate oxide film provided under the gate electrode on the island-like region excluding the region.