JPS62247686A - Special reproduction circuit - Google Patents

Abstract

PURPOSE:To halve the number of noise pieces appearing on a reprorduced screen by extracting the 1st write/read switch signal in a field and then the 2nd write/read switch signal having a opposite phase to that of the 1st switch signal in the other field. CONSTITUTION:The reproduction FM video signals obtained by the pair of video heads having different azimuths are amplified by a preamplifier 1 and converted into the reproduction video signals by a video signal processing circuit 2. While the output of the amplifier 1 undergoes the envelope wave detection via a wave detecting circuit 6. This wave detection output is compared with the reference voltage by a comparator 7 and converted into the 1st write/read switch signal. This switch signal is used as the switch control output of a field memory 3 when an RF switching pulse is kept at a high level. Furthermore the 1st switch signal is also supplied to an address memory 8 and the 2nd write/ read switch signal having an opposite phase to the 1st switch signal is outputted from the memory 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [A] Field of Industrial Application The present invention relates to a special playback circuit for a video tape recorder of a T2 head helical scan type with a switching noise of all phenomena.

(o) Conventional technology A video tape recorder using the 2-helf scan system for even-numbered speed playback by fully utilizing the field memory is disclosed, for example, in Japanese Patent Laid-Open No. 6 [J-57890]. .

In these video tape recorders, the position of the noise bar during even-numbered multiple speed playback is based on the fact that the position of noise on the playback screen does not overlap in even-numbered fields and in even-numbered fields. Figure 5 shows the relationship between the azimuthally recorded recording track pattern and the 4x reproduction scan trace (r), which is derived by replacing the video signal with a reproduced video signal including noise bars.
As shown by the hatching, the playback FMI starts from the part where the azimuth of the playback head and the azimuth of the recording track match.
I! Hiiragi (* signal is obtained 0 This reproduced F'M video signal (
A) The attenuation positions in the Fra field and the even field are different. The comparator output (8) obtained by envelope detecting this FM playback video signal and inputting it to the comparator becomes a low level between points a and 0, points 0 and d, and points e and 1 as shown in the figure. , the field memory read signal is derived at three locations during one frame period.
The reason is that the signal switching timing on the playback screen is illustrated.

Problems to be solved by the H invention [7]However, when the above-mentioned groove bottom is adopted, six switching noises occur on the screen.This switching noise matches the total number of fields and even 197 yield. In order to reduce the number of noise lines to three in total, it is a good idea to adjust the reference level of the comparator appropriately. However, in a video tape recorder, the level of the reproduced FM signal is not constant, and it is difficult to completely eliminate switching noise. 0) Problem? Therefore, according to the present invention, the playback FMI 1% in one field is
a comparator that inputs the envelope output of the image signal and supplies a field memory @1f inclusive derivation switching signal; and an address that stores a specified address to the field memory corresponding to the switching timing of the 818 inclusive readout signal in one field. and a memory control circuit which generates a second write/derive switching signal having an opposite phase to the first write/derive switching signal based on a read address obtained from the address memory in another field. Characteristics 0 (E) Operation Therefore, according to the present invention, the first v-include derivation switching signal is output from the comparator in one field, and the first @-include derivation switching signal is output from the storage control circuit in the other field. A second input switching signal having an opposite phase is derived.

(f) Example Hereinafter, the present invention will be explained according to an illustrative embodiment.

In this embodiment, when the rx RF switching pulse is at low level, the comparator derives the V first write derivation switching signal, and when it is at high level, the 241' inclusive derivation switching signal is derived from the storage control circuit. As shown in FIG. 2, the positions where the switching noise occurs in the odd and even fields are made to coincide with each other, thereby effectively reducing the noise.

Fig. 1 ζ Circuit block diagram of this embodiment? As is clear from the reasons shown, azimuth? Playback FMII obtained from a pair of different videos! The IIL image signal is amplified by a preamplifier, inputted to a video signal processing circuit 12ζ, and converted into a reproduced video 1g. On the other hand, the preamplifier output is input to a detection circuit +61 and subjected to envelope detection. This envelope detection output (61) is input to the comparator 17+, compared with the reference voltage, and converted into the first write derivation switching signal. When , the third switch (S
3), the first and second swifts ($1 claw 8
2) and field memo January 31 switching control input.

Field memo January 31H1 Input playback video signal 2 AD converted data stored and read out All D
In order to derive A conversion, an AD conversion circuit for input and an OA conversion circuit for output are arranged at the input/output common terminal of the digital memory. AD that is stored one field before the specified address when AD conversion data is stored and read.
Reading conversion data.

Therefore, when the first write derivation switching signal, which is the comparator output, is in a high level state, the 7π1/whistle 2 switch (Sl) (32) is set to write 1ull L W ), and the first switch (Sl ), the entire reproduced video signal No. 1 is derived as it is, and the reproduced video signal is stored in the designated address of the field memory 131 by the @ notation 2 switch (S2), and when it is in the low level state, both the switches L Sl> (82 ) Hochiri side (RIK is set,
The half 2 switch (S:23) derives the entire reproduced video signal of one field before, which is obtained from the address specified in the field memo January 31.

The specified address for specifying the reading or subtracting position for the field memo 31 is derived from the address specifying circuit 14+, which inputs the total count of the clock signal. This clock signal a, color subcarrier frequency & number fs c2a
Address memo January 8 is derived from the multiplying black signal generation circuit 15+, and is also input to the field memory 13+, and is also used as a timing pulse for LADLAD conversion.
1, and when the RF switching pulse is at a high level, the designated address and inversion direction are stored in the inversion typing of the ONI 11 write/read switching signal. This address memory is in a continuous state when the RF switching pulse is at low level, and inputs the specified address and inversion direction information to the storage control circuit +9+. When the specified address from the address designation circuit (1j) matches the specified address from the address memo January 81, the second write derivation circuit inverts the corresponding reversal direction information. A switching signal is derived.Therefore, the 14th continuous write switching signal and the second write-in derivation switching signal are inverted at the same specified address, and the inversion directions are mutually opposite. When the RF switching signal is at the lawn bell, the switching signal is input to the first and second switches (811 (32) and field memo 31 through the third switch (s6+i). Therefore, the field memory (3) The write and successive conditions are completely opposite to those of the preceding field, and a reproduced video signal that causes switching noise is derived from the first switch (Sl) with the same typing as the preceding field.

Therefore, the noise on the playback screen is limited to three lines as shown in FIG.

()J Effects of the Invention According to the present invention, the switching noise generation position in the tsuba number field and the even number field becomes common,
The number of noise on the playback screen will be reduced by half.

[Brief explanation of drawings]

Claims (1)

[Claims] (1) Run the tape at an even number times the speed of playback at an even number multiple speed during recording, store the high level portion of the reproduced FM video signal in the field memory, and record the low level portion of the reproduced FM video signal. In a two-head helical scan type VTR that derives a read video signal from the field memory in place of the reproduced video signal, the envelope detection output of the reproduced FM video signal is input to one field and the first record of the field memory is input. a comparator that supplies a write/read switching signal; an address memory that stores a specified address to the field memory corresponding to the switching timing of the first write/read signal in one field; and a storage control circuit that generates a second write/read switching signal having a phase opposite to that of the first write/read switching signal based on a read address.