JPS62247653A - Constitution of packet exchange - Google Patents

Abstract

PURPOSE:To improve the circuit efficiency by storing a header part for analysis after delaying a packet for a fixed period of time by a buffer, selecting an outgoing circuit out of the idle circuits for allocation and transmissing immediately the packet under reception to a terminating station. CONSTITUTION:The packet input received from an incoming circuit 1 undergoes the protocol processing 2 and is delayed by a buffer part 3 for a fixed short time. At the same time, a header analyzing part 4 stores the header part for analysis. A transmitting destination is detected and an outgoing circuit request signal 5 is transmitted to a conflict circuit 11. The circuit 11 chooses an idle circuit to transmit an outgoing circuit allocating signal 6 to the part 4 of a transmission requester. At the same time, the circuit 11 controls 14 the open/ close of a switch 15 by a switch control signal 12 to close a switch set within the switch 15. Thus the part 4 transmits immediately the packet under reception to a terminating station. As a result, the traffic concentration never occurs at a specific circuit. Then the delay time is shortened and the circuit availability is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a packet switch, and is particularly suitable for a high-speed packet switch that accommodates a large number of high-speed lines, and which exchanges packets without storing them in the switch. Regarding the configuration method.

[Conventional technology]

Regarding the configuration method of high-speed packet switching equipment that accommodates a large number of high-speed lines, please refer to IEICE technical research report 5E85-91.
r high-speed packet switching system” and 5E85-123 r
As discussed in ``Study of configuration capability of high-speed multi-packet switching system with broadcast function'', the configuration is such that packet processing is performed individually on each line, and furthermore, packets are stored on each line.

[Problem that the invention seeks to solve]

In the above conventional technology, the packet routing process is a fixed routing for each call, and the packet traffic to the line is uneven, making it impossible to use the line efficiently, and furthermore, the delay time of the switch increases by the time it takes to accumulate packets. . As a result, in response to an increase in traffic, it is necessary to take into account the imbalance in traffic and increase the number of lines by more than the amount of traffic increase.Furthermore, because the delay time at the exchange is large, it is necessary to increase the number of lines between computers that require high-speed processing. There is no choice but to impose restrictions on connections between local area networks that require high-speed communications and high-speed communications.

[Means for solving problems]

The above purpose is to analyze the header part of the packet received for each line with a competing circuit that has the function of selecting one free line from multiple destination lines according to a predetermined priority order in packet routing processing. and determine the landing point,
A header analysis unit that issues a request to the competing circuit, a switch control unit that controls the switch between the traffic lines, and a delay buffer that delays the packet by the time necessary for the processing are used to switch between the traffic lines. This is achieved by controlling and exchanging packets.

[Effect]

The contention circuit described above allocates an idle line in response to an outgoing line allocation request generated for each incoming line packet, thus enabling dynamic routing for each packet. Also, the header analysis section mentioned above.

Once the headers are accumulated, the incoming station analysis and outgoing line request are sent to the above-mentioned competing circuit, and the above-mentioned switch control unit connects the idle line selected by the above-mentioned competing circuit to the incoming line,
By storing packets in the delay buffer described above during the processing and sending them out, packets can be exchanged with a short delay time.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
In the figure, 1 is an incoming line, 2 is an incoming line protocol processing unit, 3 is a delay buffer, 4 is a header analysis unit, 5 is an outgoing line request signal line for competing circuits, 6 is an outgoing line allocation signal line, and 7
is the control signal line between the protocol processing section and the delay buffer,
8 is a delay buffer input line, 9 is a control signal line between the protocol processing section and the header analysis section, 10 is a switch input line, 11
12 is a switch control signal line, 13 is an outgoing line use signal line, 14 is a switch opening/closing control unit, 15 is a switch, 16 is a switch output line, and 17 is an outgoing line. The protocol processing unit 18 is an outgoing line.

Note that the delay buffer 3 can be configured using a first-in-first-out memory or a normal random memory, and since the operations of the header processing section 4, contention circuit 11, and switch opening/closing control section 14 can be easily patterned, read-only memory can be used. It can be configured by using wiring logic or storage program control using a microprocessor.

In FIG. 1, the incoming line protocol processing unit 2 is an HDLC
It deletes zeros from frames, detects frames with less than 32 bits, and detects frame errors based on the procedure, and notifies the delay buffer 3 and header analysis unit 4 of the detected abnormalities through the control signal line 7 or 9.

The header analyzer 4 takes in the header part of the packet from the delay buffer input line 8, analyzes the destination, determines the destination station, and issues an outgoing line allocation request to the competition circuit 11 via the outgoing line request signal line 5 corresponding to the destination station. The competition circuit 11 selects one outgoing line request from the header analysis unit 4 corresponding to each incoming line 1, searches for an empty line using the outgoing line use signal line 13 from the switch opening/closing control unit 14, and selects the selected outgoing line request. Allocates a vacant line to the switch opening/closing control unit 14 and issues an instruction to close the corresponding contact of the switch 15 via the switch control signal line 12.At the same time, a response is sent to the header processing unit 4 corresponding to the selected outgoing line request via the outgoing line allocation signal line 6. return it. The competition circuit 11 continues to repeat the above process until there are no outgoing line allocation requests, and if there are no free lines during the process, the process is interrupted until a free line is available. The header analysis unit 4 receives a response from the competition circuit 11 via the output line allocation signal line 6.

A sending instruction is issued to the delay buffer 3, and the request continues to be issued via the outgoing line request signal line 5 until the packet is completely sent out from the delay buffer 3. The delay buffer 3 stores the packet received from the delay buffer input line 8, delays it until it receives a transmission instruction from the header analyzer 4, and then sends the packet to the switch 15 via the switch input line 10. The packets exchanged by the switch 15 are sent to the outgoing line protocol processing unit 17 via the switch output line 16.
sent to. The outgoing line protocol processing unit 17 is an HDLC
Perform O insertion and Fe2 addition based on the procedure, and connect the output line 1.
Send packet to 8.

Through the processing described above, the baquerato that entered from the incoming line 1 is delayed by the total time of the header accumulation time and analysis time in the header processing unit 4, the processing time of the competition circuit 11, and the processing time of the switch opening/closing control unit 14, and then is transmitted to the outgoing line. is sent to the next station. Note that the header processing unit 4, competition circuit 11, and switch opening/closing control unit 14 can be easily wired and logicalized as described above, and can be sufficiently increased in speed even with the current technological level.
The packet exchange delay time can be made sufficiently smaller than when all packets are stored.

It is also possible to configure a configuration in which the incoming line protocol processing unit 2, control signal lines 7 and 9, and outgoing line protocol processing unit 17 in FIG. 1 are omitted, and the operation is the same as that described using FIG. Therefore, the explanation will be omitted here. Further, the switch 15 may be configured using a bus, a loop, or the like instead of an open/close switch.

As explained above, according to the present invention, by selecting an empty line from a plurality of outgoing lines for each packet, it is possible to prevent traffic from concentrating on a specific line, and all lines can be used equally. It is possible to improve the usage efficiency of moreover,
Since the packet delay time can be made the sum of the header accumulation time and the routing processing time, the delay time can be reduced by a proportional amount when all packets are accumulated and then processed.

〔Effect of the invention〕

According to the present invention, it is possible to realize dynamic routing for each packet, so it is possible to prevent traffic from concentrating on a specific line, improve the efficiency of line usage, and furthermore, it is possible to perform exchange by simply accumulating packet headers. Since the operation can be started, it is effective in reducing the delay time of the exchange.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a packet switch according to the present invention. 1... Incoming line 2... Incoming line protocol processing unit 3... Delay buffer 4... Header analysis unit 5... Outgoing line request signal compatible with competing circuits 6... Outgoing line allocation signal 7 ... Control signal between the protocol processing section and the delay buffer 8 ... Delay buffer input line 9 ... Control signal between the protocol processing section and the header analysis section 10 ... Switch input line 11 ... Output line Selection competition circuit 12... Switch control signal 13... Outgoing line use signal 14... Switch opening/closing control unit 15... Switch 16... Switch output line 17... Outgoing line protocol processing unit 18...・Outgoing line diagram 1

Claims (1)

[Claims] In a packet switch, there is a buffer memory that can add a delay by a predetermined amount of time, a block that has the function of storing and analyzing the packet header part, and determining the destination, and a block that manages the arrival according to the requests of the said block. It has a block that has the function of monitoring and extracting the free line, and a switch that has the function of closing the switch between the free line selected in the block and the line of the request source to which this free line is assigned, and supports incoming calls. A configuration of a packet switching device characterized in that it manages a plurality of lines, allocates an idle line for each packet, immediately extracts the idle line after storing the header part, and starts transmitting the packet being received to the destination station. method.