JPS6223894B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high performance data processing device having a dedicated service processing device.

In the field of recent high-performance data processing equipment, in addition to a central processing unit (hereinafter abbreviated as CPU) and a main memory unit (hereinafter abbreviated as MMU), they are equipped with a dedicated service processing unit (hereinafter abbreviated as SVP). .

SVP controls the operation mode of the CPU, MMU, and comprehensive data processing system including the CPU and MMU, observes the internal state of the CPU, collects data when a failure occurs, performs failure recovery work, and general maintenance work. This is a device that is installed independently outside the CPU to control the following. Therefore, SVP is a dedicated CRT.
It may be equipped with a display (cathode ray tube display device), and can be used to respond to various service requests such as those listed above.
By organizing the data from the CPU using the SVP's own program and displaying it on the CRT display, the operability and maintainability of the data processing device can be significantly improved.

In conventional data processing devices that have a dedicated SVP, the SVP and CPU are directly connected by a data bus and multiple independent control signal lines, and some CPUs have separate functions for executing instructions. Hardware or (and) microprograms are provided for executing various service requests, and this hardware or microprogram controls the signals on the control signal line and the data bus. Data input/output is performed.

In such a conventional data processing device, hardware is required for each request in response to a request from the SVP, which increases and complicates the hardware in the CPU. Furthermore, since it is wired logic, the operation for one service request is uniquely determined and cannot be changed, resulting in lack of expandability and flexibility. In addition, a microprogram dedicated to service request processing is required in the CPU, and instruction execution stops during service request processing.
This results in a decrease in CPU processing power. Also, when transferring data indicating the internal state of the CPU to the SVP,
Since the CPU itself operates, problems may occur where accurate data cannot be transferred.

Therefore, the main purpose of the present invention is to eliminate the above-mentioned drawbacks in conventional devices, and for this purpose, the present invention provides a maintenance processing unit (hereinafter abbreviated as MAU) between the CPU and SVP.
The MAU is equipped with a rewritable control storage device that stores microprograms for executing various service requests, and is capable of decoding control signals and sending and receiving data in response to various service requests from the SVP and CPU. The service request is processed only by the above microprogram in the MAU, so it does not interfere with the original operation of the CPU, and even if the CPU is not operated or the CPU does not operate due to a failure etc. The present invention provides a data processing device capable of processing.

Another object of this invention is to configure the control storage device in the MAU with a rewritable storage element, and when performing microdiagnosis or maintenance work,
From the CPU, the desired program is written to a storage device that can be rewritten as needed, and the contents of this storage device are changed to a microprogram that meets the requirements, without adding or changing hardware. To provide a data processing device that can perform detailed diagnosis and maintenance, and can flexibly deal with additions and changes to service requests.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of this invention, where 1 is an MMU, 2 is a CPU, and 3 is an SVP.
includes a CRT display 4 and a keyboard 5. 6 is an MAU, and the MAU 6 and the CPU 2 and the MAU 6 and the SVP 3 are connected by a data bus and a control signal line. The data bus and control signal lines will be explained with reference to FIG. 2 in a later section. Also
The MAU6 and MMU1 may be connected by a data bus and a control signal line.

FIG. 2 is a block diagram showing an example of the internal connection of the MAU 6 shown in FIG. 1. In the figure, 11 is a command register (hereinafter abbreviated as MCMR), and 12 is a control memory write data register (hereinafter abbreviated as MCWR). , 13 is a CPU output data register (hereinafter abbreviated as CPDR), 14 is an SVP output data register (hereinafter abbreviated as SVDR), 15 is a CPU output data bus (hereinafter abbreviated as CPUO), and 16 is a CPU output data register (hereinafter abbreviated as CPUO).
SVP output data bus (hereinafter abbreviated as SVPO),
17 is an SVP input data bus (hereinafter abbreviated as SVPI), and 18 is a CPU input data bus (hereinafter abbreviated as CPUI). CPUO15 from CPU2 is
MCMR11, MCWR12, CPDR1 in MAU6
3 and SVPO16 from SVP3 is MCMR
11, connected to MCWR12 and SVDR14. Also, SVPI17 from MAU6 to SVP3 is CPDR1
Output from output terminal 3, MAU6 to CPU2
The CPUI 18 that reaches this point is output from the output terminal of the SVDR 14.

19 is a rewritable control storage device (hereinafter referred to as
(abbreviated as MWCS) stores microprograms for executing various service requests. 2
0 is a control storage read register (hereinafter abbreviated as MCDR) from which the contents of MWCS19 are read; 2
Reference numeral 1 denotes a microprogram address register (hereinafter abbreviated as MADR) that provides the address of a microprogram within the MCWS 19.

During normal operation, various service requests mutually generated from the CPU 2 and SVP 3 are transferred to the CPUO 15 and SVPO 16 as commands to the MAU 6, respectively. When CPU 2 issues a service request, a CPU service request signal (hereinafter referred to as
When the SVP 3 issues a service request, the control signal line 23 outputs an SVP service request signal (hereinafter abbreviated as SVRQ).
The data on CPUO15 is set to MCMR11 by CPRQ on signal line 22, and the data on SVPO16 is set to MCMR11 by SVRQ on signal line 23.
Set to 1.

24 is an instruction decoder (hereinafter abbreviated as ISDR)
The instruction set in MCMR11 is decoded, and the start address of the microprogram to be read from MWCS19 to process the decoded instruction is set in MADR21, and subsequent instructions are executed under the control of the microprogram. be exposed. Sequential control using a microprogram is generally well known, and the MAU 6 also performs control using the known sequential control, so a detailed explanation thereof will be omitted.

MAU6 reads the microinstructions sequentially read from the address set in MADR21 to MCDR.
Set to 20. 25 is a microinstruction decoder (hereinafter abbreviated as MIDR) which decodes the microinstruction set in MCDR 20. Of the output signal groups of MIDR25, 26 are MAU control signal groups (hereinafter referred to as
27 indicates a CPU control signal group (hereinafter abbreviated as CCNT), 28 indicates an SVP control signal group (hereinafter abbreviated as SCNT), and MCNT2
6 controls the circuit inside MAU 6, CCNT 27 is sent to CPU 2 through independent control signal lines,
SCNT28 is SVP3 with each independent control signal line.
sent to.

Next, the operation of the circuit shown in FIG. 2 will be explained using an example in which the SVP 3 issues a service request involving data transfer.

SVP3 is a CPU internal register read instruction.
SVRQ is sent on the SVPO 16 via the signal line 23. Instructions on SVPO16 are sent to MCMR by SVRQ.
It is set to 11. The instruction set in MCMR 11 is decoded by ISDR 24, the first address to be read from MWCS 19 is set in MADR 21, and execution of the microprogram is started. When the first instruction input to MCDR20 in this microprogram is decoded by MIDR25, SCNT28
SVP data transmission request signal on signal line 29
(abbreviated as STRQ) becomes significant. The signal line 29
When connected to SVP3 and STRQ becomes significant
SVP3 learns that MAU6 requests the address of the internal register to be read from CPU1, and puts this requested address on SVPO16.
SVP data ready signal (hereinafter abbreviated as SVDQ)
is sent back via the control signal line 30. 31 is a data ready signal waiting circuit (hereinafter abbreviated as DINT);
Interlocks data transfer between MAU6, SVP3 and CPU2. That is, through the signal line 30
When SVD _Q is input to DINT31, the output of DINT31 becomes significant and MADR21 advances the address by 1 and the next microinstruction is transferred from MWCS19 to MCDR.
20 and decoded by MIDR25.

In the next microinstruction mentioned above, the SVP output data register set signal (hereinafter referred to as SVDS) on the control signal line 32 of the MCNT 26 is made significant and the SVDS is activated.
When added to SVDR14, the data being sent to SVPO16 at that time, that is, the CPU2 internal register address, is set in SVDR14, and this
The address set in SVDR14 is CPUI18
is sent to CPU2, and then CCNT
27, the CPU data reception request signal (hereinafter abbreviated as CRRQ) on the control signal line 33 is made significant. CRRQ transmitted on signal line 33 in CPU2
The data on CPUI18, i.e. CPU2
Input the internal register address and temporarily store it.

Next, the read microprogram is processed by the CPU data transmission request signal (hereinafter referred to as
(abbreviated as CTRQ) is made significant and sent to CPU2. When CPU2 receives CTRQ on signal line 34, CPU2 is specified by the address on CPUI18.
The contents of the internal register are loaded onto the CPUO 15, and a CPU data ready signal (hereinafter abbreviated as CPDQ) is similarly sent to the MAU 6 via the control signal line 35.

When the CPDQ on the signal line 35 is input to the DINT31, the microprogram advances one address further, makes the CPU output data register set signal (hereinafter abbreviated as CPDS) on the control signal line 36 valid, and stores the data on the CPUO15 at that time. In other words, the contents of the CPU2 internal register are set to CPDR13, and this
The data set in CPDR13 is put on SVPI17 and sent to SVP3, and then the control signal 3
7 makes the SVP data reception request signal (hereinafter abbreviated as SRRQ) significant. In the SVP3, the data on the SVPI17 is inputted and stored through the SRRQ on the signal line 37, and a series of data transfers is completed.

When writing a microprogram in the MWCS 19, that is, when writing a special microprogram during initial setting or for the purpose of microdiagnosis, maintenance, etc., this write request is sent from the CPU 2 to the CPUO 15 or
It is output from SVP3 to SVPO16 and set in MCMR11. In the MAU6, this command set in the MCMR11 is decoded by the ISDR24 and transmitted to the CPU2 via the control signal line 38 as a CPU microprogram data request signal (hereinafter abbreviated as CIMP), or is transmitted as an SVP microprogram data request signal (hereinafter abbreviated as SIMP). (abbreviated) as the control signal line 3
9, it is transmitted to SVP3. Next, the MCWR set signal (hereinafter referred to as MCWS) is set by a certain time sequence.
) is output to the control signal line 40 and the MWCS
A write signal (hereinafter abbreviated as MWSS) is output to the control signal line 41, and the CPUO15 or SPVO16
Microprogram data transferred by
Write to MWCS19 via MCWR12.

MADR increment signal (hereafter MAUP)
) is sent to the control signal line 42 and MADR
By incrementing the contents of 21 by the numerical value 1 and repeating the above sequence, a new write is made to the MWCS 19 or a part of the contents of the MWCS 19 is rewritten.

As explained above, in this invention, by providing the MAU 6 with the rewritable MWCS 19, the decoding operation, data transfer processing, etc. are performed in response to various service requests mutually generated between the CPU 2 and the SVP 3. CPU2 can be made independent, and it can be executed without interfering with CPU2, and even if CPU2 fails and does not operate, it is possible to process service requests such as internal state observation. Ta.

In addition, by changing the microprogram stored in the MWCS 19 of MAU6 to correspond to the operating mode of CPU 2, detailed diagnosis and maintenance are possible, and the MWCS 19 is used more efficiently, creating a data processing device with improved maintainability. can be obtained.

In the embodiment shown in FIG. 2, the data bus and various control signal lines input and output to the MAU 6 are
The ones between MAU6 and CPU2 and between MAU6 and SVP3 are shown, but as shown in Figure 1, MAU6
A data bus and a control signal line may also be provided between the MAU 6 and the MMU 1 to exchange data between the MAU 6 and the MMU 1.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing an example of internal connections of the maintenance processing unit (MAU) shown in FIG. 1...Main memory unit (MMU), 2...Central processing unit (CPU), 3...Service processing unit (SVP), 6...Maintenance processing unit (MAU), 11...Command register (MCMR), 1
2...Control memory write data register (MCWR), 13...CPU output data register (CPDR), 14...SVP output data register (SVDR), 15...CPU output data bus (CPUO), 16...SVP Output data bus (SVPO), 17...SVP input data bus (SVPI), 18...CPU input data bus (CPUI), 19...Control storage device (MWCS), 2
0...MWCS read register (MCDR), 21...
...Micro program address register (MADR), 24...Instruction decoder (ISDR), 25
...Micro instruction decoder (MIDR).

Claims (1)

[Claims] 1. In a data processing device including a central processing unit, a main storage device, and a service processing device, a maintenance processing device connected to the central processing unit and the service processing device and having a rewritable control storage device, the central processing device or means for writing a microprogram for executing a predetermined service request from the service processing device to a specified address in the control storage device; 1. A data processing device comprising means for sequentially reading out a microprogram to execute instructions defined by the microprogram.