JPS62237537A - Fault detecting circuit - Google Patents

Abstract

PURPOSE:To detect the runaway of a CPU by ORing a pulse which rises at the trailing edge of the output pulse of a counter circuit in holding the fixed level for a period longer than the repeating period of said output pulse, with the output pulse of the counter circuit, to provide a circuit outputting a fault detecting pulse. CONSTITUTION:When the CPU 7 is runaway by disturbance, a monitoring pulse VC is expanded at its repeated period or stopped. Since the counter circuit 3 is not reset, the circuit 3 is reset by the just preceding pulse, and after the passage of a repeating period T2 of the circuit 3, the pulse VC is outputted and inputted to a program reset means 6. Consequently, the advancement of the program is reset, the operation is restored to the normal operation and the monitoring pulses VS are outputted again at a fixed repeating period T1. Although the pulses VC are inputted to a timer circuit and pulses VT are outputted from the timer circuit 4, no output is generated from the counter circuit 3 because the operation is restored to the normal operation, so that a fault detecting pulse VD is not outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a failure detection circuit, and more particularly to a failure detection circuit for a device incorporating a microcomputer or the like controlled by a program.

L Conventional Technology] Conventionally, this type of failure detection port Wl! As an example, as shown in FIG. 3, there is a monitoring pulse generating means 1 within the CPU 7 which divides the system clock pulse CKi and generates a monitoring pulse Vsk having a constant repetition period in accordance with the timing at which the program progresses. , supervisor a, input to the reset terminal via Hals Vat output port 2, and monitor pulse ■s
When CKf is not input, the system clock pulse CKf
A pulse V whose frequency is divided and whose repetition period is longer than that of the monitoring pulse V.

, and a program reset means 6 that resets the progress of the program using the output pulse vo of the counter circuit 3 and returns it to normal operation.

The monitoring pulse generating means 1 is normally incorporated into the program f'L, and during normal operation, the monitoring pulse (8) is output at a constant 11i1 period which is better than the repetition period of the output pulse (20) of the counter circuit 3. Therefore, the counter circuit 3 does not output the pulse Vo in order to repeat the reset 2, and therefore the program continues to progress.

On the other hand, program control is disturbed due to noise etc. fLcP
When IJ7 goes out of control, a, supervisor? Since the R pulse ■8 repetition cycle often becomes long or stops, the counter circuit 3 outputs a pulse ■0, and the program reset means 6Vc is configured to set the progress of the program by +3 and return to normal operation. .

[The blinding point that the invention attempts to solve]

In the conventional fault detection circuit described above, CI)
The IC is effective when the U temporarily runs away, but if there is a hardware failure such as an abnormality in the program memory, or a continuous strong disturbance occurs, these failures may occur. Is there a drawback that the microcomputer, etc. configured in the device continues to perform inappropriate operations because it cannot be detected? had.

SUMMARY OF THE INVENTION An object of the present invention is to provide a failure detection circuit that can detect a CPU runaway caused by a hardware failure or continuous strong disturbance, and can take measures to prevent improper operation of a microcomputer, etc. .

[Makoma point tw! + Ninth means to decide]

The failure detection circuit of the present invention includes a monitoring pulse generating means for generating a monitoring pulse having a constant repetition period t corresponding to the timing at which the program progresses, and a repetition period longer than the monitoring pulse when the monitoring pulse is not input. Motsu pulse? 1. Output and reset when the monitoring pulse is input. a fault detection circuit having a counter circuit, a program reset means that resets the progress of the program and returns to normal operation when the output pulse of the counter circuit goes low; A timer circuit that outputs a pulse that maintains a constant level for a long period of repetition period, a gate circuit that outputs logic output pulses of the counter circuit and the timer circuit, and nine failure detection pulses. .

〔Example〕

Next, what are the drawings about the embodiments of the present invention? Refer to and explain.

The first factor is a block diagram showing an embodiment of the present invention.

This embodiment differs from the conventional failure detection circuit shown in the third garden ((The output pulse 2 of the counter circuit 3 is different from the conventional failure detection circuit shown in FIG.

It rises at the rear end of O and stays at a constant level for how long, longer than the repetition period of O's output pulse? The timer circuit 4 that outputs the maintaining pulse Vtk, and the n pulses Vo and Vd output from the counter circuit 3 and the timer circuit 4 are ANDed, and these pulses V0. Failure detection pulse V is output when V is output at the same time.
This is the point where the gate circuit 5 which outputs ok and t are provided.

Next, the operation of this embodiment will be explained.

Figure 2 i (a1 to (cl) shows the implementation fllf
FIG. 3 is a waveform diagram of a signal when the je signal is activated.

First, the normal operation shown in the 113th (at) will be explained.

During normal operation, since the program is progressing normally, the monitoring pulse Vs output from the monitoring 7M pulse generation circuit 1
l”j: constant repetition period T1 via output port 2
is input to the reset terminal of the counter circuit 3. Since the repetition period of the output pulse ■o of the counter circuit 3 is set longer than the repetition period TIL of the monitoring pulse ■s, the counter circuit 3 outputs the pulse Vo' and always resets with the monitoring pulse vs before it is about to sleep. and the pulse Va k
Unable to output. Therefore, the program remains as is.
The output pulses VT and VD from the timer circuit 4 and gate circuit 5 are not output.

Next, a case will be described in which the program control is temporarily disturbed due to the disturbance shown in ) in FIG. 2, and the CPU 7 goes out of control.

In this case, the monitoring pulse Vat? Since the repetition cycle becomes longer or stops, the output should be Snowhals P
, stops. Therefore, since the counter circuit 3 is not reset, the pulse ``o'' is output after the repetition period T2 of the counter circuit 3 has elapsed after being reset by the previous pulse Pl. This pulse Vou is input to the program reset means 6, and the progress of the program is reset to return to normal operation, and the monitoring pulse 8 is again output at a constant repetition period T1. Also, when the pulse VOH timer circuit 4 is input, it outputs 17 pulses, but since it has already returned to normal operation, the counter circuit 4
There is no output pulse from VD, so the failure detection pulse VD is not output.

Next, the case of a hardware failure shown in FIG. 2 (C1) will be explained.

In this case, first, the pulse P2 that should be output as the monitoring pulse vs stops. Then, from counter circuit 3,
After the repetition period T2 has elapsed from the pulse P1, the pulse ■
o is output, but it is determined that there is a hardware failure CPU7H
Since the normal operation does not return and the monitoring pulse VstX stops and remains unchanged, the counter circuit 3 outputs a pulse V at a repetition period T2.

is output. -10,000, pulse V at the output of timer circuit 4
It rises at the rear end of the first pulse P3 of o, and the repetition period T2
J: Since it is set to maintain a constant level for a long period of time, will it remain at this level when the next pulse P4 is input? At the same time as the pulse P4 is held, the period during which the entire output of the timer circuit 4 lasts is set again at the rear end of the pulse P4, and the pulse VTk is outputted to continue holding this level. Therefore, the failure detection pulse VD is output from the gate circuit 5, and the next action can be taken.

[Effects of the Invention] As explained above, the present invention is based on the logical product of the output pulse of the counter circuit and the pulse that rises at the rear end of the output pulse of the counter circuit and maintains a constant level for a long period of time due to the repetition period of this output pulse. By providing a circuit that outputs a fault detection pulse for t, it is possible to detect runaway of CPtJ due to hardware failure or continuous disturbance, and it is possible to take measures to prevent improper operation of the microcomputer, etc. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
a) to (cl are waveform diagrams of signals when operating the embodiment t shown in FIG. 1, and FIG. 3 is a block diagram showing an example of a conventional failure detection circuit. 1... Monitoring pulse generation means, 2... Output port. 3... Counter circuit, 4... Timer circuit %50110.. Gate circuit, 6... Program reset. means,
7...CPU. zu 7 cape shi 4 map 3 map

Claims (1)

[Claims] a monitoring pulse generating means for generating a monitoring pulse having a constant repetition period in accordance with the timing at which the program progresses, and outputting a pulse having a repetition period longer than the monitoring pulse when the monitoring pulse is not input; A counter circuit that is reset when an input is received;
In a failure detection circuit having a program reset means that resets the progress of the program using the output pulse of the counter circuit and returns to normal operation, the output pulse rises at the rear end of the output pulse of the counter circuit and remains constant for a period longer than the repetition period of the output pulse. 1. A failure detection circuit comprising: a timer circuit that outputs a pulse that maintains a level; and a gate circuit that performs a logical product of the output pulses of the counter circuit and the timer circuit and outputs a failure detection pulse.