JPS62235649A - Information processor - Google Patents

Abstract

PURPOSE:To detect an error at the time when a fault has been generated in an error correcting circuit, by comparing the contents of a register which has stored each parity bit before and after correcting the error. CONSTITUTION:From a data signal line 1 and a check bit signal line 2, information to be inspected is inputted to an error correcting circuit 21, a parity bit to a data on the signal line 1 is generated on a signal line 9, and an error bit of a data which has been contained in the information to be inspected is inverted and sent out onto a signal line 8. Subsequently, the data on the signal lines 8, 9 are sent out to a data register 23, and the first parity register 24, respectively, the parity bit to the data on the signal line 9 is stored in the register 24, the parity bit to the data before correcting an error, which has been stored in the register 24 is stored in the second parity register 25, and the parity bits which have been stored in the registers 24, 25 are compared by a parity comparing circuit 27, by which an error is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device, and particularly to an information processing device including an error correction circuit.

(Prior Art) Conventionally, an error correction circuit is often added to an information processing device as one means for achieving high reliability. In particular, main storage devices generally employ error correction circuits such as 1-bit error correction and 2-bit error detection.

In an information processing device having such an error correction circuit, the access time is delayed by the delay time during which the error correction circuit operates. As a method for minimizing this access time delay, an information processing apparatus described in Japanese Patent Publication No. 53-39293 is known.

It is assumed that the above disclosure allows the error correction circuit to determine the presence or absence of an error. If there is no error, the synchronization signal for the information is generated at that point and set in the information register.

On the other hand, when there is an error, a synchronization signal is generated when the error correction of the information is completed, and the operation is performed so that all the information after error correction is set in the information register.

That is, by controlling the synchronization signal for setting all information in the information register to be delayed only when there is an error, the access time when there is no error is shortened.

In such an information processing device, an error cannot be detected even if incorrect information is transferred at a rate of failure of the error correction circuit. For example, this will be explained with reference to Japanese Patent Publication No. 53-39293. FIG. 3 is an explanatory diagram showing an example of such a conventional technique. In FIG. 3, 1.31 is a check circuit, 32 is a syndrome register, 33 is a detection circuit, 34 is a decoder, 35 is an inversion circuit, 36 is a timing selection circuit, and 37
is a timing generation circuit, and 38 is an information register.

In FIG. 3, when the information under test includes a 1-bit error, the detection circuit 33 operates normally and the error signal line 3
05 is 1! % Rio 9I - As shown, timing selection circuit 3
6 operates to output the synchronization signal T2y (and set it in the error-corrected information@i meeting information register 38. At this time,
If a failure occurs in the decoder 34 and the error bit designation signal is not output on the error bit designation signal line 3()4,
The inversion circuit 35 does not perform inversion (correction) of error bits.

(Problems to be Solved by the Invention) In the conventional information processing device described above, information containing a 1-bit error Lf- is set in the information register as if it were normal information, and furthermore, there is no means for checking the normality of this information. Since the money is not distributed evenly, there is a drawback that fraud is carried out based on information.

An object of the present invention is to enable the error correction circuit to detect errors.
A first parity register that stores parity bits after error correction (f) and a second parity register that stores parity bits before error correction are provided, and by comparing the contents of the first and second parity registers, It is an object of the present invention to provide an information processing device 11 configured to eliminate the drawbacks and to be able to detect error 1 even if a failure occurs in an error correction circuit.

(Means for Solving the Problems) The present invention includes a shift generator, a decoder, a detection circuit, a data correction circuit, a parity generation circuit, and a data register. The device includes a first parity register, a parity check circuit, a second parity register, a parity comparison circuit, and a timing generation circuit.

The syndrome generation circuit is for generating a syndrome by inputting information to be inspected consisting of data and check bits.

The decoder is for generating a data correction signal for correcting 9 bits from syndromes and a parity correction signal for correcting parity bits generated from data.

The detection circuit is used to completely check for errors in data in the information to be checked based on the syndrome.

The data correction circuit is for inverting seven error bits in response to a data correction signal.

The parity generation circuit is for inverting the parity bit using a parity correction signal.

The data register is for storing data from the data correction circuit.

The first parity register is the parity register from the parity generation circuit. It is for storing.

The parity check circuit is a companion that performs a parity check on the next information stored in the first parity register.

The second parity register is for storing the parity bits f from the first parity register.

The parity comparison circuit is for comparing the contents of the first and second parity registers.

The timing generation circuit includes a Zitter register and a first
and a data set signal for setting the second parity register, and a parity comparison timing signal to the parity comparison circuit in accordance with the error detection result signal of the detection circuit.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus having all error correction circuits according to the present invention.
1, timing generation circuit 22, and data register 23
．． , a first parity register 24 , a second parity register 25 , a parity check circuit 26 , and a parity comparison circuit 27 . Error correction circuit 21 is composed of a syndrome generation circuit 211, a decoder 212, a detection circuit 213, a data correction circuit 214, and a parity generation circuit 215.

When the information to be inspected is input from the data signal line 1 and the check bit signal line 2, the syndrome generation circuit 211 generates a syndrome on the entire syndrome signal Is3, and the parity generation circuit 215 generates a parity bit for the data on the data signal line 1. Generated on signal line 9. The syndrome error detection circuit 213 inspects the data on the signal line l of the information to be inspected for errors, and outputs an error detection result signal on the signal line 6. tfc.

The decoder 212 is connected to a signal line 5 for correcting the error bit when there is an error in the data included in the information to be inspected.
The data correction signal above and the error beep)? At the same time as the correction, the signal generated by the parity generation circuit 215 and the next signal line 9
A parity correction signal for correcting the upper parity bit is output onto signal line 4. When an error bit is pointed out by the data correction signal on the signal line 5, the data correction circuit 214 sends the data on the signal line 8, in which seven error bits are inverted, to the data register 23, and when no error bit is pointed out, the data is Send.

When a parity inversion instruction is issued by the parity correction signal on signal line 4, parity generation circuit 215 inverts the parity bits on signal line 9 to the already generated parity bits for the data on signal line 1. The data is sent to the first parity register 24, and when there is no inversion instruction, the data (
The parity bit for signal 49 (on line 1) is output as is. The timing generation circuit 22 is controlled by the state of the error detection result signal sent from the detection circuit 213 to the signal line 6, and outputs a data set signal on the signal line 10 and a parity comparison timing signal on the signal line 11. The data set signal on the signal line 10 is sent to the data register 23.
, and first and second parity registers 24.2
This is a timing signal for setting 5"4e. When the error detection result signal on signal line 6 does not detect an error ff?L-, the data on signal line 1 is stored as is in data register 23, and the parity for the data is The bit (on signal line 9) is stored in the first parity register 24. On the other hand, when an error is detected, the data before error correction (on signal line 1) and the parity bit (on signal line 9) are stored.
is stored in the data register 23 and the first parity register 24. Next, when error correction is completed in the data correction circuit 214 and the parity generation circuit 215,
Output the second data set signal onto the signal line lO,
The corrected data on signal line 8 is stored in the data register 23, the parity bit (on signal line 9) for the corrected data on signal line 8 is stored in the first parity register 24, and the parity bit (on signal line 9) is stored in the first parity register 24. The parity pick for the data before error correction is stored in the second parity register 25.

The parity comparison timing signal on the signal line 11 is a timing signal indicating a valid condition when comparing the parity bits stored in the first parity register 24 and the second parity register 25, and is a timing signal on the signal line 6. An error detection result signal is output when an error is detected. The parity check circuit 26 performs a parity check on the information stored in the data register 23 and the first parity register 24. Figure 2 shows the data to be inspected (signal line 1
This is a time chart showing the operation when the above) contains an error, and it shows the time chart showing the operation when each circuit performs the above-mentioned operation normally.

Next, the operation when a failure occurs in the error correction circuit will be explained. For example, when the data of the information to be inspected (on signal line 1) contains a 1-bit error t-, the decoder 21
2 and the data correction signal on the signal line 5 and the harrity correction signal on the signal line 4 are not output, the uncorrected data containing a 1-bit error and its parity bit are transferred to the data register 23 and the 1 parity register 24. At this time, since the detection circuit 213 performs all error correction, the timing generation circuit 22 outputs the second data set signal onto the signal line IO, and outputs the corrected data and its parity bits to the first data register 23 and the first data set signal. An attempt is made to store it in the parity register 24. However, if the error is not corrected, it is stored at the end, and the uncorrected data and its parity bit are stored in the register. Therefore, the same parity bit is stored in the first parity register 24 and the second parity register 25, and the parity comparison circuit 27 detects a parity comparison error.

This is because if the error correction circuit 21 operates normally when the data on the signal line 1 contains a 1-bit error,
The parity bit before correction and the parity bit after correction are always inverted.

That is, the corrected parity bit stored in the first parity register 24 and the second parity register 25
It should not match the parity bit before correction stored in .

Considering yet another failure example, if the detection circuit 213 erroneously detects an error when the information under test does not include an error t-, the timing generation circuit 213
The data set signal is outputted twice from , but the same data and parity bit are stored in the data register 23 and the parity register 24 of i@1 both times.

Therefore, since the first and second pads are stored in this case as well, it is possible to detect a parity comparison error.

(Effects of the Invention) As described above, the present invention provides a first parity register that stores parity bits after error correction after the error correction circuit detects an error, and a first parity register that stores parity bits before error correction. ll- a second parity register for storing;
By comparing the contents of the first and second parity registers, even if a fault occurs in the error correction circuit, the fault Wt
- It has the effect of being able to be detected.

As a result, it is possible to prevent erroneous data from being transferred as if it were normal data. Just in case, the gold v to realize this effect! J
As is clear from the above explanation, the amount of addition required is very small due to the use of parity bits, and the information processing apparatus is inexpensive and highly reliable. There is an effect that can be provided.

FIG. 1 is a block diagram of an information processing apparatus with an error correction circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the tenth information processing device.

FIG. 3 is a block diagram of an information processing device equipped with an error correction circuit according to the prior art.

21...Error correction circuit 22.37...Timing generation circuit 23...Data register 24.25...Parity register 26...Parity check circuit 27...Parity ratio IIR circuit 211...Syndrome generation circuit 212.34...decoder 213.33...Detection circuit 214...Data correction circuit 215...Parity generation circuit 31...Check circuit 32...Syndrome register 35... Inversion circuit 36...timing selection circuit 38...Information register

Claims (1)

[Claims] A syndrome generation circuit for generating a syndrome by inputting information to be inspected consisting of data and check bits, a data correction signal for correcting error bits from the syndrome, and a parity correction signal for correcting parity bits generated from the data. a decoder for generating a signal, a detection circuit for checking the presence or absence of an error regarding the data in the information to be checked based on the syndrome, and data for inverting error bits by the data correction signal. a correction circuit, a parity generation circuit for inverting a parity bit by the parity correction signal, a data register for storing data from the data correction circuit, and a parity generation circuit for inverting the parity bit from the parity generation circuit. a first parity register for storing information, a parity check circuit for performing a parity check on information stored in the first parity register, and a parity check circuit for performing a parity check on information stored in the first parity register; a second parity register for storing bits; and a second parity register for storing bits;
and a parity comparison circuit for comparing the contents of a second parity register, a data set signal for setting the data register and the first and second parity registers, and a parity comparison timing for the parity comparison circuit. An information processing apparatus comprising: a timing generation circuit for outputting a signal according to an error detection result signal of the detection circuit.