JPS62234446A - Data reception - Google Patents

Abstract

PURPOSE:To obtain a data speed at a high speed in simple constitution by sampling fast the data where a data pattern is known and the data speed is unknown after detecting the speed of the input start-stop synchronizing serial data and deciding the data speed from the obtained data pattern. CONSTITUTION:When the input data speed is unknown,and the input data pattern is known, a timing control part 4 is first set through a control register 6 in response to the expected maximum data speed. Then the start-stop synchronizing serial data is read in a normal procedure. Here a data comparing part 8 compares the data obtained by a data latch circuit 3 with a pattern registered in a standard pattern memory part 9. When the input data speed is coincident with the data speed set presently, the data speed can be fixed. If the input data speed is lower than the set data speed, the part 8 searches for a pattern of another data speed out of the part 9. Then the desired data speed is known when a coincident pattern is obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention is used to adjust the speed of data transmission and reception.

In particular, the present invention relates to a method for detecting the data rate of asynchronous serial data.

〔overview〕

The present invention employs a data reception method that detects and receives the data rate of input asynchronous serial data, in which data with a known data pattern and unknown rate is sampled at high speed, and the data rate is determined from the obtained pattern. By doing so, high data speeds can be obtained with a simple configuration.

[Conventional technology]

FIG. 5 is a block diagram of a main part of a conventional data rate detection circuit.

In conventional data rate detection circuits, asynchronous serial data is sampled using a clock that is sufficiently faster than the data rate (3 times faster than the data rate), held in a latch circuit, and read out the output of this latch circuit. The waveform of the input data was known and the data rate was detected from this.

[Problem that the invention seeks to solve]

For this reason, the conventional data receiving circuit has the disadvantage that a data rate detection circuit is required in addition to a circuit for converting asynchronous serial data into parallel data.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a data reception method that can detect data speed with a simple circuit configuration.

[Means for solving problems]

The data reception method of the present invention includes a latch circuit that samples and holds input asynchronous serial data, a shift register that takes in the output of this launch circuit and converts it into parallel data, and operations of the latch circuit and the shift register. In a data receiving system comprising a timing means for setting a speed and a data speed detecting means for detecting a data speed of the asynchronous serial data and controlling the timing means, the latch circuit and the shift register are configured to provide the maximum expected speed. The data rate detecting means detects a pattern corresponding to a known data pattern input for data rate determination from among the data patterns accumulated in the shift register. The present invention is characterized in that it includes means for detecting the data speed of the start-stop serial data by comparing it with a standard pattern registered in advance corresponding to the data speed.

[For production]

The data reception scheme of the present invention uses a known input data pattern to detect data rate.

Sampling this human data pattern at a rate greater than or equal to the highest expected data rate will result in different output data patterns depending on the data rate.

Therefore, the data rate can be known by storing the correspondence between the data rate and the output data pattern in advance and comparing it with this.

〔Example〕

FIG. 1 is a block diagram of a data receiving circuit according to the present invention.

The latch circuit 1 is connected to a data transmission circuit via a transmission line, and asynchronous serial data is input from this data transmission circuit. The output of the latch circuit 1 is connected to a shift register 2 and a timing control section 4. Shift register 2 is connected to data latch circuit 3. Data latch circuit 3 is connected to data comparator 8 via data bus 7 . Data comparator 8 is connected to control register 6 via data bus 7 . The data comparison section 8 is further connected to a standard pattern storage section 9. The control register 6 is connected to the timing control section 4 and the clock generation section 5. The clock generator 5 is connected to the timing controller 4. The timing control section 4 is connected to the latch circuit 1 and the shift register 2.

The latch circuit 1 samples input data using a clock from the timing control section 4 and holds the data. When the timing control section 4 monitors the output of the latch circuit 1 and detects a start bit, it controls the shift register 2 so that the output of the latch circuit 1 is taken into the shift register 2 at predetermined time intervals. When a predetermined number of data has been loaded into the shift register 2, the timing control unit 4 sends the data in the shift register 2 to the data latch circuit 3 for output. The data taken into the data latch circuit 3 is sent to the data comparator 8 via the data bus 7. The control register 6 is connected to the data comparison section 8 through a data bus, and can control the timing control section 4 and the clock generation section 5 based on the output of the data comparison section 8. Further, when the shift register 2 takes in a predetermined number of data and sends this data to the data latch circuit 3, the information is notified to the data comparator 8 through the control register 6. In the standard pattern storage unit 9, output data patterns corresponding to all expected data speeds are registered when a certain known data pattern is inputted at the highest data speed expected in advance. . The data comparison section 8 compares the data output to the data latch circuit 3 with the registered pattern, and searches for a matching registered pattern.

FIG. 2 shows an example of a pattern of asynchronous serial data.

The horizontal direction is the time axis, and time increases from left to right. The start bit has a “0” polarity, and b
There are 8 data from 0 to b, and the stop bit is "1".
” shall have polarity. b0 to b7 are each rOJ
Or has "1" polarity.

If the input data rate is known, the input data is correctly converted into parallel data and supplied to the data latch circuit 3 by the above-described procedure. First, when the timing control unit 4 detects a start bit, data b is detected at the sampling point indicated by the upward arrow in FIG. -b7 is taken into shift register 2. Here, the timing control unit 4 sends the contents of the shift register 2, ie, b0 to b7, to the data launch circuit 3.

As a result, the input serial data b0 to b.

is obtained as the output of the day latch circuit 3.

On the other hand, if the data rate is unknown, the input data pattern (data b.-b in FIG. 2).

If the data rate (pattern) is known, the data rate can be detected by the following procedure.

First, the timing control section 4 is set through the control register 6 in accordance with the expected highest data rate, and the asynchronous serial data is read in using the normal procedure described above. At this time, the data comparison section 8 compares the data obtained by the data latch circuit 3 with each pattern registered in the standard pattern storage section 9.

If the human data rate matches the currently set data rate, the known data pattern will directly match the output data, and the data rate will be determined based on this. Also, if the input data rate is lower than the currently set data rate, the output data will not match the known pattern. The data comparison section 8 searches for patterns of other data speeds registered in the standard pattern storage section 9, and if a matching pattern is found, it knows that the data speed is that one.

3 and 4 show examples of data, with reference to which the above-described data rate detection procedure will be explained.

These figures show rioiil 01 with different data rates.
The data pattern of 0J is shown. Assuming that the known data patterns to be input are 8 pieces of rlolloloJ, and the data rate is 1/2 of the set value, the data latch circuit 3 has 8 pieces of rlolloloJ as shown on the left side of FIG.
Eight pieces of data of lllJ are obtained. The data comparison unit 8 searches for a pattern matching this pattern among the patterns registered in the standard pattern storage unit 9, and the second registered pattern of the registered data rate of the pattern is outputted as the second registered pattern. 8th data (r on the right side of Figure 3)
olloollJ) and notifies the detected data rate to the outside. Furthermore, if the data rate is four times the set value as shown in FIG. 4, the first eight pieces of data will be rooolloJ, the second will be [01111111J, and some more data will follow. However, in Fig. 4, the known pattern [101110
Only the first part of 10J is shown. The data comparison unit 8 compares all these patterns with the registered patterns and notifies the outside of the data rate that has failed.

The unknown data rate can be detected in the above manner. Once the data rate is determined, subsequent data can be received normally by resetting the timing control section 4 in accordance with the detected data rate.

〔Effect of the invention〕

As described above, the data reception method of the present invention can detect an unknown data rate without separately preparing a data rate detection circuit, and can convert subsequent data into parallel data.

The present invention has great effects when used for data transfer between data processing devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data receiving circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of asynchronous serial data. FIG. 3 is a diagram showing an operation example of data rate detection. FIG. 4 is a diagram showing an operation example of data rate detection. FIG. 5 is a block diagram of a main part of a conventional data rate detection circuit. 1...Latch circuit, 2...Shift register, 3...
・Data latch circuit, 4...timing control section, 5.
...Clock generator, 6...Control register, 7...
Data bus, 8... Data comparison section, 9... Standard pattern storage section.

Claims (1)

[Claims] (1) A latch circuit that samples and holds the input asynchronous serial data, a shift register that captures the output of this latch circuit and converts it into parallel data, and a timing for setting the operating speed of the latch circuit and shift register. and data rate detection means for detecting the data rate of the asynchronous serial data to control the timing means, wherein the latch circuit and the shift register are arranged to detect a data rate of the asynchronous serial data and control the timing means. The data rate detecting means detects a pattern corresponding to a known data pattern inputted for data rate determination from among the data patterns accumulated in the shift register to correspond to the data rate. A data receiving system comprising means for detecting a data speed of the start-stop serial data by comparing it with a standard pattern registered in advance.