JPS62232143A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62232143A JPS62232143A JP7498186A JP7498186A JPS62232143A JP S62232143 A JPS62232143 A JP S62232143A JP 7498186 A JP7498186 A JP 7498186A JP 7498186 A JP7498186 A JP 7498186A JP S62232143 A JPS62232143 A JP S62232143A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- substrate
- oxide film
- oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 230000003647 oxidation Effects 0.000 claims abstract description 26
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000001020 plasma etching Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 8
- 239000013078 crystal Substances 0.000 abstract description 8
- 230000007547 defect Effects 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910005091 Si3N Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の目的]
(産業上の利用分野)
本発明は、半導体11の製造方法に係り、特に高密度集
積回路の素子領域の寸法誤差を小さくするフィールド領
域の形成方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor 11, and in particular, a method of forming a field region that reduces dimensional errors in an element region of a high-density integrated circuit. Regarding.
(従来の技術)
従来の半導体装置、特にMO8型集積回路装置では、素
子間の分離領域(フィールド酸化膜)に厚い絶縁膜を形
成する方法として一般に選択酸化法<LOCO8法)が
用いられている。この方法では、基板の素子領域に耐酸
化性マスクとして例えばシリコン窒化Ml (S i3
N4 II)を形成し、フィールド領域に反転防止用の
イオン注入を行なった後、酸化性雰囲気中で高温、長時
間の熱酸化を行なうことにより厚いフィールド酸化膜を
形成する。しかしこの方法では、フィールド酸化膜を形
成する際、酸化が横方向にも進行するために、Si3N
+111の端部から厚いフィールド酸化膜が鳥のくちば
し状に食込む現象が見られる。このため素子形成領域の
寸法誤差が生じ、特に高密度集積回路では高集積化の妨
げとなり、微IO素子の特性劣化の原因ともなる。(Prior Art) In conventional semiconductor devices, especially MO8 type integrated circuit devices, a selective oxidation method (<LOCO8 method) is generally used as a method for forming a thick insulating film in an isolation region (field oxide film) between elements. . In this method, silicon nitride Ml (S i3
After forming N4 II) and implanting ions into the field region to prevent inversion, a thick field oxide film is formed by performing thermal oxidation at high temperature and for a long time in an oxidizing atmosphere. However, in this method, when forming the field oxide film, oxidation also progresses in the lateral direction, so the Si3N
A phenomenon in which the thick field oxide film digs into the edge of +111 in the shape of a bird's beak can be seen. This causes a dimensional error in the element formation region, which hinders high integration, especially in high-density integrated circuits, and causes deterioration of characteristics of micro IO elements.
この様な問題を解決するフィールド酸化膜形成方法とし
て、第2図(a)〜(d)に示す方法が提案されている
。先ず(a)に示すように、シリコン基板21に5i0
2膜22を介してSi3N4膜23をjfi積形酸形成
これをパターン形成して耐酸化性マスクを構成する。そ
して、SiO2膜22とS i3N41123をマスク
として例えば、反応性イオンエツチング法(RIE法)
により2000人程度基板21を選択的にエツチングし
て、満24を形成する。この後基板全面にCVD注によ
り厚さ700APi!度の多結晶シリコン摸25を堆積
する。次に異方性エツチング法として例えばRIE法を
用いて多結晶シリコン膜25を全面エツチングし、(b
)に示すようにSi3N+ffQ23の側壁部にのみ多
結晶シリコン膜25を残置させる。そしてボロンをイオ
ン注入して反転防止居26を形成する。この後桟された
多結晶シリコン膜25および基板21を同時に、例えば
水蒸気を含む雰囲気中でi ooo℃、4時間の熱酸化
を行い、(C)に示すように8000人程度0厚いフィ
ールド酸化1127を形成する。As a method for forming a field oxide film to solve such problems, the method shown in FIGS. 2(a) to 2(d) has been proposed. First, as shown in (a), 5i0 is applied to the silicon substrate 21.
The Si3N4 film 23 is formed with a jfi oxide film through the two films 22 and patterned to form an oxidation-resistant mask. Then, using the SiO2 film 22 and Si3N41123 as a mask, for example, a reactive ion etching method (RIE method) is performed.
The substrate 21 is selectively etched by about 2,000 people to form a wafer 24. After this, the entire surface of the board was coated with CVD to a thickness of 700 APi! A layer of polycrystalline silicon 25 is deposited. Next, the entire surface of the polycrystalline silicon film 25 is etched using, for example, the RIE method as an anisotropic etching method (b
), the polycrystalline silicon film 25 is left only on the sidewalls of the Si3N+ffQ23. Then, boron ions are implanted to form the anti-inversion groove 26. After this, the deposited polycrystalline silicon film 25 and substrate 21 are simultaneously thermally oxidized at 100°C for 4 hours in an atmosphere containing water vapor, and as shown in FIG. form.
そして(d)に示すように素子形成領域のS ix N
4 WA23および酸化!122を除去して基板表面を
露出させる。Then, as shown in (d), S ix N in the element formation region
4 WA23 and oxidation! 122 is removed to expose the substrate surface.
この方法によれば、フィールド酸化膜形成時にマスク側
壁に多結晶シリコン膜があり、これが同時に酸化される
ため、マスク下へのフィールド酸化膜の食い込みは効果
的に防止される。According to this method, there is a polycrystalline silicon film on the side wall of the mask when the field oxide film is formed, and this is oxidized at the same time, so that encroachment of the field oxide film under the mask is effectively prevented.
しかしながらこの方法では、フィールドfRRに予め満
24を形成しているために、高温、長時間の熱酸化の工
程で溝24のコーナ一部に大きいストレスがかかる。こ
の結果、第2図(d>に示したようにフィールドm域周
辺から素子形成領域の基板内に結晶欠陥28が入り、こ
れが素子特性を損う。またフィールド領域に1124を
形成した後、基板面が露出したままこの上に多結晶シリ
コン瑛25を堆積し、これを(b)に示すようにS i
3N411!23の側壁に残してエツチング除去してい
る。このため基板21表面がRIEのエツチング雰囲気
に晒され、イオンによるダメージや汚染を生じる。これ
らも後の高温工程で基板の結晶欠陥の原因となり、素子
の信頼性1歩留り低下の原因となる。However, in this method, since the field fRR is formed in advance, a large stress is applied to a part of the corner of the groove 24 during the high-temperature, long-time thermal oxidation process. As a result, as shown in FIG. 2 (d), crystal defects 28 enter the substrate in the element formation region from around the field m region, which impairs the device characteristics. A polycrystalline silicon layer 25 is deposited on this surface with its surface exposed, and as shown in FIG.
It is etched away leaving it on the side wall of 3N411!23. Therefore, the surface of the substrate 21 is exposed to the RIE etching atmosphere, causing damage and contamination by ions. These also cause crystal defects in the substrate in a subsequent high-temperature process, resulting in a decrease in device reliability and yield.
(発明が解決しようとする問題点)
以上のように従来のフィールド酸化膜形成方法では、フ
ィールドWA城端部から素子領域内に結晶欠陥が発生し
、特に微細素子を高密度に集積した場合に素子特性を劣
化させる、という問題があった。(Problems to be Solved by the Invention) As described above, in the conventional field oxide film forming method, crystal defects occur in the element region from the edge of the field WA, especially when fine elements are integrated at high density. There was a problem that the characteristics deteriorated.
本発明は、上記のような問題を解決した半導体INの製
造方法を提供することを目的とする。An object of the present invention is to provide a method for manufacturing a semiconductor IN that solves the above problems.
[発明の構成]
(問題点を解決するための手段)
本発明の方法は、素子形成領域に耐酸化性マスクを形成
した半導体基板全面に多結晶シリコン模を堆積して、こ
の多結晶シリコン膜を異方性エツチングによりエツチン
グして耐酸化性マスク側壁に残置させる。ここで本発明
の方法が従来と異なる点は、第1に、耐酸化膜で囲まれ
たフィールド領域の基板表面にストレスの原因となる溝
形成を行なわないこと、第2に、多結晶シリコン膜エツ
チングの工程で基板表面を露出させないように熱酸化膜
が形成された状態で多結晶シリコン躾堆積を行なうこと
である。この後従来と同様に多結晶シリコン躾と同時に
基板表面を熱酸化してフィールド酸化膜を形成する。[Structure of the Invention] (Means for Solving the Problems) The method of the present invention involves depositing a polycrystalline silicon pattern over the entire surface of a semiconductor substrate with an oxidation-resistant mask formed in the element formation region, and depositing this polycrystalline silicon film. is etched by anisotropic etching and left on the oxidation-resistant mask sidewall. Here, the method of the present invention differs from the conventional method in that, firstly, no grooves are formed on the substrate surface in the field region surrounded by the oxidation-resistant film, which causes stress, and secondly, the method is different from the conventional method in that Polycrystalline silicon is deposited with a thermally oxidized film formed so that the surface of the substrate is not exposed during the etching process. Thereafter, as in the conventional method, a field oxide film is formed by thermally oxidizing the substrate surface at the same time as polycrystalline silicon oxidation.
(作用)
本発明の方法によれば、フィールド領域に溝形成を行な
わないから、高温、長時間の熱工程での結晶欠陥の発生
が抑制される。また多結晶シリコン膜の下地に熱酸化膜
を介在させているために、この多結晶シリコン膜をRI
E法でエツチングした時に基板表面がRIE雰囲気に晒
されることがなく、イオンダメージや汚染が防止される
。これによっても結晶欠陥の発生が抑制される。従って
本発明によれば、素子特性を劣化させることなく微細素
子の^密度集積化が可能になる。(Function) According to the method of the present invention, since grooves are not formed in the field region, the generation of crystal defects during a high-temperature, long-time thermal process is suppressed. Furthermore, since a thermal oxide film is interposed under the polycrystalline silicon film, this polycrystalline silicon film can be
When etching is performed using the E method, the substrate surface is not exposed to the RIE atmosphere, and ion damage and contamination are prevented. This also suppresses the occurrence of crystal defects. Therefore, according to the present invention, it is possible to integrate fine elements at a high density without deteriorating the element characteristics.
(実施例) 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.
第1図(a)〜(f)は一実施例のフィールド酸化膜形
成の工程を示す。<a)に示すように、面方位(100
)、比抵抗5〜50Ω・1のp型シリコン基板11に熱
酸化[112を介して、耐酸化性マスクとなるCVDに
よる5iiN+1113をiffff酸形成。熱酸化1
112は例えば600人、Si3N<[!113は例え
ば1000人程基板する。FIGS. 1(a) to 1(f) show the process of forming a field oxide film in one embodiment. As shown in <a), the surface orientation (100
), 5iiN+1113 is formed by CVD as an oxidation-resistant mask through thermal oxidation [112] on a p-type silicon substrate 11 with a specific resistance of 5 to 50 Ω·1. thermal oxidation 1
For example, 112 is 600 people, Si3N<[! 113 has a board of about 1,000 people, for example.
この後通常の写真蝕刻法により、(b)に示すようにフ
ィールド領域上の51gN41113を例えばRIE法
により選択的にエツチング除去する。Thereafter, as shown in (b), the 51 g N41113 on the field area is selectively etched away using a conventional photolithography method, for example, by RIE.
そして(C)に示すように基板全面にCVD法により約
700人の多結晶シリコン膜14を堆積形成する。この
ときフィールド領域の多結晶シリコン膜14と基板11
の間には必ず、熱酸化Wj112が存在するようにする
。もし、(b)のSi3N+IIlエツチングの工程で
同時に熱酸化膜12がエツチング除去されるか、または
これが薄くなる場合には再度熱酸化を行なって少なくと
ち400人程基板熱酸化膜が存在するようにする。Then, as shown in (C), about 700 polycrystalline silicon films 14 are deposited over the entire surface of the substrate by the CVD method. At this time, the polycrystalline silicon film 14 in the field region and the substrate 11
Thermal oxidation Wj112 is ensured to exist between the two. If the thermal oxide film 12 is etched away at the same time in the Si3N+IIl etching step of (b), or if it becomes thin, thermal oxidation is performed again so that at least 400 substrate thermal oxide films are present. Make it.
次に異方性エツチング法、例えばRIE法によって多結
晶シリコン躾14を全面エツチングし、(d)に示すよ
うにSi3N4膜13の側壁部にのみこれを残置させる
。このとき基板表面は熱酸化膜12で覆われているので
、多結晶シリコン膜エツチングで基板表面がダメージを
受けたり、汚染されることはない。次いでボロンのイオ
ン注入を行なって、反転防止用のp+型層15を形成す
る。この後水蒸気を含む酸化性雰囲気中で多結晶シリコ
ンl114および基板11の酸化を行い、(e)に示す
ように厚いフィールド酸化膜16を形成する。そして(
f)に示すように、素子形成領域の5i3N41111
3および熱酸化1112をエツチング除去して基板11
表面を露出させる。以下周知の工程に従って例えばMO
Sトランジスタ等の素子形成を行なう。Next, the entire surface of the polycrystalline silicon layer 14 is etched by an anisotropic etching method, for example, the RIE method, so that it remains only on the side walls of the Si3N4 film 13, as shown in FIG. At this time, since the substrate surface is covered with the thermal oxide film 12, the substrate surface will not be damaged or contaminated by polycrystalline silicon film etching. Next, boron ions are implanted to form a p+ type layer 15 for preventing inversion. Thereafter, the polycrystalline silicon 114 and the substrate 11 are oxidized in an oxidizing atmosphere containing water vapor to form a thick field oxide film 16 as shown in FIG. and(
As shown in f), 5i3N41111 in the element formation region
3 and thermal oxidation 1112 are removed by etching to remove the substrate 11.
expose the surface. Following the well-known process, for example, MO
Elements such as S transistors are formed.
この実施例によれば、従来のようにフィールド領域に溝
形成を行なわないから、後の熱工程で溝のコーナ一部の
ストレスに起因する結晶欠陥の発生が防止される。また
多結晶シリコン膜エツチングの工程で基板表面がイオン
ダメージを受けたり、汚染されることもない。従って素
子特性の劣化が効果的に防止されることになる。また、
マスク側壁に多結晶シリコン膜を残してフィールド酸化
を行なっており、多結晶シリコン躾は単結晶シリコンよ
り酸化速度が速いため、比較的短時間の熱工程で厚いフ
ィールド酸化膜を得ることができる。According to this embodiment, unlike the conventional method, a groove is not formed in the field region, so that crystal defects due to stress at a part of the corner of the groove are prevented from occurring in a later thermal process. Further, the substrate surface is not damaged by ions or contaminated during the polycrystalline silicon film etching process. Therefore, deterioration of device characteristics can be effectively prevented. Also,
Field oxidation is performed while leaving a polycrystalline silicon film on the mask sidewalls, and since polycrystalline silicon has a faster oxidation rate than single crystal silicon, a thick field oxide film can be obtained in a relatively short heat process.
勿論、多結晶シリコン膜の働きによりフィールド酸化膜
が素子領域に鳥のくちばし状に良い込むことも防止され
、素子領域の寸法誤差を小さく抑えることができる。更
に、フィールド反転防止用のイオン注入はマスク側壁に
多結晶シリコン膜を残した状態で行なっているため、反
転防止層が後の熱工程で素子領域に広がり、素子特性に
影響を与えることも防止される。Of course, the action of the polycrystalline silicon film prevents the field oxide film from penetrating into the device region in a bird's beak shape, and dimensional errors in the device region can be kept small. Furthermore, since the ion implantation to prevent field reversal is performed with the polycrystalline silicon film left on the sidewalls of the mask, the anti-reversal layer is prevented from spreading into the device area during the subsequent thermal process and affecting device characteristics. be done.
なお本発明は上記実施例に限られるものではなく、その
趣旨を逸脱しない範囲で種々変形して実施することがで
きる。Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the spirit thereof.
[発明の効果]
以上述べたように本発明によれば、フィールド酸化膜形
成工程に起因する結晶欠陥の発生が効果的に抑制され、
優れた素子特性の微細素子の高密度集積化が可能となる
。[Effects of the Invention] As described above, according to the present invention, the occurrence of crystal defects caused by the field oxide film forming process is effectively suppressed,
High-density integration of fine devices with excellent device characteristics becomes possible.
第1図(a)〜(f)は本発明の一実施例のフィールド
酸化膜形成工程を説明するための図、第2図(a)〜(
d)は従来のフィールド酸化膜形成工程を説明するため
の図である。
11・・・p型シリコン基板、12・・・熱酸化膜、1
3・・・Si3N4膜(耐酸化性マスク)、14・・・
多結晶シリコン躾、15・・・p+型層、16・・・フ
ィールド酸化膜。FIGS. 1(a) to (f) are diagrams for explaining the field oxide film forming process in one embodiment of the present invention, and FIGS. 2(a) to (f)
d) is a diagram for explaining a conventional field oxide film forming process. 11...p-type silicon substrate, 12...thermal oxide film, 1
3...Si3N4 film (oxidation-resistant mask), 14...
Polycrystalline silicon layer, 15...p+ type layer, 16... field oxide film.
Claims (3)
成する工程と、前記耐酸化性マスクで囲まれたフィール
ド領域の基板表面に熱酸化膜が形成された状態で基板全
面に多結晶シリコン膜を堆積する工程と、前記多結晶シ
リコン膜を異方性エッチング法によりエッチングして前
記耐酸化性マスクの側壁にのみ残置させる工程と、残置
させた多結晶シリコン膜および基板を熱酸化してフィー
ルド酸化膜を形成する工程とを備えたことを特徴とする
半導体装置の製造方法。(1) Forming an oxidation-resistant mask in the element formation region of the semiconductor substrate, and covering the entire surface of the substrate with polycrystalline silicon with a thermal oxide film formed on the substrate surface in the field region surrounded by the oxidation-resistant mask. a step of depositing a film; a step of etching the polycrystalline silicon film by an anisotropic etching method so that it remains only on the side wall of the oxidation-resistant mask; and thermally oxidizing the remaining polycrystalline silicon film and the substrate. 1. A method of manufacturing a semiconductor device, comprising the step of forming a field oxide film.
i_3N_4膜である特許請求の範囲第1項記載の半導
体装置の製造方法。(2) The oxidation-resistant mask is S formed by CVD.
The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is an i_3N_4 film.
グ法である特許請求の範囲第1項記載の半導体装置の製
造方法。(3) The method of manufacturing a semiconductor device according to claim 1, wherein the anisotropic etching method is a reactive ion etching method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7498186A JPS62232143A (en) | 1986-04-01 | 1986-04-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7498186A JPS62232143A (en) | 1986-04-01 | 1986-04-01 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62232143A true JPS62232143A (en) | 1987-10-12 |
Family
ID=13562971
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7498186A Pending JPS62232143A (en) | 1986-04-01 | 1986-04-01 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
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JP (1) | JPS62232143A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4965221A (en) * | 1989-03-15 | 1990-10-23 | Micron Technology, Inc. | Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions |
US5472905A (en) * | 1990-11-17 | 1995-12-05 | Samsung Electronics Co., Ltd. | Method for forming a field oxide layer of a semiconductor integrated circuit device |
US5599730A (en) * | 1994-12-08 | 1997-02-04 | Lucent Technologies Inc. | Poly-buffered LOCOS |
-
1986
- 1986-04-01 JP JP7498186A patent/JPS62232143A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4965221A (en) * | 1989-03-15 | 1990-10-23 | Micron Technology, Inc. | Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions |
US5472905A (en) * | 1990-11-17 | 1995-12-05 | Samsung Electronics Co., Ltd. | Method for forming a field oxide layer of a semiconductor integrated circuit device |
US5599730A (en) * | 1994-12-08 | 1997-02-04 | Lucent Technologies Inc. | Poly-buffered LOCOS |
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