JPS62230105A - Power amplifier circuit - Google Patents

Power amplifier circuit

Info

Publication number
JPS62230105A
JPS62230105A JP7068286A JP7068286A JPS62230105A JP S62230105 A JPS62230105 A JP S62230105A JP 7068286 A JP7068286 A JP 7068286A JP 7068286 A JP7068286 A JP 7068286A JP S62230105 A JPS62230105 A JP S62230105A
Authority
JP
Japan
Prior art keywords
output
operational amplifier
circuit
amplifier
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7068286A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Matsuda
光弘 松田
Tetsushi Yamashita
哲史 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Electric Equipment Corp
Original Assignee
Toshiba Electric Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Electric Equipment Corp filed Critical Toshiba Electric Equipment Corp
Priority to JP7068286A priority Critical patent/JPS62230105A/en
Publication of JPS62230105A publication Critical patent/JPS62230105A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To amplify an analog signal without distortion while reducing power consumption by providing a bias resistor between input and output terminals of a complimentary push-pull emitter follower. CONSTITUTION:A bypass resistor 11 is provided between an input terminal 6 and an output terminal 7 of a booster circuit. The resistor 11 is selected to cause a voltage VBE (nearly 0.6V) of transistors (TR) 4,5 when a current slightly smaller than the maximum output current of an operational amplifier 1 flows. Then, an output waveform of the operational amplifier l to an input signal A is expressed as a signal B. When an output of the amplifier l is within + or -0.6V, only an output current of the amplifier l is fed to a load via the resistor 11. On the other hand, when the output of the amplifier l is at the outside of the range of + or -0.6V, the TRs 4,5 are operated in the booster operating region and the complementary push-pull emitter follower circuit amplifies the output current of the operational amplifier 1. Thus, the analog signal is amplified without distortion while keeping the power consumption small.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は、電力増幅回路に関し、特に入出力端子間にバ
イパス抵抗を設けたコンプリメンタリプッシュプルエミ
ッタホロワをIC演算増幅器(以下、オペアンプという
)の出力部に有する電力増幅回路に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a power amplification circuit, and in particular, a complementary push-pull emitter follower provided with a bypass resistor between input and output terminals as an IC operational amplifier (hereinafter referred to as an operational amplifier). The present invention relates to a power amplifier circuit included in an output section of a power amplifier circuit.

[従来の技術] 従来、オペアンプの出力部にNPN型トランジスタとP
NP型トランジスタによるコンプリメンタリプッシュプ
ルエミッタホロワをブースタ回路として設け、オペアン
プの出力電流を増加させる電力増幅回路がある。
[Prior art] Conventionally, an NPN transistor and a P
There is a power amplifier circuit that uses a complementary push-pull emitter follower using an NP type transistor as a booster circuit to increase the output current of an operational amplifier.

第5図は、このような電力増幅回路の回路図を示す。同
図において1はオペアンプ、2と3は抵抗である。4は
NPN型トランジスタ、5はPNP型トランジスタで、
コンプリメンタリプッシュプルエミッタホロワを構成し
、オペアンプ1の出力電流を増加させるブースタ回路と
して作用する。
FIG. 5 shows a circuit diagram of such a power amplifier circuit. In the figure, 1 is an operational amplifier, and 2 and 3 are resistors. 4 is an NPN type transistor, 5 is a PNP type transistor,
It constitutes a complementary push-pull emitter follower and acts as a booster circuit to increase the output current of the operational amplifier 1.

6および7は、このブースタ回路の入力端および出力端
である。8は負荷抵抗、9および10はそれぞれ正負電
源である。
6 and 7 are the input and output ends of this booster circuit. 8 is a load resistance, and 9 and 10 are positive and negative power supplies, respectively.

以上の構成において、入力信号はオペアンプ1により増
幅されたのちさらにブースタ回路により増幅される。一
方、ブースタ回路の出力電流の一部は抵抗2を介してオ
ペアンプ1の入力に帰還され、オペアンプ1とブースタ
回路が一体となって反転増幅型オペアンプの負帰還制御
がなされる。
In the above configuration, the input signal is amplified by the operational amplifier 1 and then further amplified by the booster circuit. On the other hand, a part of the output current of the booster circuit is fed back to the input of the operational amplifier 1 via the resistor 2, and the operational amplifier 1 and the booster circuit are integrated to perform negative feedback control of the inverting amplifier type operational amplifier.

しかしながら従来の電力増幅回路は、オペアンプ1の出
力を直ちにコンプリメンタリプッシュプルエミッタホロ
ワで増幅していた為、トランジスタ4.5のB(ベース
)−「(エミッタ)間がバイアスされない小振幅領域(
約±o、sy )ではオペアンプ1の動作スピードが遅
いことからこの約±0.6vの領域を通過する間にクロ
スオーバー歪が発生していた。
However, in the conventional power amplifier circuit, the output of the operational amplifier 1 is immediately amplified by a complementary push-pull emitter follower, so the small amplitude region (
Since the operational speed of the operational amplifier 1 is slow at approximately ±o, sy), crossover distortion occurs while passing through this region of approximately ±0.6V.

この状態を第6図に示J信号図によって説明する。同図
(A>は入力信号の波形図である。このような入)j波
形の信号に対ツるオペアンプ1の出力信号の波形は同図
(B)のようになる。図中aで示される区間はオペアン
プ1の出力が±0.6v内の区間であり、この±0.6
vのスウィングにオペアンプ1の動作速度に見合った時
間を右する。
This state will be explained using the J signal diagram shown in FIG. Figure (A) is a waveform diagram of the input signal. The waveform of the output signal of the operational amplifier 1 corresponding to the input signal (input) j waveform is as shown in Figure (B). The section indicated by a in the figure is the section where the output of the operational amplifier 1 is within ±0.6V, and this ±0.6V is within ±0.6V.
Set a time commensurate with the operating speed of the operational amplifier 1 for the swing of v.

その間、模膜のブースタ回路を構成するトランジスタ4
.5のB−5間はバイアスされないため、このブースタ
回路の出力は同図(C)のようになり、区間aにクロス
オーバー歪が発生していた。
Meanwhile, the transistor 4 that constitutes the booster circuit of the mock-up
.. Since no bias is applied between B and 5 of 5, the output of this booster circuit becomes as shown in FIG. 5C, and crossover distortion occurs in section a.

第7図は、このブースタ回路の入出力特性を示ず。同図
に示すように、入力が変化しても出力が変化しない不連
続領11i(不感帯)、区間すがある。
FIG. 7 does not show the input/output characteristics of this booster circuit. As shown in the figure, there is a discontinuous region 11i (dead zone) or section in which the output does not change even if the input changes.

また、無信号時には1−ランジスタ4,5のB−5間が
バイアスされる限界付近で微弱な発成を発生して消費電
力が増加したり雑音を発生するという欠点がある。
Furthermore, when there is no signal, a weak signal is generated near the bias limit between transistors 1 and B-5 of transistors 4 and 5, which increases power consumption and generates noise.

[発明が解決しようとする問題点] 以上のように、従来の電力増幅回路はクロスオーバー歪
を生じ、また無信号時微弱発振をするという問題点があ
った。
[Problems to be Solved by the Invention] As described above, conventional power amplifier circuits have the problems of causing crossover distortion and weak oscillation when there is no signal.

本発明の目的は、面述従来例の問題点に鑑み、部品点数
が少な(、かつ消費電流を少なくしながらアナログ信号
を歪なく増幅することができる電力増幅回路を提供する
ことにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a power amplifier circuit that can amplify an analog signal without distortion while having a small number of components (and reducing current consumption), in view of the problems of the conventional example described above.

[問題点を解決するための手段および作用1本発明は、
小振幅領域では当然出力電流も小電流であることに着目
し、NPN型トランジスタとPNP型トランジスタから
なるコンプリメンタリプッシュプルエミッタホロワの入
出力端子間にバイパス抵抗を段【プることにより入力段
のオペアンプの出力電流が小なる場合にはバイパス抵抗
を介して負荷に電力供給すると共に、NPN型トランジ
スタおよびPNP型トランジスタを零バイアス状態にし
て、ブースタ回路での電力消費を略零にし、他方、オペ
アンプの出力電流が大なる場合には、バイパス抵抗の電
圧降下を利用して上記NPNlトランジスタおよびPN
P型トランジスタを順バイアス状態にして、ブースタ回
路がオペアンプの出力電流を増加させることを特徴とす
る。
[Means and effects for solving the problems 1 The present invention has the following features:
Focusing on the fact that the output current is naturally small in the small amplitude region, the input stage is When the output current of the operational amplifier is small, power is supplied to the load via the bypass resistor, and the NPN and PNP transistors are placed in a zero bias state to reduce the power consumption in the booster circuit to almost zero. When the output current of the NPNl transistor and PN
It is characterized in that the booster circuit increases the output current of the operational amplifier by putting the P-type transistor in a forward bias state.

以下、図面を用いて本発明をさらに詳しく説明する。な
お、従来例と同一部品については同一の符号で表わす。
Hereinafter, the present invention will be explained in more detail using the drawings. Note that parts that are the same as those in the conventional example are represented by the same reference numerals.

第1図は、本発明の電力増幅回路の回路図を示す。同図
の回路は、第5図の従来の電力増幅回路とは、ブースタ
回路の入力端6および出力端7の間にバイパス抵抗11
を有する点で異なっている。
FIG. 1 shows a circuit diagram of a power amplifier circuit of the present invention. The circuit shown in the same figure is different from the conventional power amplifier circuit shown in FIG.
They are different in that they have

このバイパス抵抗11の値は、オペアンプ1の最大出力
電流よりも若干小さい電流を流した時に、トランジスタ
4,5のV[llE電圧(約0.6V )が発生するよ
うに選定する。
The value of the bypass resistor 11 is selected so that when a current slightly smaller than the maximum output current of the operational amplifier 1 flows, a V[llE voltage (approximately 0.6 V) of the transistors 4 and 5 is generated.

以上の構成において、第2図(A)に示す入力信号に対
するオペアンプ1の出力波形は同図(B)のようになる
。このオペアンプ1の出力が±0.6Vの範囲内はオペ
アンプ1の出力電流だ番プがバイパス抵抗11を介して
負荷に供給され、一方、この±0.6Vの範囲外はブー
スタ作動領域で、トランジスタ4,5が作動しコンプリ
メンタリプッシュプルエミッタ小ロワ回路がオペアンプ
1の出力電流を増幅する。
In the above configuration, the output waveform of the operational amplifier 1 in response to the input signal shown in FIG. 2(A) is as shown in FIG. 2(B). When the output of the operational amplifier 1 is within the range of ±0.6V, the output current of the operational amplifier 1 is supplied to the load via the bypass resistor 11, while outside the range of ±0.6V is the booster operating region. Transistors 4 and 5 operate, and the complementary push-pull emitter small lower circuit amplifies the output current of operational amplifier 1.

第3図はブースタが作動しない領域での本発明の電力増
幅回路の等価回路を示す。ブースタが非動作の状態では
トランジスタ4,5の電力消費も略零であり、実質的に
バイパス抵抗11だけの回路と等価になる。
FIG. 3 shows an equivalent circuit of the power amplifier circuit of the present invention in a region where the booster does not operate. When the booster is inactive, the power consumption of the transistors 4 and 5 is approximately zero, and the circuit is substantially equivalent to a circuit including only the bypass resistor 11.

また第4図は、本発明のブースタ回路の入出力特性を示
す。ブースタが作動する領域を除いた部分はバイパス抵
抗11と負荷抵抗8の分電圧特性を示す。同図に示すよ
うに、この入出力特性は非線形ではあるが不感帯はない
Further, FIG. 4 shows the input/output characteristics of the booster circuit of the present invention. The portion excluding the area where the booster operates shows the voltage division characteristics of the bypass resistor 11 and the load resistor 8. As shown in the figure, although this input/output characteristic is nonlinear, there is no dead zone.

また、このように入出力特性は非線形となるものの、実
用上はフィードバック回路により補償できるため問題は
ない。
Further, although the input/output characteristics are nonlinear in this way, there is no problem in practice because it can be compensated for by a feedback circuit.

このように本発明の電力増幅回路は、オペアンプの動作
スピードが、略、入力周波数に応答することができる程
度の5のであってもクロスオーバー歪みの発生が無く、
良好な歪み率性能が得られ、しかも、本来の特徴である
無信号時の低消費電流特性、簡単な回路構成を同時に実
現できるものである。
As described above, the power amplifier circuit of the present invention does not generate crossover distortion even when the operating speed of the operational amplifier is approximately 5, which is a level that can respond to the input frequency.
Good distortion rate performance can be obtained, and the original characteristics of low current consumption during no signal and a simple circuit configuration can be realized at the same time.

[発明の効果J 以上説明したように本発明によれば、部品点数が少なく
、かつ消費電力を少なくしながらアナログ信号を歪なく
増幅することができる。
[Effect of the Invention J As described above, according to the present invention, an analog signal can be amplified without distortion while using a small number of parts and reducing power consumption.

また、本発明の電力増幅回路は、インターホンおよび電
話機の拡声回路に好適に使用することができる。
Further, the power amplifier circuit of the present invention can be suitably used for intercoms and loudspeaker circuits of telephones.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の電力増幅回路を適用した増幅回路の回
路図、 第2図は、第1図の回路の信号図、 第3図は、第1図の回路の小振幅領域における等価回路
図、 第4図は、第1図のブースタ回路の入出力特性図、 第5図は、従来の電力増幅回路の回路図、第6図は、第
5図の回路の信号図、 第7図は、第5図のブースタ回路の入出力特性図である
。 1・・・オペアンプ、2.3・・・抵抗、4・・・NP
N型トランジスタ、 5・・・PNP型トランジスタ、11・・・バイパス抵
抗。
Figure 1 is a circuit diagram of an amplifier circuit to which the power amplifier circuit of the present invention is applied, Figure 2 is a signal diagram of the circuit of Figure 1, and Figure 3 is an equivalent circuit in the small amplitude region of the circuit of Figure 1. Figure 4 is an input/output characteristic diagram of the booster circuit in Figure 1, Figure 5 is a circuit diagram of a conventional power amplifier circuit, Figure 6 is a signal diagram of the circuit in Figure 5, Figure 7 5 is an input/output characteristic diagram of the booster circuit of FIG. 5. FIG. 1... operational amplifier, 2.3... resistor, 4... NP
N type transistor, 5... PNP type transistor, 11... bypass resistor.

Claims (1)

【特許請求の範囲】 演算増幅器と、 該演算増幅器の出力を増幅するコンプリメンタリプッシ
ュプルエミッタホロワと、 該コンプリメンタリプッシュプルエミッタホロワの入出
力端子間に挿入されたバイパス抵抗と、上記演算増幅器
を負帰還制御するフィードバック回路と を有することを特徴とする電力増幅回路。
[Claims] An operational amplifier, a complementary push-pull emitter follower for amplifying the output of the operational amplifier, a bypass resistor inserted between the input and output terminals of the complementary push-pull emitter follower, and the operational amplifier. A power amplifier circuit comprising a feedback circuit that performs negative feedback control.
JP7068286A 1986-03-31 1986-03-31 Power amplifier circuit Pending JPS62230105A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7068286A JPS62230105A (en) 1986-03-31 1986-03-31 Power amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7068286A JPS62230105A (en) 1986-03-31 1986-03-31 Power amplifier circuit

Publications (1)

Publication Number Publication Date
JPS62230105A true JPS62230105A (en) 1987-10-08

Family

ID=13438662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7068286A Pending JPS62230105A (en) 1986-03-31 1986-03-31 Power amplifier circuit

Country Status (1)

Country Link
JP (1) JPS62230105A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000013152A (en) * 1998-01-13 2000-01-14 Xerox Corp Analog video buffer
JP2014230246A (en) * 2013-05-27 2014-12-08 旭化成エレクトロニクス株式会社 Ring amplifier and switched capacitor circuit with the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5394163A (en) * 1977-01-28 1978-08-17 Hitachi Ltd Negative feedback power amplifier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5394163A (en) * 1977-01-28 1978-08-17 Hitachi Ltd Negative feedback power amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000013152A (en) * 1998-01-13 2000-01-14 Xerox Corp Analog video buffer
JP2014230246A (en) * 2013-05-27 2014-12-08 旭化成エレクトロニクス株式会社 Ring amplifier and switched capacitor circuit with the same

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