JPS62229952A - Mis type semiconductor integrated circuit device - Google Patents

Mis type semiconductor integrated circuit device

Info

Publication number
JPS62229952A
JPS62229952A JP61072855A JP7285586A JPS62229952A JP S62229952 A JPS62229952 A JP S62229952A JP 61072855 A JP61072855 A JP 61072855A JP 7285586 A JP7285586 A JP 7285586A JP S62229952 A JPS62229952 A JP S62229952A
Authority
JP
Japan
Prior art keywords
source
drain
voltage
mos transistor
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61072855A
Other languages
Japanese (ja)
Inventor
Koji Matsuki
松木 宏司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61072855A priority Critical patent/JPS62229952A/en
Publication of JPS62229952A publication Critical patent/JPS62229952A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To obtain the MIS type semiconductor integrated circuit device provided with a monitoring transistor with which an lmuAVth and an externally inserted Vth can be made to have an equal value by a method wherein the monitoring transistor, on which the ratio of the width and length of a channel is set in such a manner that the voltage (1muAVth) between a gate and a source will be made equal to the threshold voltage (externally inserted Vth), is provided. CONSTITUTION:The drain and source of an MOS transistor Q1 are connected to the drain and source of a P-channel type MOS transistor Q2, and a pad 14 is connected to these gates respectively. The W/L of the N-channel type MOS transistor Q1 is set at 40/4, for example, and the W/L of the above- mentioned P-channel type MOS transistor Q2 is set at 20/4, for example. In other words, the size of said transistors is set corresponding to the ratio of the (gm) of the N-cannel type MOS transistor Q1 and the (gm) of the P-channel. type MOS transistor Q2. As a result, the 1muAVth and the externally inserted Vth are made equal.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) この発明は、MIS(金属−絶縁物一半導体)型半導体
集積回路装置に関するもので、特に、スレッショールド
電圧の検査用のモニタトランジスタに係わる。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to an MIS (metal-insulator-semiconductor) type semiconductor integrated circuit device, and in particular, to a device for testing threshold voltage. related to the monitor transistor.

(従来の技術) 一般に、MIS型の半導体集積回路装置にあっては、0
MO8型にせよNMO8型にせよ、第2図に示すように
同一チップ15上の空き領域、もしくはスクライブライ
ン16上の少なくとも一方に、製造工程の検査を行なう
ためのモニタトランジスタ17.181 、182を必
ず設けている。このモニタトランジスタ17.181 
、182は、主にスレッショールド電圧vthの検査の
ために用いられるもので、所定の製造プロセスを経て完
成された半導体集積回路装置が意図したく設計時に設定
した)スレッショールド電圧vthになっているか否か
を確めるために使用される。上記スレッショールド電圧
vthの検査は、通常第3図に示すように、例えばNチ
ャネル型のMOSトランジスタの場合、ドレイン・ソー
ス間電圧Vos−5Vで、ドレイン・ソース間に1μA
のドレイン・ソース間電流1osが流れる時のゲート・
ソース間電圧Vosで求められる。
(Prior Art) Generally, in an MIS type semiconductor integrated circuit device, 0
Regardless of the MO8 type or the NMO8 type, as shown in FIG. 2, monitor transistors 17, 181 and 182 are provided in at least one of the vacant areas on the same chip 15 or on the scribe line 16 to inspect the manufacturing process. It is always provided. This monitor transistor 17.181
, 182 are mainly used for testing the threshold voltage vth, and are used to ensure that the semiconductor integrated circuit device completed through a predetermined manufacturing process reaches the threshold voltage vth (as intended and set at the time of design). It is used to check whether the The above threshold voltage vth is normally tested as shown in FIG.
When a drain-source current of 1 os flows, the gate
It is determined by the source-to-source voltage Vos.

このようなスレッショールド電圧の測定は、カーブトレ
ーサにより簡単に求まるため、完成されたウェハの検査
で良く使われている。しかしながら、このスレッショー
ルド電圧はトランジスタのサイズによって異なる。すな
わち、ドレイン・ソース間電流Ioaが1μAの時のゲ
ート・ソース間電圧Vanをスレッショールド電圧vt
hとするため、MOSトランジスタのチャネル幅Wとチ
ャネル長りとの比W/Lが大きければvthは小さくな
り、W/Lが小さければvthは大きくなる。もちろん
、W/Lが同じでも製造工程の違い(例えば酸化膜厚の
差)によってもvthは変わってくる。
Such threshold voltage measurement is easily determined using a curve tracer, and is therefore often used in inspecting completed wafers. However, this threshold voltage varies depending on the size of the transistor. In other words, the gate-source voltage Van when the drain-source current Ioa is 1 μA is the threshold voltage vt.
h, if the ratio W/L of the channel width W to the channel length of the MOS transistor is large, vth will be small, and if W/L is small, vth will be large. Of course, even if the W/L is the same, vth changes depending on differences in the manufacturing process (for example, differences in oxide film thickness).

このvthの変化量は最大0.5V程度である。The amount of change in this vth is about 0.5V at maximum.

これに対し、設計時点においては、上述したスレッショ
ールド電圧(1μA V th)は用いず、トランジス
タのW/Lによらない外挿vthを用いる。
On the other hand, at the time of design, the threshold voltage (1 μA V th) described above is not used, but an extrapolated vth that does not depend on the W/L of the transistor is used.

この外挿vthは、第4図に示すようにドレイン・ソー
ス間電圧Vos−5Vで、ゲート・ソース間電圧Vos
とドレイン・ソース間電流の平方根V I o aのグ
ラフからデータを外挿し、Vos軸と交わる点のVos
をスレッショールド電圧vthとする定義である。この
定義におけるスレッショールド電圧vthは、トランジ
スタのW/Lの違いが、Vos−V]=こ1−のデータ
の傾斜の違いとなって現われるが、外挿点はほぼ同じと
なる。従って、トランジスタのW/Lの違いでスレッシ
ョールド電圧vthが変化しない。
As shown in FIG. 4, this extrapolation vth is the drain-source voltage Vos-5V, and the gate-source voltage Vos
The data is extrapolated from the graph of the square root of the drain-source current V I o a, and the Vos at the point intersecting the Vos axis is
is defined as the threshold voltage vth. Regarding the threshold voltage vth in this definition, the difference in W/L of the transistor appears as a difference in the slope of the data of Vos-V]=this 1-, but the extrapolation point is almost the same. Therefore, the threshold voltage vth does not change due to the difference in W/L of the transistor.

このように、製造プロセス技術者が使用するスレッショ
ールド電圧(1μA V th)と、設計技術者が使用
するスレッショールド電圧(外挿Vth)とが興なって
いるため、vthマージンの議論をする際に混乱を招く
欠点がある。
As described above, the threshold voltage used by manufacturing process engineers (1 μA V th) and the threshold voltage used by design engineers (extrapolated V th) are becoming more and more important, so the discussion of the V th margin is important. It has the disadvantage of causing confusion when doing so.

(発明が解決しようとする問題点) 上述した如く、従来のMIS型半導体集積回路装置にあ
っては、製造プロセス技術者が使用するスレッショール
ド電圧(1μA V th)と、設計技術者が使用する
スレッショールド電圧〈外挿vth>とが異なっており
、vthマージンの議論をする場合に混乱を招く欠点が
あった。
(Problems to be Solved by the Invention) As mentioned above, in conventional MIS type semiconductor integrated circuit devices, the threshold voltage (1 μA V th) used by manufacturing process engineers and the threshold voltage used by design engineers The threshold voltage (extrapolated vth) to be used is different, which has the disadvantage of causing confusion when discussing the vth margin.

従って、この発明の目的は、1μA V thと外挿v
thとを同じ値に出来るモニタトランジスタを備えたM
IS型半導体集積回路装置を提供することにある。
Therefore, the purpose of this invention is to calculate 1 μA V th and extrapolate v
M equipped with a monitor transistor that can make th the same value
An object of the present invention is to provide an IS type semiconductor integrated circuit device.

[発明の構成] (問題点を解決するための手段とその作用)すなわち、
この発明においては、上記の目的を達成するために、チ
ャネル幅とチャネル長との比が、ドレイン・ソース間に
所定の電圧を印加した時に1μAのドレイン・ソース間
電流が流れる時のゲート・ソース間電圧(1μAVtl
+)と、ドレイン・ソース間に所定の電圧を印加した時
のゲート・ソース間電圧とドレイン・ソース間電流の平
方根から外挿したスレッショールド電圧(外挿Vth)
とが等しくなるように設定されたモニタトランジスタを
設けている。、 (実施例) 以下、この発明の一実施例について図面を参照して説明
する。第1図は、モニタ回路の構成例を示すもので、パ
ッド11とパッド12間にはNチャネル型のMOSトラ
ンジスタQ1のドレイン、ソースがそれぞれ接続され、
パッド13と上記パッド12間にはPチャネル型のMO
SトランジスタQ2のドレイン、ソースがそれぞれ接続
される。そして、上記各MOSトランジスタQ1 、Q
2のゲートにはそれぞれ、パッド14が接続されて成る
。このモニタ回路は、前記第2図に示したように、チッ
プ15上の空き領域、もしくはスクライブライン16上
の少なくとも一方に設けられる。
[Structure of the invention] (Means for solving the problem and their effects) In other words,
In order to achieve the above object, in this invention, the ratio of the channel width to the channel length is such that when a predetermined voltage is applied between the drain and the source, a current of 1 μA flows between the gate and the source. voltage (1μAVtl
+) and the threshold voltage (extrapolated Vth) extrapolated from the square root of the gate-source voltage and drain-source current when a specified voltage is applied between the drain and source.
A monitor transistor is provided that is set so that the values are equal to each other. , (Example) An example of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the configuration of a monitor circuit, in which the drain and source of an N-channel MOS transistor Q1 are connected between pads 11 and 12, respectively.
A P-channel type MO is connected between the pad 13 and the pad 12.
The drain and source of the S transistor Q2 are connected to each other. And each of the above MOS transistors Q1, Q
Pads 14 are connected to the gates of 2, respectively. As shown in FIG. 2, this monitor circuit is provided in at least one of the empty area on the chip 15 and the scribe line 16.

上記Nチャネル型MOSトランジスタQ1のW/Lは例
えば40/4、上記Pチャネル型MOSトランジスタQ
2のW/Lは例えば20/4に設定する。換言すれば、
Nチャネル型のMOSトランジスタQ1のgmとPチャ
ネル型のMOSトランジスタQ2のgmとの比に相当す
るサイズに設定する。このようなW/Lとするのは、N
チャネル型のMOSトランジスタの易動度がPチャネル
型のMOSトランジスタの易動度の約2倍であることに
よる。これによって1μAVthと外挿vthが等しく
なる。但し、上記各モニタトランジスタの寸法(W/L
)は、製造プロセス等に応じて最適な値に設定する必要
がある。
The W/L of the N-channel MOS transistor Q1 is, for example, 40/4, and the W/L of the P-channel MOS transistor Q
The W/L of 2 is set to 20/4, for example. In other words,
The size is set to correspond to the ratio of gm of N-channel type MOS transistor Q1 to gm of P-channel type MOS transistor Q2. Such W/L is N
This is because the mobility of a channel type MOS transistor is approximately twice that of a P channel type MOS transistor. As a result, 1 μAVth and extrapolated vth become equal. However, the dimensions of each monitor transistor above (W/L
) needs to be set to an optimal value depending on the manufacturing process, etc.

このような構成によれば、製造技術者側で容易に測定で
きる1μAVthと設計技術者が使用する外挿vthと
を等しくできるので、製品のvthマージン等を議論す
る際に両者の定義するvthの変換が不要となり、混乱
を招くことがない。
With this configuration, 1 μAVth, which can be easily measured by manufacturing engineers, can be equalized with the extrapolated vth used by design engineers, so when discussing the product's vth margin, etc., the vth defined by both parties can be equalized. There is no need for conversion and no confusion.

なお、上記実施例では、MIS型半導体集積回路装置が
0MO8型の場合について説明したが、同様にしてNM
O8型のものにも適用が可能なのはもちろんである。
In the above embodiment, the case where the MIS type semiconductor integrated circuit device is 0MO8 type was explained, but in the same way, NM
Of course, it can also be applied to the O8 type.

[発明の効果1 以上説明したようにこの発明によれば、1μA V t
hと外挿vthとを同じ値に出来るモニタトランジスタ
を備えたMIS型半導体集積回路装置が得られる。
[Effect of the invention 1 As explained above, according to this invention, 1 μA V t
A MIS type semiconductor integrated circuit device is obtained that includes a monitor transistor that can make h and extrapolated vth the same value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例に係わるMIS型半導体集
積回路装置におけるモニタ回路の構成例について説明す
るための図、第2図はモニタトランジスタおよびモニタ
回路の配置例について説明するための図、第3図は1μ
AVthの定義について説明するための図、第4図は外
挿vthの定義について説明するための図である。 11〜14・・・パッド、Ql 、Q2・・・モニタト
ランジスタ、15・・・チップ、16・・・スクライブ
ライン、17゜1ax 、 182・・・モニタトラン
ジスタ、モニタ回路。 出願人代理人 弁理士 鈴江武彦 第1 図 612rI!J 只h
FIG. 1 is a diagram for explaining a configuration example of a monitor circuit in a MIS type semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining an example of the arrangement of a monitor transistor and a monitor circuit, Figure 3 is 1μ
FIG. 4 is a diagram for explaining the definition of AVth. FIG. 4 is a diagram for explaining the definition of extrapolated vth. 11-14... Pad, Ql, Q2... Monitor transistor, 15... Chip, 16... Scribe line, 17° 1ax, 182... Monitor transistor, monitor circuit. Applicant's agent Patent attorney Takehiko Suzue No. 1 Figure 612rI! J

Claims (2)

【特許請求の範囲】[Claims] (1)チップ上の空き領域あるいはスクライブライン上
の少なくともいずれか一方に、チャネル幅とチャネル長
との比が、ドレイン・ソース間に所定の電圧を印加した
時に1μAのドレイン・ソース間電流が流れる時のゲー
ト・ソース間電圧と、ドレイン・ソース間に所定の電圧
を印加した時のゲート・ソース間電圧とドレイン・ソー
ス間電流の平方根とから外挿したスレッシヨールド電圧
とが等しくなるように設定されたモニタトランジスタを
設けたことを特徴とするMIS型半導体集積回路装置。
(1) When a predetermined voltage is applied between the drain and the source with a channel width to channel length ratio of at least one of the vacant area on the chip or the scribe line, a drain-source current of 1 μA flows. The threshold voltage is set so that the gate-to-source voltage at the current time is equal to the threshold voltage extrapolated from the gate-to-source voltage and the square root of the drain-to-source current when a predetermined voltage is applied between the drain and source. A MIS type semiconductor integrated circuit device characterized by being provided with a monitor transistor.
(2)チップ上の空き領域あるいはスクライブライン上
の少なくともいずれか一方に、第1のパッドと第2のパ
ッド間に接続されゲートが第3のパッドに接続されるN
チャネル型のMOSトランジスタと、第4のパッドと上
記第2のパッド間に接続されゲートが上記第3のパッド
に接続されるPチャネル型のMOSトランジスタとから
成るモニタ回路を設け、上記各MOSトランジスタのチ
ャネル幅とチャネル長との比はそれぞれ、ドレイン・ソ
ース間に所定の電圧を印加した時に1μAのドレイン・
ソース間電流が流れる時のゲート・ソース間電圧と、ド
レイン・ソース間に所定の電圧を印加した時のゲート・
ソース間電圧とドレイン・ソース間電流の平方根とから
外挿したスレッシヨールド電圧とが等しくなるように設
定されていることを特徴とするMIS型半導体集積回路
装置。
(2) An N whose gate is connected between the first pad and the second pad and whose gate is connected to the third pad in at least one of the vacant area on the chip or on the scribe line.
A monitor circuit consisting of a channel type MOS transistor and a P channel type MOS transistor connected between a fourth pad and the second pad and having a gate connected to the third pad is provided, and each of the MOS transistors The ratio of channel width to channel length is 1 μA when a predetermined voltage is applied between the drain and source.
Gate-source voltage when source current flows and gate-source voltage when a specified voltage is applied between drain and source.
1. A MIS type semiconductor integrated circuit device, wherein a threshold voltage extrapolated from a source voltage and a square root of a drain-source current is set to be equal.
JP61072855A 1986-03-31 1986-03-31 Mis type semiconductor integrated circuit device Pending JPS62229952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61072855A JPS62229952A (en) 1986-03-31 1986-03-31 Mis type semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61072855A JPS62229952A (en) 1986-03-31 1986-03-31 Mis type semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS62229952A true JPS62229952A (en) 1987-10-08

Family

ID=13501392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61072855A Pending JPS62229952A (en) 1986-03-31 1986-03-31 Mis type semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62229952A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362641B2 (en) 1998-08-25 2002-03-26 Nec Corporation Integrated circuit device and semiconductor wafer having test circuit therein
USRE40132E1 (en) 1988-06-17 2008-03-04 Elpida Memory, Inc. Large scale integrated circuit with sense amplifier circuits for low voltage operation
JP2009003468A (en) * 1997-02-17 2009-01-08 Seiko Epson Corp Light emitting device and its driving method
US8154199B2 (en) 1997-02-17 2012-04-10 Seiko Epson Corporation Display apparatus

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE40132E1 (en) 1988-06-17 2008-03-04 Elpida Memory, Inc. Large scale integrated circuit with sense amplifier circuits for low voltage operation
JP2009003468A (en) * 1997-02-17 2009-01-08 Seiko Epson Corp Light emitting device and its driving method
US8154199B2 (en) 1997-02-17 2012-04-10 Seiko Epson Corporation Display apparatus
US8188647B2 (en) 1997-02-17 2012-05-29 Seiko Epson Corporation Current-driven light-emitting display apparatus and method of producing the same
US8247967B2 (en) 1997-02-17 2012-08-21 Seiko Epson Corporation Display apparatus
US8354978B2 (en) 1997-02-17 2013-01-15 Seiko Epson Corporation Display apparatus
US8362489B2 (en) 1997-02-17 2013-01-29 Seiko Epson Corporation Current-driven light-emitting display apparatus and method of producing the same
US6362641B2 (en) 1998-08-25 2002-03-26 Nec Corporation Integrated circuit device and semiconductor wafer having test circuit therein

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