JPS62202268A - Circuit processor - Google Patents
Circuit processorInfo
- Publication number
- JPS62202268A JPS62202268A JP61044586A JP4458686A JPS62202268A JP S62202268 A JPS62202268 A JP S62202268A JP 61044586 A JP61044586 A JP 61044586A JP 4458686 A JP4458686 A JP 4458686A JP S62202268 A JPS62202268 A JP S62202268A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- storage means
- information
- connection
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は回路処理装置に属する。[Detailed description of the invention] [Industrial application field] The present invention relates to a circuit processing device.
従来の回路処理装置は、回路記憶手段により与えられる
回路の情報をそのまま用いて回路の解析を行なっていた
。Conventional circuit processing devices analyze circuits using circuit information provided by circuit storage means as is.
このような従来の技術としては、〔遅延時間解析システ
ム−NELTAS2− )(情報処理学会、設計自動化
研究会資料、設計自動化14−3 、1982)がある
。As such a conventional technique, there is [Delay Time Analysis System - NELTAS2-] (Information Processing Society of Japan, Design Automation Study Group Materials, Design Automation 14-3, 1982).
しかしながら、このような上述した従来の回路処理装置
は、回路記憶手段により与えられる回路の情報をそのま
ま用いて回路の解析を行なっているので、対象とする回
路の解析に多くの計算機資源を必要とするという欠点が
ある。However, the above-mentioned conventional circuit processing device analyzes the circuit using the circuit information provided by the circuit storage means as it is, and therefore requires a large amount of computer resources to analyze the target circuit. There is a drawback that it does.
本発明の回路処理装置は、回路の端子、端子間の接続お
よび各接続に関する情報を記憶する回路記憶手段と、該
回路記憶手段から該回路を端子数や接続数がより少なく
かつ接続に関する情報が等価な回路に変換する回路簡略
化手段と、該回路簡酪化手段により変換された回路の情
報を記憶する簡略化回路記憶手段と、該簡略化回路記憶
手段から該回路の解析を行ない解析された結果を表示す
る回路解析手段とを有して構成される。The circuit processing device of the present invention includes a circuit storage means for storing information regarding terminals of a circuit, connections between the terminals, and each connection, and a circuit storage means that stores the circuit with a smaller number of terminals and connections and information regarding the connections. circuit simplification means for converting into an equivalent circuit; simplified circuit storage means for storing information about the circuit converted by the circuit simplification means; and analysis of the circuit from the simplified circuit storage means. and circuit analysis means for displaying the obtained results.
次に、本発明の実施例について、図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例を示すブロック図である。こ
こでは、論理回路の遅延解析を行なう例について述べる
。FIG. 1 is a block diagram showing one embodiment of the present invention. Here, an example of delay analysis of a logic circuit will be described.
第1図に示す回路処理装置は、回路記憶手段1と、回路
簡略化手段2と、簡略化回路記憶手段3と、回路解析手
段4とを含んで構成される。The circuit processing device shown in FIG. 1 includes circuit storage means 1, circuit simplification means 2, simplified circuit storage means 3, and circuit analysis means 4.
回路記憶手段lは、対象とする回路中の各端子および端
子間の接続線および接続に関する情報として遅延情報を
記憶する。回路簡略化手段2は、回路記憶手段1から読
み出した端子数や接続線数がより少なく、遅延時間に対
応する接続に関する情報が等価な回路に変換する。簡略
化回路記憶手段3は、回路部理化手段2により変換され
た回路の素子、端子、接続線および遅延情報を記憶する
。The circuit storage means 1 stores delay information as information regarding each terminal in the target circuit and the connection lines and connections between the terminals. The circuit simplification means 2 converts the circuit read out from the circuit storage means 1 into a circuit having a smaller number of terminals and a smaller number of connection lines, and having equivalent information regarding the connections corresponding to the delay time. The simplified circuit storage means 3 stores the elements, terminals, connection lines, and delay information of the circuit converted by the circuit section rationalization means 2.
回路解析手段4は、簡略化回路記憶手段3から読み出し
た情報にもとづいて遅延解析を行ない、遅延解析結果を
表示する。The circuit analysis means 4 performs delay analysis based on the information read from the simplified circuit storage means 3 and displays the delay analysis results.
第2図(al 、 (blは、回路簡略化手段2による
簡略化の一例である。第2図(alに示す回路が簡略化
されることにより、第2図fb)に示す回路が生成され
る。この際、端子5,7けそれぞれ、端子10゜11と
なり、接続線8,9は、接続線12になり、接続ffM
12の遅延時間は接続線8,9の遅延時間の和となる。FIG. 2 (al, (bl) is an example of simplification by the circuit simplification means 2. By simplifying the circuit shown in FIG. 2 (al), the circuit shown in FIG. 2 (fb) is generated. At this time, terminals 5 and 7 become terminals 10 and 11, respectively, connection wires 8 and 9 become connection wire 12, and connection ffM
The delay time of 12 is the sum of the delay times of connection lines 8 and 9.
この簡略化に伴ない端子6は消去される。Along with this simplification, the terminal 6 is eliminated.
第3図(a) 、 (b)は、回路簡略化手段2による
簡略化の他の例である。第3図fa)に示す回路が簡略
化されることにより、第3図(b)に示す回路が生成さ
れる。この際、端子13,14.16はそれぞれ端子2
0〜22となり、接続線17〜19は、接続延時間は接
続線18.19の遅延時間の和となる。3(a) and 3(b) are other examples of simplification by the circuit simplification means 2. FIG. By simplifying the circuit shown in FIG. 3fa), the circuit shown in FIG. 3(b) is generated. At this time, terminals 13, 14, and 16 are respectively terminal 2.
0 to 22, and for the connection lines 17 to 19, the total connection time is the sum of the delay times of the connection lines 18 and 19.
この簡略化に伴ない端子15は消去される。Along with this simplification, the terminal 15 is eliminated.
本発明の回路処理装置は、回路解析前に、対象とする回
路を端子数や接続線数がより少なくかつ接続に関する情
報が等価な回路に変換することにより、該回路の解析に
必要な計算機資源をよシ少なくすることができるという
効果がある。Before circuit analysis, the circuit processing device of the present invention converts a target circuit into a circuit with fewer terminals and connection wires and equivalent connection information, thereby reducing the computer resources necessary for analyzing the circuit. This has the effect of reducing the amount of damage.
第1図は本発明の一実施例を示すグロ、ンク図、第2図
[a) 、 (b)は第1図に示す回路簡略化手段によ
る変換前後の論理回路の端子および接続情報の一例を説
明するための接続状態図、第3図(a) 、 (b)は
第1図に示す回路簡略化手段による変換前後の論理回路
の端子および接続情報の他の例を説明するための接続状
態図である。
1・・・・・・回路記憶手段、2・・・・・・回路簡略
化手段、3・・・・・・簡略化回路記憶手段、4・・・
・・・回路解析手段、5〜7,10,11.13〜16
.20〜22・・・・・・端子、(aノ
$2I!r
千 3 面FIG. 1 is a diagram showing one embodiment of the present invention, and FIGS. 2 (a) and (b) are examples of terminal and connection information of the logic circuit before and after conversion by the circuit simplification means shown in FIG. 1. FIGS. 3(a) and 3(b) are connection state diagrams for explaining the terminals and connection information of the logic circuit before and after conversion by the circuit simplification means shown in FIG. 1. FIG. 1...Circuit storage means, 2...Circuit simplification means, 3...Simplification circuit storage means, 4...
...Circuit analysis means, 5-7, 10, 11.13-16
.. 20-22...Terminal, (aノ$2I!r 1,000 3 sides
Claims (1)
情報を記憶する回路記憶手段と、前記回路記憶手段から
読み出した端子数や接続線数がより少なくかつ接続に関
する情報が等価な回路に変換する回路簡略化手段と、前
記回路簡略化手段により変換された回路の情報を記憶す
る簡略化回路記憶手段と、前記簡略化回路記憶手段から
読み出した情報にもとづいて解析を行ない解析された結
果を表示する回路解析手段とを含むことを特徴とする回
路処理装置。A circuit storage means for storing information regarding terminals of a circuit, connection lines between the terminals, and each connection; and a circuit for converting information read from the circuit storage means into a circuit having a smaller number of terminals and connection wires and having equivalent information regarding the connections. A simplification means, a simplification circuit storage means for storing information of the circuit converted by the circuit simplification means, and an analysis is performed based on the information read from the simplification circuit storage means and the analyzed result is displayed. A circuit processing device comprising circuit analysis means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61044586A JPS62202268A (en) | 1986-02-28 | 1986-02-28 | Circuit processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61044586A JPS62202268A (en) | 1986-02-28 | 1986-02-28 | Circuit processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62202268A true JPS62202268A (en) | 1987-09-05 |
Family
ID=12695586
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61044586A Pending JPS62202268A (en) | 1986-02-28 | 1986-02-28 | Circuit processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62202268A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08202761A (en) * | 1995-01-30 | 1996-08-09 | Nec Corp | Logic circuit delay information holding system |
US6275238B1 (en) | 1998-01-19 | 2001-08-14 | Nec Corporation | Path compression system for compressing path in graph information and path compression method thereof |
JP2003500745A (en) * | 1999-05-26 | 2003-01-07 | ゲット2チップ | Inter-service application service provider |
-
1986
- 1986-02-28 JP JP61044586A patent/JPS62202268A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08202761A (en) * | 1995-01-30 | 1996-08-09 | Nec Corp | Logic circuit delay information holding system |
US6275238B1 (en) | 1998-01-19 | 2001-08-14 | Nec Corporation | Path compression system for compressing path in graph information and path compression method thereof |
JP2003500745A (en) * | 1999-05-26 | 2003-01-07 | ゲット2チップ | Inter-service application service provider |
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