JPS62195264U - - Google Patents
Info
- Publication number
- JPS62195264U JPS62195264U JP8079486U JP8079486U JPS62195264U JP S62195264 U JPS62195264 U JP S62195264U JP 8079486 U JP8079486 U JP 8079486U JP 8079486 U JP8079486 U JP 8079486U JP S62195264 U JPS62195264 U JP S62195264U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- counter
- output
- converter
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 2
- 238000013139 quantization Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は第１図に示した電子ボリユームへの入力
信号のグラフ、第３図は上記電子ボリユームの出
力信号を示すグラフである。
１は電子ボリユーム、２はＡ／Ｄ変換器、３は
シフトレジスタ、７は切替スイツチ（切替え手段
）、８・９はカウンタ、１０・１１・１２はＡＮ
Ｄ回路（論理回路）、１３はＮＯＲ回路（論理回
路）、１４はアツプダウンカウンタ、１５はメモ
リー、１８は基準信号発生器である。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a graph of input signals to the electronic volume shown in FIG. 1, and FIG. 3 is a graph of output signals of the electronic volume. 1 is an electronic volume, 2 is an A/D converter, 3 is a shift register, 7 is a changeover switch (switching means), 8 and 9 are counters, and 10, 11, and 12 are AN
A D circuit (logic circuit), 13 a NOR circuit (logic circuit), 14 an up-down counter, 15 a memory, and 18 a reference signal generator.
Claims (1)
力の制御信号により設定される減衰量に基づいて
入力アナログ信号の振幅を調整する電子ボリユー
ムと、基準信号発生器出力の制御信号を記憶する
メモリーと、電子ボリユーム出力のアナログ信号
をデジタル信号に変換するＡ／Ｄ変換器と、Ａ／
Ｄ変換器の量子化ビツト数を有し、Ａ／Ｄ変換器
のデジタル出力を記憶するシフトレジスタと、シ
フトレジスタからのデジタル信号をカウンタにて
計数されるパルス信号に処理する論理回路と、論
理回路の出力パルスをカウントし、入力アナログ
信号の減衰量を設定する制御信号を送出するカウ
ンタと、上記電子ボリユームの接続を、カウンタ
、録音状態、及びメモリーに切り替える切替え手
段と、制御信号である録音レベル信号を発生する
基準信号発生器とを備えたことを特徴とするＰＣ
Ｍ録音機の自動レベル設定装置。 An electronic volume that adjusts the amplitude of the input analog signal based on the attenuation amount set by the control signal stored in the memory and the control signal of the counter output, a memory that stores the control signal of the reference signal generator output, and the electronic volume. An A/D converter that converts the output analog signal into a digital signal, and an A/D converter that converts the output analog signal into a digital signal.
A shift register that has the quantization bit number of the D converter and stores the digital output of the A/D converter, a logic circuit that processes the digital signal from the shift register into a pulse signal that is counted by a counter, and a logic circuit that processes the digital signal from the shift register into a pulse signal that is counted by a counter. A counter that counts the output pulses of the circuit and sends out a control signal that sets the amount of attenuation of the input analog signal, a switching means that switches the connection of the electronic volume to the counter, recording state, and memory, and a recording that is the control signal. A PC characterized in that it is equipped with a reference signal generator that generates a level signal.
Automatic level setting device for M recorders.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8079486U JPS62195264U (en) | 1986-05-28 | 1986-05-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8079486U JPS62195264U (en) | 1986-05-28 | 1986-05-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62195264U true JPS62195264U (en) | 1987-12-11 |
Family
ID=30931928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8079486U Pending JPS62195264U (en) | 1986-05-28 | 1986-05-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62195264U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5030457A (en) * | 1973-07-06 | 1975-03-26 | ||
| JPS5745720A (en) * | 1980-09-03 | 1982-03-15 | Hitachi Ltd | Quantizing circuit |
-
1986
- 1986-05-28 JP JP8079486U patent/JPS62195264U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5030457A (en) * | 1973-07-06 | 1975-03-26 | ||
| JPS5745720A (en) * | 1980-09-03 | 1982-03-15 | Hitachi Ltd | Quantizing circuit |
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