JPS62190934A - Data demodulating device - Google Patents
Data demodulating deviceInfo
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- JPS62190934A JPS62190934A JP61031831A JP3183186A JPS62190934A JP S62190934 A JPS62190934 A JP S62190934A JP 61031831 A JP61031831 A JP 61031831A JP 3183186 A JP3183186 A JP 3183186A JP S62190934 A JPS62190934 A JP S62190934A
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- 238000001514 detection method Methods 0.000 claims description 8
- 230000010363 phase shift Effects 0.000 claims description 3
- 230000004048 modification Effects 0.000 claims 4
- 238000012986 modification Methods 0.000 claims 4
- 230000002411 adverse Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000013507 mapping Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この本発明は、たたみ込み符号化と直交振幅変調とを組
み合わせた通信方式で使用される、自動等化器と自動位
相制御回路とヴィタビ復号器を骨えたデータ復調装置に
関する。特に、ヴィタビ復号器の出力を用いて、自動等
化器と自動位相制御ＣＣＩＴＴは現在、ｆ！を語口線用
として、１４．４ｋｂｐｓのデータ変復調方式を観告し
ようとしている。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an automatic equalizer, an automatic phase control circuit, and a Viterbi decoder used in a communication system that combines convolutional coding and quadrature amplitude modulation. This invention relates to a data demodulation device with improved functionality. In particular, using the output of the Viterbi decoder, the automatic equalizer and automatic phase control CCITT now uses f! We are trying to develop a 14.4 kbps data modulation/demodulation system for speech lines.
現在観告草案が作成ずみ（ＣＣＩＴＴ呼称 Ｖ。A review draft has now been prepared (CCITT designation V).
ＣＣ）で、はぼこの案どうりの観告がおこなわれると見
られている。CC), it is expected that a viewing will be held as planned by Haboko.
本方式は、１４．４ｋｂｐｓのデータを２．４ｋｂａｕ
ｄの変調速度で伝送するものであり、従って１シンボル
当りの情報伝送速度は６ビツトである。この６ビツトの
うちの下位２ビツトが差動符号化及びたたみ込み符号化
される。たたみ込み符号器は符号化率２／３、状態数８
のもので第２図に示す構成をとる。符号化出力は、１２
８値直交振幅変調され通信される。この信号点配置を第
３図に示す。This method converts 14.4kbps data into 2.4kbaud.
The information transmission rate per symbol is 6 bits. The lower two bits of these six bits are differentially encoded and convolutionally encoded. The convolutional encoder has a coding rate of 2/3 and a number of states of 8.
It has the configuration shown in Figure 2. The encoded output is 12
The signal is 8-value orthogonal amplitude modulated and communicated. This signal point arrangement is shown in FIG.
なお、第３図において、バイナリ−ナンバは。In addition, in FIG. 3, the binary numbers are as follows.
０６ｎ、０５ｎ＝ ０４ｎ、０３ｎ、Ｑ’ ２ｎ−Ｑ’
Ｌ＋−Ｑ’ Ｏｎを表わし、Ａ、Ｂ、Ｃ，Ｄは同期
信号成分を示している。06n, 05n= 04n, 03n, Q'2n-Q'
It represents L+-Q' On, and A, B, C, and D represent synchronization signal components.
ここでこのような変調方式に対する従来の復調方式を説
明する。第４図は、従来のデータ復調装置の回路構成を
示す図であり、１は、変調波の入力端子、２はＡ／Ｄ変
換器、３は復調器、４はロールオフ・フィルタ、５は自
動等化器、６は自動位相制御回路、７はヴィタビ（Ｖｉ
ｔａｒｂｉ）復号器、８はデータ信号の出力端子、９は
誤差検出器、１゜はタイミング再生回路、１１は差動復
号器である。Here, a conventional demodulation method for such a modulation method will be explained. FIG. 4 is a diagram showing the circuit configuration of a conventional data demodulator, in which 1 is a modulated wave input terminal, 2 is an A/D converter, 3 is a demodulator, 4 is a roll-off filter, and 5 is a 6 is an automatic phase control circuit, 7 is a Viterbi (Vi
8 is a data signal output terminal, 9 is an error detector, 1° is a timing recovery circuit, and 11 is a differential decoder.
まず変調波１０１はＡ／Ｄ変換器２によりディジタル信
号信号１０２に変換される。信号１０２は、復調器３に
おいて、固定搬送波により２軸回期検波され複素信号１
０３となる。複素信号１０３はロールオフ・フィルタ４
に入力されると共に、タイミング再生回路１０にも入力
され受信タイミングが再生される。First, a modulated wave 101 is converted into a digital signal 102 by an A/D converter 2. The signal 102 is subjected to two-axis periodic detection using a fixed carrier wave in the demodulator 3 and becomes a complex signal 1.
It becomes 03. Complex signal 103 is passed through roll-off filter 4
The signal is input to the timing reproducing circuit 10, and the reception timing is reproduced.
ロールオフ・フィルタ４の出力信号１０４は、自動等化
器５に入力され、線路歪が取り除かれ、信号１０５とな
る。信号１０５は、自動位相制御回路６に入力され、上
記固定搬送波と真の搬送波との間の位相ずれに起因して
生じた位相誤差が除去され信号１０６となる。信号１０
６はヴィタビ復号器７に入力され、ユークリッド距離に
基づいたヴィタビ復号がおこなわれ、データ信号１０７
が出力される。最後にデータ信号１０７が差動復号器１
１によって差動復号化され、データ出力１１１となる。The output signal 104 of the roll-off filter 4 is input to an automatic equalizer 5 to remove line distortion and becomes a signal 105. The signal 105 is input to the automatic phase control circuit 6, where a phase error caused by a phase shift between the fixed carrier wave and the true carrier wave is removed, resulting in a signal 106. signal 10
6 is input to the Viterbi decoder 7, where Viterbi decoding is performed based on the Euclidean distance, and the data signal 107 is
is output. Finally, the data signal 107 is sent to the differential decoder 1
1 and is differentially decoded, resulting in data output 111.
さて、自動等化器５並びに自動位相制御回路６は、その
名の通り、伝送路特性に合わせて、特性が変化する。こ
の制御を実現するために、ヴィタビ復号器７は、データ
出力１０７に対応する信号点（第３図参照）を信号１０
８として出力する。信号１０６は本来は信号１０８に一
致すべきものであるが。Now, as the name suggests, the characteristics of the automatic equalizer 5 and the automatic phase control circuit 6 change according to the transmission path characteristics. To realize this control, the Viterbi decoder 7 converts the signal point (see FIG. 3) corresponding to the data output 107 into the signal 10
Output as 8. Signal 106 should originally match signal 108.
ａ路歪、搬送波の位相誤差、回線雑音により実際には異
なる。この誤差が誤差検出回路９によって検出される。In reality, it differs due to a-path distortion, carrier wave phase error, and line noise. This error is detected by the error detection circuit 9.
すなわち、誤差検出回路内の割算器により位相誤差１０
９が検出され、引算器によって歪成分１１０が検出され
る。自動位相制御回路６は、最大傾斜法を用いて上記位
相誤差１０９の電力が最小となるように特性を動かす、
同様に自動等化器５は、最大傾斜法を用いて上記歪成分
１１０の電力が最小となるよう、特性を動かす。That is, the phase error is 10 by the divider in the error detection circuit.
9 is detected, and a distortion component 110 is detected by the subtractor. The automatic phase control circuit 6 uses the maximum slope method to change the characteristics so that the power of the phase error 109 is minimized.
Similarly, the automatic equalizer 5 uses the maximum slope method to change the characteristics so that the power of the distortion component 110 is minimized.
これらの従来回路の具体的構成については、下記文献〔
１〕および〔２〕に詳細な記述があるのでここでは省略
する。For specific configurations of these conventional circuits, see the following document [
1] and [2], so detailed descriptions are omitted here.
（１） Ｆａｌｃｏｎｅｔ、“Ｊｏｉｎｔｌｙ ａｄａ
ｐｔｉｖｅ ｅｑｕａｌｉｚａ−ｔｉｏｎ ａｎｄ ｃ
ａｒｒｉｅｒ ｒｅｃｏｖｅｒｙ ｉｎ ｔｗｏ ｄｉ
ｍｅｎｓｉｏｎａｌｃｏｍｍｕｎｉｃａｔｉｏｎ ｓｙ
ｓｔｅｍｓ、” ＢＳＴＴ、 ５５．３． Ｐ ３１７
゜Ｍａｒ、 １０７６
（２） Ｇ、 Ｄ、 Ｆｏｒｎｅｙ、“Ｔｈｅ Ｖｉｔ
ｅｒｂｉ Ａｌｇｏｒｉｔｈｎｍｍ。(1) Falconet, “Jointly ada
ptive equalization and c
arrier recovery in two di
mensional communication system
stems,” BSTT, 55.3. P 317
゜Mar, 1076 (2) G. D. Forney, “The Vit
erbiAlgorithnmm.
”Ｐｒｏｃ、ｏｆ ＩＥＥＥ、６１，３．Ｍａｒ、、
１９７３自動等化器、自動位相制御回路は、前述のよう
にヴィタビ復号器からの出力を受けて、適応的に特性を
修正する。このような方式の問題点は、ヴィタビ復号器
によって判定誤りが生じた場合、誤まった誤差信号が自
動等化層並びに自動位相制御回路に帰還し、両者におい
て特性の修正を誤まってしまうことである。高Ｓ／Ｎの
場合には１判定誤りがほとんど生じないので、この問題
点が顕在化することはない。しかし、低Ｓ／Ｎで、判定
誤り確率が高い場合には、自動等化器並びに自動位相制
御回路の特性が相当乱れる。ただでさえ高い判定誤り確
率が、自動等化器、自動位相制御回路の特性の乱れによ
ってさらに悪化することになる。“Proc, of IEEE, 61, 3. Mar.
The 1973 automatic equalizer and automatic phase control circuit receive the output from the Viterbi decoder and adaptively modify the characteristics as described above. The problem with this method is that when a decision error occurs in the Viterbi decoder, the erroneous error signal is fed back to the automatic equalization layer and the automatic phase control circuit, resulting in incorrect correction of characteristics in both. It is. In the case of a high S/N, a one-judgment error hardly occurs, so this problem does not become apparent. However, when the S/N is low and the probability of judgment error is high, the characteristics of the automatic equalizer and automatic phase control circuit are considerably disturbed. The already high probability of a decision error is further exacerbated by disturbances in the characteristics of the automatic equalizer and automatic phase control circuit.
極端な場合には、この悪循環によって、モデムの同期が
はずれることもある。In extreme cases, this vicious cycle can cause modems to become unsynchronized.
この発明は、このような問題に鑑みなされたものであり
、判定誤りによって自動等化器並びに自動位相制御回路
の特性が乱れることを防止したデータ復調装置を提供す
るを目的とする。The present invention has been made in view of such problems, and an object of the present invention is to provide a data demodulation device that prevents the characteristics of an automatic equalizer and an automatic phase control circuit from being disturbed due to judgment errors.
上記目的を達成するために１本発明ではヴィタビ復号器
の判定結果が誤まっている可能性が強い時には、自動等
化器並びに自動位相制御回路への誤差信号の帰還を中止
、ないしは帰還量を少なくしている。特に１本発明では
、ヴィタビ復号結果の信頼性を最小のバスメトリックと
、二番目に対さいパスメトリックの差の大きさで評価し
たことを特徴としている。In order to achieve the above object, the present invention stops feeding back the error signal to the automatic equalizer and automatic phase control circuit or reduces the amount of feedback when there is a strong possibility that the judgment result of the Viterbi decoder is incorrect. I'm doing less. In particular, one feature of the present invention is that the reliability of the Viterbi decoding result is evaluated based on the magnitude of the difference between the smallest bus metric and the second smallest path metric.
更に、この発明は、たたみ込み符号化と直交振幅変調が
おこなわれた入力変調波信号に対して、基準搬送波を用
いて２軸検波をおこなう復調手段と、線路歪を除去する
自動等化手段と、上記基準搬送波と真の搬送波との間の
位相ずれに起因して生ずる２軸間の相互干渉を除去する
自動位相制御手段と、パスメトリックの計算に基づき生
残りパスを更新しかつ復号データを決定する。いわゆる
ヴィタビ復号手段と、ヴィタビ復号手段の人出カ間の誤
差を検出し、以って自動等化手段及び自動位相制御手段
の特性を修正するための誤差検出手段とを備えたデータ
復調装置において、最小のパスメトリックと二番目に小
さいパスメトリックの差に基づき帰還係数を決定する帰
還係数決定手段と、上記誤差検出手段からの誤差出力と
上記帰還係数と乗算し、以って誤差信号の自動等化手段
及び位相制御手段への帰還量を制御する乗算器とを備え
たことを特徴とする。Furthermore, the present invention includes demodulation means for performing two-axis detection using a reference carrier wave on an input modulated wave signal subjected to convolutional encoding and orthogonal amplitude modulation, and automatic equalization means for removing line distortion. , an automatic phase control means for removing mutual interference between two axes caused by a phase shift between the reference carrier wave and the true carrier wave, and updating the surviving path based on path metric calculation and updating the decoded data. decide. In a data demodulation device comprising a so-called Viterbi decoding means and an error detection means for detecting an error between the output power of the Viterbi decoding means and correcting the characteristics of the automatic equalization means and the automatic phase control means. , feedback coefficient determining means for determining a feedback coefficient based on the difference between the smallest path metric and the second smallest path metric, and multiplying the error output from the error detecting means by the feedback coefficient, thereby automatically detecting the error signal. It is characterized by comprising equalization means and a multiplier that controls the amount of feedback to the phase control means.
パスメトリックは、各々の生き残りパスのｔ′度を示す
ものであるから、これをもとに復号データの信頼性が評
価できる。すなわち、復号データの信頼性が高いときに
は、復号データに対応する生き残りパスのパスメトリッ
クが、他の生き残りパスのパスメトリックより、はるか
に小さく （１度でみれば高く）なる。Since the path metric indicates the degree t' of each surviving path, the reliability of decoded data can be evaluated based on this. That is, when the reliability of decoded data is high, the path metric of the surviving path corresponding to the decoded data is much smaller (higher in terms of one degree) than the path metrics of other surviving paths.
一方、復号データの信頼性が低いときには、この差は縮
まる。従って、最小のパスメトリックと二番目に小さい
パスメトリックスの差を計算し。On the other hand, when the reliability of decoded data is low, this difference decreases. Therefore, calculate the difference between the smallest path metric and the second smallest path metric.
これが大きいほど復号データの信頼性が高いと判断でき
る０本発明はこの性質を利用し上記量を用いて、誤差信
号の自動等化器並びに自動位相制御回路への帰還量を制
御したものである。The larger this value is, the higher the reliability of the decoded data can be judged. The present invention takes advantage of this property and uses the above amount to control the amount of feedback of the error signal to the automatic equalizer and automatic phase control circuit. .
このような本発明を用いれば検分データの信頼性が低い
ときには誤差信号の帰還量を相対的に小さくできる。従
って、判定誤りによる自動等化器並びに自動位相制御回
路の特性の乱れが少なくなる。これによって、前述の悪
循環を断ち切ることができ、低Ｓ／Ｎ時の誤り率特性を
改善できる。By using the present invention as described above, when the reliability of inspection data is low, the amount of feedback of the error signal can be made relatively small. Therefore, disturbances in the characteristics of the automatic equalizer and automatic phase control circuit due to judgment errors are reduced. This makes it possible to break the aforementioned vicious cycle and improve the error rate characteristics when the S/N is low.
さらに、同期はずれの確率を従来と比較し、格段に減少
できる。Furthermore, the probability of out-of-synchronization can be significantly reduced compared to the conventional method.
以下、本発明の詳細を図示の実施例に基づき説明する。 Hereinafter, details of the present invention will be explained based on illustrated embodiments.
第１図は本発明に基づくデータ復調装置の全体構成図で
ある６図の大部分は第４図と同一なので、異なる部分の
みを説明する。ヴィタビ復号器７からの出力信号１１４
は、信号１０８の４Ｂ頼性を示す０〜１の係数（ここで
は帰還数とよぶ）である。この帰還係数は信頼性が低い
ときはＯに近くなり、信頼性が高いときは１に近くなる
。帰還係数は、最小のパスメトリックと、二番目に小さ
いパスメトリックの差を適切に変換して得られる係数で
あるが、この詳細は後述する。この帰還係数は５乗算器
１２及び１３に導かれ、それぞれ信号１０９゜１１０と
乗算されて、信号１１２及び１１３が形成される。FIG. 1 is an overall configuration diagram of a data demodulating device based on the present invention. Most of FIG. 6 is the same as FIG. 4, so only the different parts will be explained. Output signal 114 from Viterbi decoder 7
is a coefficient of 0 to 1 (herein referred to as the feedback number) indicating the 4B reliability of the signal 108. This feedback coefficient is close to O when reliability is low, and close to 1 when reliability is high. The feedback coefficient is a coefficient obtained by appropriately converting the difference between the smallest path metric and the second smallest path metric, and the details will be described later. This feedback factor is led to 5 multipliers 12 and 13 and multiplied by signals 109 and 110, respectively, to form signals 112 and 113.
信号１１２及び１１３は、信号１０９．１１０をその信
頼性に応じて減衰させたものとなっている。信号１０９
゜１１０の代わりに信号１１２，１１３をそれぞれ自動
位相制御回路、自動等化層に帰還すれば１判定誤りによ
る悪影響を防げることは言うを待たない。Signals 112 and 113 are attenuated versions of signals 109 and 110 depending on their reliability. signal 109
Needless to say, if the signals 112 and 113 are fed back to the automatic phase control circuit and the automatic equalization layer instead of the signal 110, it is possible to prevent the adverse effects caused by a single judgment error.
次に、ヴィタビ復号器７の実施例を第５図に示し、これ
を用いて信号１１４の生成法を説明する。Next, an embodiment of the Viterbi decoder 7 is shown in FIG. 5, and a method of generating the signal 114 will be explained using this example.
７１はブランチ・メトリック計算回路、７２は加算・比
較・選択（ＡＣ８）回路、７３はパスメモリ、７４は出
力選択回路、７５はパリティ除去回路、７６はマツピン
グ回路、７８は比較器、７９は比較減算回路、８０は係
数変換回路である。なお、図において二重線は信号が複
数であることを示す。71 is a branch/metric calculation circuit, 72 is an addition/comparison/selection (AC8) circuit, 73 is a path memory, 74 is an output selection circuit, 75 is a parity removal circuit, 76 is a mapping circuit, 78 is a comparator, and 79 is a comparison circuit. The subtraction circuit 80 is a coefficient conversion circuit. Note that in the figure, double lines indicate that there are multiple signals.
まず、ブランチ・メトリックス計算回路７１は、自動位
相制御回路６からの信号１０６を入力し、ブランチメト
リック１１５を求める。加算比較選択回路７２は、ヴィ
タビ復号器のいわゆるＡＣ３動作をおこなう。すなわち
、パスメトリックスの更新をおこない、生き残りパス選
択の指示（信号１１６）をおこなう。パスメモリ７３は
信号１１６は指示通りに生き残りパスの更新をおこなう
、一方、比較器７８は、状態数と同じ個数だけあるパス
メトリック１２０を相互比較し、バスメトリックスを最
小にする状態番号１２１を出力する。出力選択回路７４
は、状態番号１２１を用いてパスメトリック最小に対応
する（すなわちｔ′度が最も高い）生き残りパスを選択
し、このパスの中の最も高いデータを復号データ１１８
として出力する。この復号データ７ビツトのうち、最下
位ビットはパリティビットであるから（第２図参照）、
パリティ除去回路７５はこれを除去し、上位６ビツトの
みを正味の復号データ１０７として出力する。First, the branch metric calculation circuit 71 receives the signal 106 from the automatic phase control circuit 6 and calculates the branch metric 115. The addition comparison selection circuit 72 performs the so-called AC3 operation of the Viterbi decoder. That is, the path metrics are updated and a surviving path selection instruction (signal 116) is issued. The path memory 73 updates the surviving paths as instructed by the signal 116, while the comparator 78 mutually compares the path metrics 120, which are the same in number as the number of states, and outputs the state number 121 that minimizes the bus metrics. do. Output selection circuit 74
selects the surviving path corresponding to the minimum path metric (that is, the highest degree t') using the state number 121, and uses the highest data in this path as the decoded data 118.
Output as . Of these 7 bits of decoded data, the least significant bit is the parity bit (see Figure 2), so
Parity removal circuit 75 removes this and outputs only the upper 6 bits as net decoded data 107.
なお、自動等化器５並びに自動位相制御回路６で用いら
れる参照信号１０８は、マツピング回路７６で復号デー
タ１１８をマツピングすることにより得られる。マツピ
ング回路７６は、第３図に基づくマツピング操作をおこ
なうものであることは言うまでもない。Note that the reference signal 108 used in the automatic equalizer 5 and the automatic phase control circuit 6 is obtained by mapping the decoded data 118 in the mapping circuit 76. It goes without saying that the mapping circuit 76 performs the mapping operation based on FIG.
本発明の大きな特徴である帰還係数は、第５図の最下位
のパスで生成される。まず、加算・比較・選択回路７２
からのパスメトリック信号１２０を受け。The feedback coefficient, which is a major feature of the present invention, is generated in the lowest path in FIG. First, addition/comparison/selection circuit 72
receives the path metric signal 120 from.
比較・減算回路７９は最小のバスメトリックスと、二番
目に小さいパスメトリックの差を計算し、信号１２２と
して出力する。これを係数変換回路８ｏで変換して帰還
係数１１４とするわけである。係数変換回路８０で変換
方法の一例を第６図に示す、変換方法の条件は、帰還係
数がＯ〜１におさまること、信号１２２と帰還係数の関
数が単調増加であることだけであり、第６図以外にも変
換方法は種々変更可能である。The comparison/subtraction circuit 79 calculates the difference between the smallest bus metric and the second smallest path metric and outputs it as a signal 122. This is converted into a feedback coefficient 114 by the coefficient conversion circuit 8o. An example of the conversion method in the coefficient conversion circuit 80 is shown in FIG. The conversion method can be changed in various ways other than the one shown in FIG.
第１図は、本発明の一実施例に基づくデータ復調装置の
全体構成図、第２図は、ＣＣＩＴＴ観告草案Ｖ、ＣＣに
おけるたたみ込み符号化器を示す図、第３図は、ｃｃ
Ｉ ＴＴｌ！３１告草案ｖ、ｃｃにおける信号点配置を
示す図、第４図は、たたみ込み符号と直交振幅変調を組
み合わせた通信方式に対する従来のデータ復調装置を示
す図、第５図は、第１図におけるヴィタビ復号器の一実
施例を示す図、第６図は、係数変換回路の変換方法の一
例を示す図である。
１・・・変調波の入力端子 ２・・・Ａ／Ｄ変換器３・
・・復調器
４・・・ロールオフフィルタ
５・・・自動等化器 ６・・・自動位相制御回路
７・・・ヴィタビ（Ｖｉｔｓｒｂｉ）復号器８・・・デ
ータ信号の出力端子
９・・・誤差検出器
ｌＯ・・・タイミング再生回路
１１・・・差動復号器
１２および１３・・・乗算器
代理人 弁理士 則 近 憲 佑
同 竹 花 喜久男
／？？
第５図
第６図FIG. 1 is an overall configuration diagram of a data demodulation device based on an embodiment of the present invention, FIG. 2 is a diagram showing a convolutional encoder in CCITT observation draft V, CC, and FIG. 3 is a diagram showing a convolutional encoder in CC.
ITTl! FIG. 4 is a diagram showing a conventional data demodulation device for a communication system that combines convolutional codes and orthogonal amplitude modulation, and FIG. FIG. 6, which is a diagram showing an embodiment of the Viterbi decoder, is a diagram showing an example of the conversion method of the coefficient conversion circuit. 1... Input terminal of modulated wave 2... A/D converter 3.
... Demodulator 4 ... Roll-off filter 5 ... Automatic equalizer 6 ... Automatic phase control circuit 7 ... Viterbi (Vitsrbi) decoder 8 ... Data signal output terminal 9 ... Error detector lO...timing recovery circuit 11...differential decoders 12 and 13...multiplier agent Patent attorney Noriyuki Chika Yudo Kikuo Takehana/? ? Figure 5 Figure 6
Claims (6)
ルスメトリックの演算から生残りパスを更新し、かつ復
号データを決定するヴィタビ復号手段と、このヴィタビ
復号手段の出力に基づき前記自動等化手段の特性を修正
する手段とを備えたデータ復調装置において、 前記ヴィタビ復号手段での復号結果の信頼性を評価し、
これに応じて前記自動等化手段の特性の修正量を制御す
ることを特徴とするデータ復調装置。(1) Automatic equalization means for removing line distortion of the received signal; Viterbi decoding means for updating surviving paths from pulse metric calculations and determining decoded data; and based on the output of the Viterbi decoding means, the automatic and means for modifying the characteristics of the equalization means, the reliability of the decoding result by the Viterbi decoding means is evaluated,
A data demodulating device characterized in that the amount of modification of the characteristics of the automatic equalization means is controlled in accordance with this.
施された入力変調波信号に対して、基準搬送波を用いて
２軸検波を行う復調手段からの出力信号であることを特
徴とする特許請求の範囲第１項記載のデータ復調装置。(2) The received signal is an output signal from demodulation means that performs two-axis detection using a reference carrier wave on an input modulated wave signal subjected to convolutional encoding and orthogonal amplitude modulation. A data demodulating device according to claim 1.
リックの差に基づく帰還係数とヴィタビ復号手段の入出
力信号間の誤差とから自動等化手段への帰還量を制御し
、もって前記自動等化手段での特性の修正量を制御する
ことを特徴とする特許請求の範囲第１項記載のデータ復
調装置。(3) The amount of feedback to the automatic equalization means is controlled from the feedback coefficient based on the difference between the smallest path metric and the second smallest path metric and the error between the input and output signals of the Viterbi decoding means, thereby achieving the automatic equalization. 2. The data demodulation device according to claim 1, wherein the amount of modification of the characteristic by the means is controlled.
相ずれに起因する２軸間の相互干渉を除去する位相制御
手段と、パスメトリックの演算から生き残りパスを更新
し、かつ、復号データを決定するヴィタビ復号手段と、
このヴィタビ復号手段の出力に基づき前記位相制御手段
の特性を修正をする手段とを備えたデータ復調装置にお
いて、前記ヴィタビ復号手段での復号結果の信頼性を評
価し、これに応じて前記位相制御手段の特性の修正量を
制御することを特徴とするデータ復調装置。(4) A phase control means for removing mutual interference between two axes caused by a phase shift between the reference carrier wave and the true carrier wave used for detection, updating the surviving path from path metric calculation, and decoded data Viterbi decoding means for determining the
and a means for modifying the characteristics of the phase control means based on the output of the Viterbi decoding means, the reliability of the decoding result of the Viterbi decoding means is evaluated and the phase control A data demodulator characterized in that the amount of modification of the characteristics of the means is controlled.
施された入力変調波信号に対して、基準搬送波も用いて
２軸検波を行う復調手段からの出力信号であることを特
徴とする特許請求の範囲第４項記載のデータ復調装置。(5) The received signal is an output signal from demodulation means that performs two-axis detection using a reference carrier wave on an input modulated wave signal subjected to convolutional encoding and direct amplitude modulation. A data demodulation device according to claim 4.
リックの差に基づく帰還係数とヴィタビ復号手段の入出
力信号間の誤差とから位相制御手段への帰還量を制御し
、もって前記位相制御手段での特性の修正量を制御する
ことを特徴とする特許請求の範囲第４項記載のデータ復
調装置。(6) The amount of feedback to the phase control means is controlled from the feedback coefficient based on the difference between the smallest path metric and the second smallest path metric and the error between the input and output signals of the Viterbi decoding means, so that the phase control means 5. The data demodulation device according to claim 4, wherein the data demodulation device controls the amount of modification of the characteristic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61031831A JPS62190934A (en) | 1986-02-18 | 1986-02-18 | Data demodulating device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61031831A JPS62190934A (en) | 1986-02-18 | 1986-02-18 | Data demodulating device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62190934A true JPS62190934A (en) | 1987-08-21 |
Family
ID=12342013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61031831A Pending JPS62190934A (en) | 1986-02-18 | 1986-02-18 | Data demodulating device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62190934A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62213322A (en) * | 1986-03-13 | 1987-09-19 | Nec Corp | Operating state supervisory method of receiver having viterbi decoder |
| JPH01211373A (en) * | 1988-02-19 | 1989-08-24 | Matsushita Electric Ind Co Ltd | Digital magnetic picture recording and reproducing device |
| JPH02179127A (en) * | 1988-12-29 | 1990-07-12 | Fujitsu Ltd | Data mode pull-in system |
| JPH03250818A (en) * | 1990-02-28 | 1991-11-08 | Matsushita Electric Ind Co Ltd | Data decoder |
| EP0697696A2 (en) | 1994-08-18 | 1996-02-21 | Hitachi, Ltd. | Apparatus and method for error correction |
| WO2001091327A1 (en) * | 2000-05-25 | 2001-11-29 | Matsushita Electric Industrial Co.,Ltd. | Radio communication apparatus and radio communication method |
| DE4308000B4 (en) * | 1993-03-13 | 2006-11-30 | Robert Bosch Gmbh | Method for decision-feedback clock derivation |
| EP2031791A1 (en) * | 2007-08-30 | 2009-03-04 | Deutsche Thomson OHG | Apparatus and method for recovering data from a clocked input signal |
-
1986
- 1986-02-18 JP JP61031831A patent/JPS62190934A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62213322A (en) * | 1986-03-13 | 1987-09-19 | Nec Corp | Operating state supervisory method of receiver having viterbi decoder |
| JPH01211373A (en) * | 1988-02-19 | 1989-08-24 | Matsushita Electric Ind Co Ltd | Digital magnetic picture recording and reproducing device |
| JPH02179127A (en) * | 1988-12-29 | 1990-07-12 | Fujitsu Ltd | Data mode pull-in system |
| JPH03250818A (en) * | 1990-02-28 | 1991-11-08 | Matsushita Electric Ind Co Ltd | Data decoder |
| DE4308000B4 (en) * | 1993-03-13 | 2006-11-30 | Robert Bosch Gmbh | Method for decision-feedback clock derivation |
| EP0697696A2 (en) | 1994-08-18 | 1996-02-21 | Hitachi, Ltd. | Apparatus and method for error correction |
| WO2001091327A1 (en) * | 2000-05-25 | 2001-11-29 | Matsushita Electric Industrial Co.,Ltd. | Radio communication apparatus and radio communication method |
| US6959169B2 (en) | 2000-05-25 | 2005-10-25 | Matsushita Electric Industrial Co., Ltd. | Wireless communication apparatus and wireless communication method |
| EP2031791A1 (en) * | 2007-08-30 | 2009-03-04 | Deutsche Thomson OHG | Apparatus and method for recovering data from a clocked input signal |
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