JPS6218996Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an analog-to-digital conversion circuit, and in particular, uses an n-bit analog-to-digital (hereinafter referred to as A-D) converter to generate a pseudo n+m-bit PCM code. It is characterized by outputting . Recently, audio signals are sampled, this sampling signal is converted into digital codes by an A-D converter, and then recorded on, for example, magnetic tape.
A pulse code modulation (hereinafter referred to as PCM) recording and reproducing apparatus has appeared in which the reproduced digital code is demodulated into the original analog audio signal using a DA converter. By the way, in the method of recording and reproducing the above-mentioned digital code using a video tape recorder, the digital code is standardized to 14 bits in order to ensure mutual compatibility. Therefore, a 14-bit A-D converter is required, but a 14-bit A-D converter is very expensive. Therefore, the present invention uses a 12-bit A-D converter to simulate
The configuration is such that a 14-bit digital code output is obtained. This will be explained below with reference to the drawings. First, the principle of the present invention will be explained with reference to FIG. Now let us assume that the full scale of the 14-bit A-D converter is ±aV, and ±aV
Suppose that a signal is input. Then, the interval (D ₀
〜D ₁ ) and (D ₃ 〜D ₀ ) signals are (0, 0, 0, ×, ..., ×) {for points D ₁ and D ₃ , (0, 0, 0, 1, ... , 1)} is output. Similarly, in the case of the interval (D ₁ to D ₃ ), (0, 1, ×, ..., ×) or (0, 0,
1,×,…,×) {For point D ₂ , (0,1,…,
1)}, for the intervals (D ₀ to D ₄ ) and (D ₆ to D ₀ ), (1, 1, 1, ×, ..., ×) {for points D ₄ and D ₆ , (1, 1 ,1,0,...,0)}, in the case of the interval (D ₄ to _{D 6} ), (1,1,0,×,...,×) or (1,
0,×,…,×) {For point D ₅ , (1,0,…,
0)}. However, the MSB (most significant digit) is a sign bit that indicates the sign of the signal, and is “0” when it is positive.
When negative, it is "1". Now, if the full scale of the 12-bit A-D converter is +bV (b = a/4), then for example the interval (D ₀
~D ₁ ) (range of Y), the output for the signal is (0,
_× , _... , ), resulting in a fixed pattern. Therefore, if the signal exceeding ±bV is compressed to 1/4 (so-called 3-fold line companding method), the waveform will become as shown by the broken line in Figure 1, and the 12-bit A-D converter A-D conversion is also possible using . In this case, simply adding a companding bit (1 bit of information indicating whether or not it has been compressed) to the output (12 bits) of the 12-bit A-D converter results in a total of 13 bits, and 14 bits.
It is no longer compatible with bit A-D converters. Therefore, the present invention has a configuration in which 2 bits are added so that a pseudo 14-bit digital code is output. That is, the signals in the sections (D ₀ to D ₁ ) and (D ₃ to _{D 0} ) (signals in the Y range) are input to the 12-bit A-D converter as they are without being compressed, and are output as 12-bit signals. (0, ×,…,
0” bit pattern is added, (0, 0, 0, ×,
.
Also, the section exceeding ±bV (D ₁ to _{D 3} ) (X range)
For signals of 1/4 and 12 bit A-D
input to the converter and output 12 bits (0, 1, ×,
..., ×) or (0, 0, 1, ×, ...,
(α, β are “0” or “1” respectively) to add (0, 1, ×, ..., ×, α, β) or (0,
0, 1, ×, …, ×, α, β), then pseudo 14
A bit digital code output can be obtained.
That is, since the 13th and 14th bits are naturally unknown, they can be fixed to any code, specifically, a code that is easy to create in terms of circuitry. In this way, S/N
Although the ratio is the same as for a 12-bit A-to-D converter, the dynamic range allows a pseudo 14-bit digital code output to be obtained that has the equivalent of a 14-bit A-to-D converter. For negative signals, when adding upper bits, ie, adding a "1,1" bit pattern to signals in the sections (D ₀ to D ₄ ) and (D ₆ to _{D 0} ), 1, 1, 1, x, . . . , The above is the principle of the present invention. Next, an embodiment will be described with reference to FIGS. 2 and 3. In Fig. 2, 1 and 2 are low-pass filters that limit the bands of the L and R input signals, and 3 and 4 are sample-hold circuits that sample the input signals, and the sampling signals SL and SR are set to rise, respectively. The value of the input signal at the time of falling is held for the time TS (see Figure 3). 5 is an analog switch, and the switching signal
LR selects which signal is to be connected to the subsequent circuit. 6 is a level conversion circuit, which is a dividing resistor
It has R ₁ , R ₂ and an analog switch 7. A signal with a gain of 1 (original signal as it is) is obtained from point A, and a signal with a gain of 1/4 (a signal whose size is 1/4 of the original signal) is obtained from point B. Signal 2LR has twice the period of switching signal LR. Therefore, a signal with a gain of 1 and a signal with a gain of 1/4 are output from the level conversion circuit 6 for each of the sampled and held L and R signals. 8 is a 12-bit A-D converter that starts conversion with command signal CC, completes conversion before the next command signal CC is generated, and converts 12-bit digital data including the MSB sign bit. Output the sign. The digital code output of the signal with a gain of 1 is latched in the first latch circuit 9 with the latch pulse La1, and the digital code output of the signal with the gain 1/4 is latched in the second latch circuit 10 with the latch pulse La2. The latch outputs of the first and second latch circuits 9 and 10 are input to a data selection circuit 11. The data selection circuit 11 has 13-bit inputs A and B and receives a selection signal.
SS outputs input A or B. The 11 bits of the latch output of the first latch circuit 9 excluding the MSB (sign bit) are input to the lower 11 bits of the A input of the data selection circuit 11, and the MSB is input to the upper 2 bits of the A input. In other words, "0, 0" for a positive signal, and "1, 0" for a negative signal.
1" is added as the upper digit. On the other hand, the 11-bit latch output excluding the MSB (sign bit) of the second latch circuit 10 is input to the upper 11 bits of the B input of the data selection circuit 11, and the lower 2 bits of the B input is set to a pattern that is easy to set circuit-wise, for example, "0, 0".The data selection circuit 11 outputs a 13-bit A or B digital code in response to a selection signal SS, and this digital code (13 bits) A sign bit (the MSB of either the first or second latch circuit 9, 10) is added to the upper part, thereby obtaining a pseudo 14-bit digital code.
The content of the upper two bits excluding the MSB (sign bit) can be obtained from the content detection circuit 12 which detects the content of the upper two bits of the data. In other words, when the magnitude of the input signal is within the range of (Y,) (see Figure 1), it is sufficient to select the output of the first latch circuit 9; The 12-bit A-D conversion output of the signal obtained by compressing the input signal by 1/4, that is, the upper 2 bits excluding the MSB of the output of the second latch circuit 10, becomes "0, 0" when the input signal is positive. , if it is negative, it will be "1, 1", so by checking the higher-order contents, the selection signal SS can be created. Therefore, the MSB of the second latch circuit 10 is inverted by the inverter 13 and is input to one of the two exclusive OR circuits 14 and 15, and the output of the upper two bits excluding the MSB of the second latch circuit 10 is If the outputs of the exclusive OR circuits 14 and 15 are used as the other inputs of the circuits 14 and 15, the output of the AND gate 16 is such that the input signal is (Y,
) becomes high level only when within the range. Therefore, if this high level output is input to the flip-flop circuit 17 and read out using the selection pulse SP, Q
The output becomes the selection signal SS. That is, the selection signal SS
When is at a high level, it is sufficient to select the output of the first latch circuit 9. FIG. 4 shows an embodiment having another selection signal generating circuit. That is, in this case, the level detection circuit 1 detects the level of the input signal in an analog manner.
A selection signal SS is created from 2'. This is the inverted level l ₁ (see FIG. 1) of the first comparator 18, and its output is at H level only when the sampled and held signal is within range X, and at L level otherwise. The inversion level of the second comparator 19 is l ₂ (see FIG. 1), and its output is at H level only when the signal is within the range, and at L level otherwise. Therefore, the output of the exclusive OR circuit 20 becomes L level when the signal is within the range (Y,), and becomes H level when the signal is within the range (X,). Therefore, exclusive OR circuit 2
If the output of 0 is input to the flip-flop circuit 21 and latched in synchronization with the switching signal 2LR, then this latch output (Q output) is input to the flip-flop circuit 22 and read out using the selection pulse SP. ,
A selection signal SS (Q output) can be obtained. According to the present invention described above, for example, a 12-bit A-D converter is used to create a pseudo 14-bit A-D converter.
To obtain the D conversion output, a first latch circuit latches the A-D conversion output in a gain state of 1, and a second latch circuit latches the A-D conversion output in a gain 1/4 state. Since the circuit is provided separately, when creating additional bits, the first
For the output of the latch circuit, the same bits as the sign bit are added as the upper 2 bits, and for the output of the second latch circuit, arbitrary bits (bits that are easy to set in terms of the circuit, such as 0 bit) are added to the lower 2 bits. ) can be added, making it extremely easy to create additional bits. Incidentally, Japanese Patent Application Laid-Open No. 140464/1983 discloses a technique for obtaining an m+n bit digital code using an n-bit encoder (A-D converter), but in the case of this conventional technique, additional The m bits used are volume control bits, which are completely different in nature from the n-bit PCM code, which indicates the magnitude corresponding to the input analog signal. Therefore, such an m+n bit digital signal is not compatible with the m+n bit A/D converter output (PCM code). However, according to the present invention, although it is pseudo, n+
The invention of the present invention is more advantageous in this respect because it is possible to obtain an m-bit PCM code and is compatible. Also, to formally obtain a 14-bit PCM code using a 12-bit A-D converter, it is sufficient to add 2 additional bits to the upper or lower side of the 12 bits, but this is not possible. You can only get the same dynamic cleanliness as 12-bit. In contrast, in the present invention, when the input signal level is large, it is compressed and converted into a 12-bit A-D converter, and then 2 additional bits are added to the lower side, while when the input signal level is small, it is converted as is. Since the configuration is such that 12-bit AD conversion is performed and 2 additional bits are added on the upper side, a dynamic range comparable to that of 14-bit AD conversion can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a signal waveform diagram for explaining the principle of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the -D conversion circuit according to the invention, Fig. 3 is a timing chart, and Fig. 4 is a diagram of other embodiments. It is a circuit diagram showing an example of. 6 ...Level conversion circuit, 8...A-D converter,
9, 10...first and second latch circuits, 11...data selection circuit, 12 ...content detection circuit, 12 '...
...Level detection circuit, SS...selection signal.

Claims (1)

[Claims for Utility Model Registration] (1) A level conversion circuit that converts the level of an input analog signal and outputs it, and an n-bit analog-to-digital converter that converts the input analog signal and the output of the level conversion circuit into digital values. The vessel and
a first latch circuit that latches the digital conversion output of the unlevel-converted analog signal output from the analog-to-digital converter; and a digital conversion of the level-converted analog signal output from the analog-to-digital converter. A second latch circuit that latches the output, and when the latch output of either one of the latch circuits is selected by the selection signal and the output of the first latch circuit is selected, the upper digit is m-bit "0" or When m bits "1" are added and the output of the second latch circuit is selected, m bits of arbitrary bits are added as lower digits, thereby forming a data selection circuit that outputs a digital output of n+m bits. , so that n+m corresponding to the input analog signal is selected from the data selection circuit.
An analog-to-digital conversion circuit characterized by obtaining a bit PCM code. (2) The analog-to-digital converter circuit according to claim 1, which is registered as a utility model, and has a structure in which the selection signal is generated by a level detection circuit that detects the level of an analog signal. (3) The analog-to-digital converter circuit according to claim 1, which is registered as a utility model and has a structure in which the selection signal is generated by a content detection circuit of the upper two bits of the second latch circuit.