JPS6218810A - Primary delay equalizing circuit - Google Patents

Primary delay equalizing circuit

Info

Publication number
JPS6218810A
JPS6218810A JP15751285A JP15751285A JPS6218810A JP S6218810 A JPS6218810 A JP S6218810A JP 15751285 A JP15751285 A JP 15751285A JP 15751285 A JP15751285 A JP 15751285A JP S6218810 A JPS6218810 A JP S6218810A
Authority
JP
Japan
Prior art keywords
primary delay
filter
temperature
delay time
equalizers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15751285A
Other languages
Japanese (ja)
Inventor
Tomiyuki Kume
久米 富幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15751285A priority Critical patent/JPS6218810A/en
Publication of JPS6218810A publication Critical patent/JPS6218810A/en
Pending legal-status Critical Current

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  • Filters And Equalizers (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To equalize primary delay time characteristics of a filter over a wide temperature range by constituting primary delay equalizers which have a positive and a negative gradient including a varactor diode and varying the capacity value of this diode, i.e. Q of the circuit according to ambient temperature. CONSTITUTION:The filter consists of the primary delay equalizer 3 which has the positive gradient, the primary delay equalizer 4 which is connected thereto and has the negative gradient, and a control circuit 5 which controls the gradients of the equalizers 3 and 4 according to temperature variation. The equalizers 3 and 4 are each composed of a coil and a capacitor, but include varactor diodes 3-1 and 4-1 respectively; and the Q of the filter is varied by varying the capacities of the diodes. Further, the control circuit 5 incorporates a temperature compensating sensor 5-1 using a Schottky diode and an output voltage corresponding to the temperature is applied to the varactor diode 3-1 through an amplifier 5-2 and an amplifier 5-3 and further applied to the varactor diode 4-1 through an inversion circuit 6. Consequently, the positive and negative gradients of the two primary delay equalizers vary with the ambient temperature and the primary delay time of the filter is equalized over a wide temperature range.

Description

【発明の詳細な説明】 〔概要〕 一次遅延等化回路において、正及び負の傾斜を持つ一次
遅延等化器3及び4を可変容量ダイオードを含んで構成
し、周囲温度に対応してこのダイオードの容量値即ち回
路のQを変化させる様にした。これにより、伝送路に生
じた負又は正の一次遅延時間特性を広い温度範囲に渡っ
て等化することができ、誤り率の劣化が改善される。
Detailed Description of the Invention [Summary] In the first-order delay equalization circuit, the first-order delay equalizers 3 and 4 having positive and negative slopes are configured to include variable capacitance diodes, and the diodes are adjusted according to the ambient temperature. The capacitance value, that is, the Q of the circuit is changed. As a result, negative or positive primary delay time characteristics occurring in the transmission path can be equalized over a wide temperature range, and deterioration in error rate can be improved.

〔産業上の利用分野〕[Industrial application field]

本発明は例えばマイクロ波無線方式に使用する一次遅延
等化回路の改良に関するものである。
The present invention relates to an improvement in a first-order delay equalization circuit used, for example, in a microwave radio system.

第6図はフィルタの周波数特性及び遅延時間特性の温度
変化図を示し、[a)は常温の場合を、(b)は高温又
は低温の場合を示す。
FIG. 6 shows temperature change diagrams of the frequency characteristics and delay time characteristics of the filter, where [a] shows the case at room temperature, and (b) shows the case at high or low temperature.

第6図(a)に示す様すフィルターは例えば導波管タイ
プのもので、常温ではf1〜f2の伝送帯域内に於いて
遅延時間特性はほぼ二次遅延時間特性になっている。
The filter shown in FIG. 6(a) is, for example, a waveguide type filter, and at room temperature, the delay time characteristic in the transmission band f1 to f2 is approximately a second-order delay time characteristic.

しかし、周囲温度が常温よりも高く又は低くなると周波
数特性が左右にシフトするので、遅延時間特性は形状が
殆ど変化しない二次遅延時間特性に、正又は負の傾斜を
持つ一次遅延時間特性が加わったものとなる。
However, when the ambient temperature is higher or lower than room temperature, the frequency characteristics shift to the left or right, so the delay time characteristics have a primary delay time characteristic with a positive or negative slope added to a secondary delay time characteristic whose shape hardly changes. It becomes something.

一方、近年は周波数の利用効率を向上させる為に、例え
ば多値振幅変調方式等が用いられる傾向があるが、この
様な方式に対しても遅延時間特性の規格を満足できる一
次遅延等他罪が要望されている。
On the other hand, in recent years, there has been a tendency to use, for example, multilevel amplitude modulation methods to improve frequency utilization efficiency, but such methods also have other disadvantages such as primary delay that can satisfy the delay time characteristic standards. is requested.

〔従来の技術〕[Conventional technology]

第7図は従来例のブロック図を示す。 FIG. 7 shows a block diagram of a conventional example.

図において、端子INから入力したマイクロ波は例えば
導波管タイプのフィルタ1で希望波のみが抽出された後
、増幅や周波数変換等が行われて中間周波帯の信号に変
換され線輪やコンデンサで構成された一次遅延等他罪2
に加えられる。この等他罪2は常温時のフィルタ1の一
次遅延時間特性を等化する様になっているので一次分が
等化された後、二次遅延等他罪で二成分が等化されて遅
延歪の減少した中間周波信号が端子OUTより送出され
る。
In the figure, the microwave input from the terminal IN is extracted by a waveguide type filter 1, for example, to extract only the desired wave, and then amplified, frequency converted, etc., and converted to an intermediate frequency band signal. Other offenses such as primary delay, etc., consisting of
added to. This other sin 2 is designed to equalize the primary delay time characteristic of the filter 1 at room temperature, so after the first component is equalized, the two components are equalized and delayed due to other sins such as secondary delay. An intermediate frequency signal with reduced distortion is sent out from the terminal OUT.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、一次遅延等化器は常温でフィルタの一次遅延時
間特性を等化する様に調整されているので、第6図(b
)に示す様に周囲温度が変化して一次遅延時間特性が変
化した時はこれを等化する事が出来なくなる。
However, since the primary delay equalizer is adjusted to equalize the primary delay time characteristics of the filter at room temperature, the
), when the ambient temperature changes and the primary delay time characteristics change, it becomes impossible to equalize them.

第8図は第7図の動作説明図を示す。FIG. 8 shows an explanatory diagram of the operation of FIG. 7.

第8図(a)は周囲温度が常温の時の等化を示している
が、一次遅延等化器(図中のEQL)の等化特性がフィ
ルタ(図中のフィルタ)の−次遅延時間特性を補償する
様になっているので、等化が充分に行われ(図中の合成
)遅延時間特性は平坦になり遅延歪は生じない。
Figure 8(a) shows equalization when the ambient temperature is room temperature, and the equalization characteristic of the first-order delay equalizer (EQL in the figure) is the -order delay time of the filter (filter in the figure). Since the characteristics are compensated for, equalization is sufficiently performed (composition in the figure), and the delay time characteristics become flat and no delay distortion occurs.

しかし、(b)及び(C1に示す様に高温又は低温の場
合にはフィルタの一次遅延時間特性の傾斜が、例えばよ
り急になり又は逆になるが、一次遅延等化器EQLの一
次遅延時間特性は例えば正の傾斜でしかも殆ど変化しな
いのでフィルタで生じた一次遅延時間特性を充分に補償
する事はできない。
However, as shown in (b) and (C1), when the temperature is high or low, the slope of the filter's primary delay time characteristic becomes steeper or vice versa, but the primary delay time of the primary delay equalizer EQL is For example, since the characteristic has a positive slope and hardly changes, it is not possible to sufficiently compensate for the primary delay time characteristic caused by the filter.

これは、温度変化による中心周波数foのずれΔfはΔ
f =foX温度変動比で示されるが、温度変動比を一
定とするとfoが高い程Δfが高くなり遅延時間特性へ
の影響が大きくなる事を示すが、f。
This means that the deviation Δf of the center frequency fo due to temperature change is Δ
It is shown as f=foX temperature fluctuation ratio, but if the temperature fluctuation ratio is constant, the higher fo is, the higher Δf is, indicating that the influence on the delay time characteristics is greater, but f.

の低い一次遅延等化器はフィルタよりも温度変化の影響
を受けない為である。
This is because a first-order delay equalizer with a low value is less affected by temperature changes than a filter.

この為、ディジタル信号を伝送する際に誤り率が劣化す
ると云う問題点がある。
For this reason, there is a problem in that the error rate deteriorates when transmitting digital signals.

〔問題点を解決する為の手段〕[Means for solving problems]

上記の問題点は、第1図に示す様に正の傾斜を持つ一次
遅延等他罪3と、該一次遅延等化器に接続され、負の傾
斜を持つ一次遅延等他罪4と、温度変化に対応して該一
次遅延等化器3.4の傾斜を制御する制御回路5とから
構成された本発明の一次遅延等化回路により解決される
The above problem consists of a first-order delay etc. 3 which has a positive slope as shown in FIG. 1, a first-order delay etc. 4 which is connected to the primary delay equalizer and has a negative slope, and a temperature This problem is solved by the first-order delay equalizer circuit of the present invention, which comprises a control circuit 5 that controls the slope of the first-order delay equalizer 3.4 in response to the change.

〔作用〕[Effect]

本発明は、第2図に示す様に例えば正の傾斜を持つ一次
遅延等化器3の遅延時間特性のピークを周波数f2に、
負の傾斜を持つ一次遅延等化器4の遅延時間特性のピー
クが周波数f1に来る様に調整し、それぞれの等他罪に
含まれる可変容量ダイオードの容量を変化させる様にし
た。これにより、Q即ち正、負の傾斜が変化する。
In the present invention, as shown in FIG. 2, for example, the peak of the delay time characteristic of the first-order delay equalizer 3 having a positive slope is set to the frequency f2,
Adjustments were made so that the peak of the delay time characteristic of the primary delay equalizer 4 having a negative slope would be at the frequency f1, and the capacitance of the variable capacitance diode included in each equalizer was changed. This changes the Q, that is, the positive and negative slopes.

そこで、制御回路5より温度変化に対応する出力でQを
制御すれば広い温度範囲に渡ってフィルタの一次遅延時
間特性を補償する事ができ、誤り率の劣化を改善する事
ができる。
Therefore, if Q is controlled by the control circuit 5 using an output corresponding to temperature changes, the primary delay time characteristics of the filter can be compensated over a wide temperature range, and the deterioration of the error rate can be improved.

〔実施例〕〔Example〕

第3図は本発明の実施例のブロック図を、第4図は制御
回路の制御特性図、第5図は第3図の動作説明図を示す
FIG. 3 is a block diagram of an embodiment of the present invention, FIG. 4 is a control characteristic diagram of the control circuit, and FIG. 5 is an explanatory diagram of the operation of FIG. 3.

第3図に示す様に一次遅延等他罪3.4は線輪及びコン
デンサで構成されているが、それぞれ可変容量ダイオー
ド(例えば5〜25pf)3−1.4−1が含まれ、こ
の容量を変化させるとQが変化する。
As shown in Fig. 3, the primary delay etc. 3.4 is composed of a coil and a capacitor, each of which includes a variable capacitance diode (for example, 5 to 25 pf) 3-1.4-1, and this capacitance When Q changes, Q changes.

又、制御回路5にショットキー・ダイオードを用いた温
度補償センサ5−1が入っている。このダイオードの電
圧降下は約−2,3mν/”cで変化するので、温度に
対応した出力電圧が増幅器5−2より得られ、これを増
幅器5−3で電圧変換して可変容量ダイオードに加える
。更に、一次遅延等化器3と4の傾斜の温度変化を第4
図に示す様に制御する為に増幅器5−3の出力を反転回
路6を介して可変容量ダイオード4−1に加える。
Further, the control circuit 5 includes a temperature compensation sensor 5-1 using a Schottky diode. Since the voltage drop across this diode changes at approximately -2.3mν/"c, an output voltage corresponding to the temperature is obtained from the amplifier 5-2, which is converted into voltage by the amplifier 5-3 and applied to the variable capacitance diode. .Furthermore, the temperature change of the slopes of the first-order delay equalizers 3 and 4 is
As shown in the figure, the output of the amplifier 5-3 is applied to the variable capacitance diode 4-1 via the inverting circuit 6 for control.

この様な制御を行うと、第5図に示す様に2つの一次遅
延等花器の正、負の傾斜(第4図中のEQL−2,EQ
L−1)が周囲温度に対応して変化し、第4図に示す様
に広い温度範囲に渡ってフィルタの一次遅延時間を等化
することができる。
When such control is performed, as shown in Fig. 5, the positive and negative slopes of the vase (EQL-2, EQ in Fig. 4) are
L-1) changes in response to the ambient temperature, and the primary delay time of the filter can be equalized over a wide temperature range as shown in FIG.

実際の調整には遅延時間測定器で全体の遅延時間特性を
ブラウン管上に表示させ、周囲温度をかえてそれが平坦
になる様に可変抵抗器5−4を調整(Qを変化させる)
すればよい。
For actual adjustment, use a delay time measuring device to display the entire delay time characteristic on the cathode ray tube, and adjust the variable resistor 5-4 (by changing the Q) so that it becomes flat by changing the ambient temperature.
do it.

向、Qを変化させる代わりにコンデンサ3−3.3−4
を可変容量ダイオードで置換して容量値を変化させると
f 1.f 2が変化するので等測的に傾斜を変える事
ができる。
Capacitor 3-3.3-4 instead of changing direction, Q
When replacing the capacitance with a variable capacitance diode and changing the capacitance value, f1. Since f2 changes, the slope can be changed isometrically.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明した様に、フィルタの一次遅延時間時間
特性を広い温度範囲にわたり等化できるのでg% ’l
率の劣化を改善する事ができると云う効果がある。
As explained in detail above, since the filter's primary delay time characteristics can be equalized over a wide temperature range, g% 'l
This has the effect of improving the rate deterioration.

【図面の簡単な説明】[Brief explanation of the drawing]

第4図は制御回路の制御特性図、 第5図は第3図の動作説明図、 第6図はフィルタの周波数及び遅延時間特性の温度変化
図、 第7図は従来例のブロック図、 第8図は第7図の動作説明図を示す。 図に於いて、 3.4は一次遅延等化器、 5は制御回路を示す。 hj図司動作説明図 第 212] A全BF4めf施づ夕すtワフ”D・ン2gり第 3 
図 キ・1蓚PロilJ°lデ即牙キ十ま二迂コ第4 図 第′3図(動作3先四図 45 図 マイクO男ド和         甲a’を周R帝ルL
釆脅・1.jl)′口・・ツク図 第 7  図
Fig. 4 is a control characteristic diagram of the control circuit, Fig. 5 is an explanatory diagram of the operation of Fig. 3, Fig. 6 is a temperature change diagram of the frequency and delay time characteristics of the filter, Fig. 7 is a block diagram of the conventional example, FIG. 8 shows an explanatory diagram of the operation of FIG. In the figure, 3.4 is a primary delay equalizer, and 5 is a control circuit. hj Zuji movement explanation diagram No. 212]
Figure 1 Figure 1 P Roil J°l De Sokuga Ki 10 Ma 2 Round Figure 4 Figure '3 (Movement 3 forward 4 Figure 45 Figure Mike O man do sum Aa' Zhou R Emperor L
Threat ・1. jl)'口...Tsuku diagram Figure 7

Claims (1)

【特許請求の範囲】  正の傾斜を持つ一次遅延等化器(3)と、該一次遅延
等化器に接続され、負の傾斜を持つ一次遅延等化器(4
)と、 温度変化に対応して該一次遅延等化器(3、4)の傾斜
を制御する制御回路(5)とから構成された事を特徴と
する一次遅延等化回路。
[Claims] A first-order delay equalizer (3) with a positive slope; a first-order delay equalizer (4) connected to the first-order delay equalizer and with a negative slope;
); and a control circuit (5) that controls the slope of the primary delay equalizer (3, 4) in response to temperature changes.
JP15751285A 1985-07-17 1985-07-17 Primary delay equalizing circuit Pending JPS6218810A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15751285A JPS6218810A (en) 1985-07-17 1985-07-17 Primary delay equalizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15751285A JPS6218810A (en) 1985-07-17 1985-07-17 Primary delay equalizing circuit

Publications (1)

Publication Number Publication Date
JPS6218810A true JPS6218810A (en) 1987-01-27

Family

ID=15651294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15751285A Pending JPS6218810A (en) 1985-07-17 1985-07-17 Primary delay equalizing circuit

Country Status (1)

Country Link
JP (1) JPS6218810A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003168944A (en) * 2001-11-29 2003-06-13 Nec Corp Equalizer circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003168944A (en) * 2001-11-29 2003-06-13 Nec Corp Equalizer circuit

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